JP2001305191A - Test method for semicondcutor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for conducting a production test considering failure by the effect of cross talk and make the production test pattern considering the failure by the effect of cross talk with a minimum number of patterns. SOLUTION: A net list 1 fulfilling a logic function is input, a scan path test structure is installed (S1) and the net list is layout in a mask pattern (S2). Danger locations apt to be affected by the cross talk in the layout are extracted (S3) and to the extracted danger locations, test circuits are added (S4) to form test patterns apt to be affected by the cross talk with a gate delay ATPG. A production test is conducted (S6, 7) by using the test pattern produced by applying the gate delay ATPG (S5) on the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit (I).
The present invention relates to a test method of a semiconductor integrated circuit which is not suitable for the test method C), and in particular, in a test step for detecting a failure of an IC, a failure of the semiconductor integrated circuit due to the influence of crosstalk noise can be eliminated by adding a small test pattern.

[0002]

2. Description of the Related Art In the development of semiconductor integrated circuits, in recent years, the process has been miniaturized, and the degree of integration and performance have been further increased. In such a situation, it is often a problem because the influence of crosstalk noise is likely to occur.

The influence of the crosstalk is as follows: (1) As the wiring length of the adjacent wiring becomes longer, (2) The wiring interval becomes narrower, (3) The difference in the performance of the driver, and (4) The higher the capacity ratio, the easier it is to receive. In addition, when an operation is performed in which one of the adjacent wirings simultaneously rises and one of the adjacent wirings falls, the delay value increases. When the same change occurs at the same time, the effect of the crosstalk appears that the delay value decreases. In addition, when one of the adjacent wirings has a fixed value, and even if only one of the wirings changes, the drive capability of the fixed-value wiring is lower than that of the changing wiring, and the ratio of the inter-wiring capacitance among the wiring capacitance is high. In the case of, there is an effect of crosstalk that noise is generated in a fixed value signal, which leads to malfunction.

With respect to the influence of the crosstalk, design verification is performed by performing delay verification and function verification in consideration of the effects of delay variation and noise at the circuit design stage of a semiconductor integrated circuit. On the other hand, in a manufacturing test, a test pattern created by a gate delay ATPG using a scan path is used for testing a semiconductor integrated circuit that fails due to a delay.

A pattern created by the gate delay ATPG will be described using the OR gate circuit in the circuit diagram of FIG. The OR circuit 40 receives input signals from input terminals A and B and obtains an output signal from an output terminal X. In this case, in order to detect a rising gate delay failure at the output terminal X, the gate delay ATPG tool performs an OR operation to bring the output terminal X into a rising state.
The input terminal A and the input terminal B of the gate are:
2) The input terminal A rises and the input terminal B also rises. 3) The input terminal A is fixed at 0 and the input terminal B rises.
An attempt is made to create a pattern for setting the type of state, and one pattern that can be easily set to that state is selected and created.

[0006]

In the pattern generated by such a mechanism, it is determined whether or not a pattern in which both adjacent wirings, which are affected by crosstalk, change at the same time or change at the same time is included. I don't know. For this reason,
In manufacturing tests, failures due to the effects of crosstalk could only be removed accidentally.

Another technique is a gate delay ATP.
When a pattern is generated in G, all possible input combinations are generated as a pattern, and a manufacturing test is performed using the pattern to remove a semiconductor integrated circuit that fails due to the influence of crosstalk. Had been. In this method, at the input terminals A and B of the OR gate in FIG. 8, 32 combinations of 2 4 power gate delay test patterns are required, and this is necessary for all terminals of the circuit. There is a problem that an enormous number of test patterns are required in order to consider the influence of crosstalk during a manufacturing test because a number of powers of a number is required.

An object of the present invention is to make it possible to carry out a manufacturing test in which a failure due to the influence of crosstalk is taken into consideration and to create a production test pattern with a minimum number of patterns in consideration of a failure due to the influence of crosstalk. A test method for a semiconductor integrated circuit is provided.

[0009]

A test method for a semiconductor integrated circuit according to the present invention comprises the steps of: inputting a netlist satisfying a logical function; creating a scan path test structure; laying out the netlist with a mask pattern; A danger point where the influence of crosstalk is likely to appear in the layout is extracted, and a test pattern in which the influence of crosstalk appears at the extracted danger point is gated ATP.
It is characterized in that a test circuit is added in order to create a G, and a manufacturing test is performed using a test pattern generated by performing a delay ATPG in the circuit.

In the present invention, a netlist satisfying a logical function is input, a scan path test structure is created,
Step 1 for improving controllability and observability by adding a scan FF or an external terminal to a portion where the controllability and observability of each signal line in the netlist to 0 and 1 are not sufficient.
Inputting a netlist satisfying the logical function into which the scan path has been inserted, and performing a mask pattern layout step 2; extracting adjacent wiring locations affected by crosstalk noise; and inputting the extracted logical gate. Using a gate delay ATPG tool, a test circuit for changing the signal value, which is likely to cause crosstalk noise, using a gate delay ATPG tool. Step 4 of adding to the list, and step 5 of using the test circuit of step 4 with the gate delay ATPG tool to generate a test pattern that converts the input of the logic gate extracted in step 3 to a signal value that is likely to cause crosstalk noise. And the expected value at the external terminal of the test circuit added in step 5 is deleted Step 6 of the test pattern modifications that that may include a step 7 for testing a semiconductor integrated circuit by a test pattern that is modified in step 6.

In the present invention, the extraction of the adjacent wiring at the danger point is performed by extracting the wiring capacitance and the wiring length of each wiring, calculating the capacitance between the adjacent wirings, and calculating the capacitance between the adjacent wirings exceeding a predetermined reference value. From the back trace results of the clock terminals of all the flip-flops, the same drive source flip-flops are divided into groups, and the adjacent wirings in the same group that have a synchronous relationship are extracted and performed. The difference between the drive capacities of the wirings having a smaller drive capacity than the reference value and the ratio of the inter-wiring capacity among the wiring capacities of the wirings having the smaller drive capacity exceeds a predetermined reference value can be taken out.

Therefore, by testing a semiconductor integrated circuit by using the present invention, it is possible to eliminate a failure of the semiconductor integrated circuit due to the influence of crosstalk noise by adding a small number of test patterns.

[0013]

FIG. 1 is a flowchart of a test method for explaining an embodiment of the present invention. Referring to FIG. 1, a scan path is inserted with a netlist 1 satisfying a desired logic function as an input, and at the same time, a test circuit is added for a portion having poor control and observability (step S1), and a mask pattern layout process is performed. Mask pattern data is created (step S2). Using the placement and routing results,
An adjacent wiring that is easily affected by crosstalk noise is extracted as a dangerous part (step S3) and recorded in the dangerous part net file 7. With respect to the extracted signal, a test circuit for generating a test pattern easily affected by crosstalk noise is added to the netlist 2 created in step S1 by a gate delay ATPG tool (step S4). At this time, the test circuit is added only to the netlist 2 and is not reflected in the layout mask pattern.

Next, a test pattern is created using the gate delay ATPG tool for the netlist 2 to which the test circuit has been added. In the next step, a test pattern correction process of deleting an expected value for a terminal added as a test circuit that does not exist in the semiconductor integrated circuit itself is performed (step S5), and a test is performed (step S5).
6). The files 3 to 7 are files for storing respective information in the middle of each step.

Next, a description will be given of the dangerous spot extraction processing which is susceptible to crosstalk noise in step S3. FIG.
In order to check the influence of the crosstalk noise from the layout result, the wiring capacitance of each wiring (step S11) and the length of the adjacent wiring are extracted (step S12), and the capacitance between adjacent wirings for each wiring is determined. The calculation is performed (step S13). Next, the reference value of the predetermined delay time delay due to the crosstalk noise and the capacitance between adjacent wirings causing a malfunction is compared with the capacitance between adjacent wirings obtained in step S13, and the adjacent wiring (Y) exceeding the reference value is extracted. (Step S14), the adjacent wiring (N) that does not exceed the reference value is stored in the dangerous location net file 7, and is recorded in the non-target file 8.

Next, using the netlist 2 of FIG. 1, the back trace is performed from the clock, set and reset terminals of all the FFs in the netlist until reaching the external input terminal and the logic gate. Reset, set signal,
Further, the names of clock signals to be arranged and wired so as not to be affected by crosstalk noise in advance are extracted (step S15).

At the same time, all flip-flops (FFs) are extracted in order to extract adjacent wirings in which delay fluctuations are likely to occur due to the influence of crosstalk noise and in which simultaneous fluctuations may occur.
From the back trace result of the clock terminal, grouping is performed such that the FFs that are the same drive source belong to the same group (step S16).

Next, the adjacent wiring extracted in step S4 is back-traced on the netlist 2 created in step S1 until it reaches an external terminal or FF, and a drive source is extracted (step S17). . Finally, the adjacent wiring extracted in step S14 is used in step S15.
Is not the signal name extracted in step S16 and
Using the FF grouping information created in the above, it is checked whether or not the adjacent wires are in a synchronous relationship by checking whether or not the drive source of the adjacent wires belongs to the same group (step S18). Adjacent wiring (Y) to be extracted and stored in the dangerous place net file 7,
The adjacent wiring (N) that is not in a synchronous relationship is recorded in the non-target file 8. .

Next, a driver of an adjacent wiring is searched to extract a portion where an adjacent wiring is formed by a wiring having a weak driving capability and a wiring having a high driving capability, in which a malfunction due to the influence of crosstalk is likely to occur. (Step S1
9). In step S20, the drive capacities of the respective drivers are compared, and if there is a difference in the drive capacities exceeding a preset reference value, step S21 is performed.
Then, for the wiring having the smaller drive capability, the ratio of the wiring capacity occupied by the wiring capacity obtained in step S11 and the wiring capacity obtained in step S13 is calculated.

Next, in step S22, when the ratio of the capacitance between the wirings exceeds the preset reference ratio, the adjacent wiring is determined to be susceptible to the crosstalk noise, and the dangerous location net file is determined as the dangerous location. 7 is stored.

Next, step S4 of FIG. 1 will be described with reference to the block diagram of FIG. 3 and the circuit diagram of FIG. In FIG. 3, functional blocks 31 to 34 are provided in a mask pattern 30 of a semiconductor integrated circuit, and target wirings 11 and 12 are provided between a functional block 31 and a functional block 34.
Is provided.

In the circuit shown in FIG. 4, the test circuit 10 tests the adjacent wirings 11 and 12, and shows that the output signal 15 of the test circuit 10 is output from the external terminal 13. The adjacent wirings 11 and 12 are adjacent wirings that are likely to be affected by the crosstalk noise extracted in step S3 of FIG. A test circuit 10 is added for the purpose of generating a test pattern in which the value of this signal is affected by an increase in delay due to crosstalk noise, in which a signal on the adjacent wiring 11 rises and a signal on the adjacent wiring 12 falls.

The test circuit 10 is connected to the adjacent wiring 1 at the same time.
The circuit specification is such that the output signal 15 rises in an input combination in which the signal 1 rises and the signal on the adjacent wiring 12 falls. With this circuit configuration, if a pattern is generated by the gate delay ATPG tool in step S5 in FIG. 1, a pattern for detecting the rising gate delay failure of the output signal 15 using the external terminal 13 to which the gate delay failure has been added is created. The output signal 15 which is affected by the increase in delay due to the talk noise rises, and the wiring 1
A pattern is created in which the signal 2 falls. In this case, the expected values are the terminal 13 added as the test circuit 10 in FIG.
Is generated at all of the external terminals affected.

The operation of this embodiment will be described. A scan path is inserted into the netlist having a logical function in step S1 in FIG. 1, and a circuit as shown in a block diagram in FIG. 5 is inserted into a portion where the controllability of the signals 0 and 1 is poor. As the test circuit, a flip-flop (hereinafter referred to as F / F) 22,
24 and F / Fs 26 and 27 synchronized with the clock signal 29
And a synchronization circuit 28 dependent on these F / Fs 26 and 27.
Then, a circuit including selectors 23 and 25 for switching the output of the synchronization circuit 28 and the outputs of the F / Fs 22 and 24 according to the test mode of the test signal 21 is inserted. By such a circuit, 100% controllability of the control of the signals 0 and 1 of the wirings 11 and 12 in FIG. 5 is ensured during the scan path test.

The netlist 2 into which the scan path has been inserted in step S1 in FIG. 1 is subjected to a mask pattern layout in step S2 in FIG. 1, and a mask pattern 30 of the semiconductor integrated circuit as shown in FIG. 3 is created. You.
Subsequently, a dangerous spot extraction process that is easily affected by crosstalk noise in step S3 in FIG. 1 is performed. The adjacent wiring length is calculated in step S11 of FIG.
Based on the wiring length calculated in step S12, the capacitance between adjacent wirings is calculated and compared with a reference value of the capacitance between wirings that fluctuates according to a process set in advance by a designer.
, An adjacent wiring exceeding a reference value is extracted.

In this embodiment, the mask pattern 40 shown in FIG.
The operation will be described by taking as an example a case where the adjacent wirings 11 and 12 are extracted as candidates. FIG. 5 is an enlarged view of the adjacent wirings 11 and 12 from the functional block 31 to the functional block 34 in FIG.
Only relevant wiring is described, and others are not described. The wirings 11 and 12 in FIG. 3 correspond to the wirings 11 and 12 in FIG.

In step S1 of FIG. 1, the netlist 2 into which the scan path is inserted is input, and the clock is input from the clock terminals, set and reset terminals of all the FFs in the netlist to the logic gate, or the external input terminal 13 The back trace is performed until the signal reaches the FF or reaches the FF, and the net in the middle of the trace is registered as a clock and reset wiring.
At the same time, the FFs are grouped for each logic gate at the root of the clock obtained by back-trace from the clock terminal or for each external input terminal. Next, in step S16 of FIG. 2, the wiring whose capacitance between the wirings extracted in step S12 exceeds the reference value is back-traced until it reaches the external input terminal or reaches the FF, and the drive source terminal of the adjacent wiring Alternatively, FF is extracted.

In step S17, step S14
It is determined whether the signal name is not the signal name extracted in step 2 and whether the drive source FF belongs to the same group.
It extracts not the set and reset signals but the adjacent wirings that operate in synchronization. The wiring 11 and the wiring 12 in FIG.
27, which is extracted as a dangerous spot.

Subsequently, in step S4 in FIG. 1, a test is performed to generate a test pattern in which the signal on the wiring 11 in FIG. 5 rises and the signal on the wiring 12 falls so that the delay increases due to the influence of crosstalk. The circuit 10a is added. The test circuit 10a is a circuit in which the output signal Y rises when the input signal A rises and the input signal B falls.

FIG. 6 shows test mode signals (TM1, TM2) from input terminals 17, 18 of this test circuit 10a.
Is a truth table of a test circuit which receives as input and outputs output signals 15, 16 (X, Y).

The netlist to which the test circuit is added in step S4 of FIG. 1 is generated in step S5 of FIG. 1 by a gate delay failure detection test pattern generated by the gate delay ATPG tool. In a pattern for detecting a rise failure, a pattern is easily generated in which signals of the wirings 11 and 12 are likely to have an influence of desired crosstalk.

Next, in step S6 of FIG.
Test mode from input terminals 17 and 18 of output signal 1
5. Delete the pattern of 16. The manufacturing test in step S7 in FIG. 1 is performed using the test pattern modified in step S6 in FIG.

FIG. 7 shows another embodiment of the present invention. Although the basic configuration is as described above, the danger spot extraction processing which may malfunction due to the influence of crosstalk in step S3 in FIG. 1 is devised. This shows the flow that is performed. Steps 15 to 18 are deleted from FIG.

In this case as well, the wiring capacity of each wiring is calculated in step S11, and in steps S12 to S14, as in the above-described embodiment, the adjacent wiring whose adjacent wiring capacity exceeds the specified reference value is extracted. Next, step S
In step 17a, the adjacent wiring extracted in step S14 is back-traced until the adjacent wiring reaches the logic gate, and the driver of the relevant adjacent wiring is extracted. In step S20, the drive capacities of the respective drivers are compared. If there is a difference in the drive capacities exceeding a preset reference value, in step S21, the wiring capacity obtained in step S12 is determined for the wire having the smaller drive capacity. Then, the ratio occupied by the interwiring capacitance is calculated from the interwiring capacitance obtained in step S13. Next, in step S22, when the ratio of the capacitance between the wirings exceeds a preset reference value, the adjacent wiring is recognized as a dangerous point as being susceptible to the crosstalk noise.

Therefore, the manufacturing test method using the dangerous part extraction processing is also effective in detecting a fault in which the influence of crosstalk does not affect the delay due to simultaneous operation but malfunctions as noise.

[0036]

As described above, according to the present invention,
After inserting a scan path and laying out, extracting a dangerous part that may malfunction due to the effect of crosstalk, and generating only a test pattern that shows the influence of crosstalk only for that point, Since this is a method of performing manufacturing tests using patterns, only patterns where the effects of crosstalk can be tested in manufacturing tests are created only at locations where the effects of crosstalk are likely to appear. There is an effect that a pattern when testing a failure at the time of a manufacturing test is minimized, and a test time for the test can be minimized, thereby improving quality while minimizing an increase or decrease in test cost.

In the method of the prior art, 16 patterns are required for detecting the output gate delay failure of the two-input logic gate and for detecting the failure due to the influence of crosstalk. The test can be performed with a total of four patterns, that is, two patterns for detecting the rise and fall of the gate output and two patterns for testing the influence of the crosstalk. This has the effect of reducing the test time and thereby the test cost.

[Brief description of the drawings]

FIG. 1 is a schematic flowchart illustrating a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a detailed process of FIG. 1;

FIG. 3 is a layout plan view illustrating an arrangement of adjacent wirings in FIG. 1;

FIG. 4 is a block diagram when testing the adjacent wiring in FIG. 1;

FIG. 5 is a block diagram when processing is performed by an additional circuit of FIG. 3;

6 is a diagram of a truth table for explaining the operation of the test circuit of FIG. 5;

FIG. 7 is a schematic flowchart illustrating a second embodiment of the present invention.

FIG. 8 is a block diagram when a strike is performed by a conventional OR circuit.

[Explanation of symbols]

 1, 2 Netlist 3-6 File 7 Dangerous place net file 8 Excluded file 10, 10a Test circuit 11, 12 Wiring (adjacent wiring) 13, 14 External terminal 15, 16 Output signal 17, 18 Input terminal 21 Test signal 22 , 24, 26, 27 flip-flops 23, 25 selector 28 synchronization circuit 29 clock signal 30 mask pattern 31-34 function block 40 OR gate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 G01R 31/28 V 21/822 H01L 21/82 C 27/04 TF term (Reference) 2G032 AA01 AB20 AC08 AC10 AD00 AE08 AE09 AE10 AE12 AG10 AK11 AK16 5B046 AA08 BA03 BA09 JA01 5F038 BH19 BH20 CD09 CD13 DF11 DT06 DT07 EZ20 5F064 BB02 BB04 BB19 EE08 EE43 EE46 H05 EE46 H05 EE46 H05 EE47 H05 BB

Claims (9)

[Claims] 1. A netlist that satisfies a logical function is input, a scan path test structure is created, and the netlist is laid out in a mask pattern. A test circuit is added in order to create a test pattern in which the influence of crosstalk appears at the extracted dangerous spot with the gate delay ATPG, and a manufacturing test is performed using the test pattern generated by performing the gate delay ATPG in the circuit. A method for testing a semiconductor integrated circuit, comprising: 2. After a scan path test structure is created, a scan flip-flop or an external terminal is added to a portion of the netlist where controllability and observability of each signal line to 0 and 1 are not sufficient, 2. The test method for a semiconductor integrated circuit according to claim 1, wherein a process for improving control and observability is added. 3. The semiconductor integrated circuit according to claim 2, wherein a netlist that satisfies the logic function into which the scan path is inserted is input, a mask pattern layout is performed, and adjacent wirings that are likely to be affected by crosstalk noise are extracted as dangerous points. How to test the circuit. 4. Extraction of adjacent wirings at a dangerous point is performed by extracting the wiring capacity and wiring length of each wiring, calculating the capacity between adjacent wirings, and selecting the adjacent wirings whose capacity between adjacent wirings exceeds a predetermined reference value. 4. The test method for a semiconductor integrated circuit according to claim 3, wherein the test is performed. 5. Extraction of adjacent wirings at a dangerous point is performed by grouping flip-flops serving as the same drive source from the back trace results of clock terminals of all flip-flops, and determining whether adjacent wirings in the same group have a synchronous relationship. 4. The test method for a semiconductor integrated circuit according to claim 3, wherein the test is performed. 6. A method of extracting adjacent wirings at a dangerous location, wherein the difference in drive capability between adjacent wirings is equal to or greater than a reference value, and the ratio of the inter-wiring capacitance to the wiring capacitance of the wiring having the smaller drive capability is a predetermined reference value. 5. A method in which an object exceeding the number is taken out.
Or the test method of a semiconductor integrated circuit according to 5. 7. A test circuit for converting an input signal of a logic gate to an extracted adjacent wiring into a transition of a signal value in which crosstalk noise is likely to occur using a gate delay ATPG tool. 2. The method for testing a semiconductor integrated circuit according to claim 1, wherein the method is used to add to a netlist. 8. A gate delay ATPG tool,
8. The test method for a semiconductor integrated circuit according to claim 7, wherein a test pattern is generated using the test circuit so that the extracted input signal of the logic gate has a signal value that easily causes crosstalk noise. 9. The test method for a semiconductor integrated circuit according to claim 7, wherein the test pattern is corrected by deleting an expected value at the external terminal of the added test circuit, and the semiconductor integrated circuit is tested using the corrected test pattern.