JP2003076742A - Apparatus and method for extraction of verification pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress verification time while ensuring the reliability of verification when verifying length of real wiring with respect to a layout. SOLUTION: In a method for the extraction of verification pattern, external terminals to be effected by a correction are extracted from delay information 201 and peripheral information 206, external terminals to be effected at every pattern block classified by function (S210) and a frequency of status shift of pattern blocks (S211) are extracted from verification patterns 209 and the verification patterns necessary to verify the correction are determined and selected (S213), so that the verification time can be suppressed while ensuring the reliability of verification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a verification pattern extraction device and method for actual wiring length verification of laid out integrated circuits.

[0002]

2. Description of the Related Art A conventional flow of actual wiring length verification will be described below with reference to the drawings. FIG. 4 is a flowchart showing a conventional process from layout design to mask creation.

In FIG. 4, first, layout / wiring processing is performed as an automatic layout design of an integrated circuit based on logic information (S401), and layout data 402 is output.
It is confirmed whether the layout data 402 has a design rule violation. Next, the delay information 403 is extracted from the layout data 402. This can be obtained by the delay calculation tool from the actual laid out wiring length. The netlist 404 corresponding to the layout data 402 on a one-to-one basis is also output using the conversion tool. Based on the delay information 403 and the netlist 404, the actual wiring length verification tool is used to verify the actual wiring length regarding the functional operation / timing (S405). When verifying the actual wiring length, the verification pattern 40 that was previously used in the temporary wiring length verification
Use 6 As a result of the actual wiring length verification, if there is no problem, the process directly proceeds to the mask making process (S407). However, if a timing error has occurred as a result of actual wiring length verification, check the location where the timing error has occurred.
Analysis and countermeasures are examined, layout correction information 408 is output, and layout data 402 is corrected based on the correction information 408 (S409). Hereinafter, this flow is repeatedly performed to perform actual wiring length verification using the verification pattern 406 until there is no problem in actual wiring length verification.

However, according to the above-mentioned conventional technique, the actual wiring length verification is performed even in the case of the layout modification with a small correction amount or the layout modification which does not necessarily affect all the verification patterns 406 used in the virtual wiring length verification. Since it was not possible to select an unnecessary verification pattern in step 2, it was necessary to perform actual wiring length verification using all verification patterns 406. Therefore, there is a problem that the verification time becomes long.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned conventional problems, the verification pattern extraction method and apparatus of the present invention aim to suppress verification time while ensuring reliability of verification. .

[0006]

In order to achieve this object, the verification pattern extraction method according to claim 1 of the present invention is a layout modified in designing a semiconductor integrated circuit by repeating layout and actual wiring length verification. A step of extracting delay information and peripheral information indicating circuit information adjacent to the corrected circuit in layout layout and the corrected logical information, and an external terminal having an influence on each pattern block classified by function from a verification pattern A step of extracting the frequency of the state transition and outputting it as pattern information, and a step of selecting a verification pattern divided by the function necessary for correction by the delay information, the peripheral information, the logical information, and the pattern information. It is characterized by extracting a verification pattern that is optimized to the minimum necessary for performing verification of correction.

The verification pattern extraction method according to claim 2 is
2. The method for extracting a verification pattern according to claim 1, wherein when extracting a verification pattern optimized to a minimum necessary for verification of the correction, circuit information corrected is extracted from the delay information and the delay information before correction. A step of extracting external terminals related to the modified circuit from the modified circuit information and the logical information; a step of extracting external terminals related to the peripheral circuit of the modified circuit from the peripheral information and the logical information; A step of merging an external terminal related to a circuit and an external terminal related to the peripheral circuit to output information of the external terminal necessary for verification, and an external terminal that has an influence on each pattern block classified by function from the verification pattern. And extracting the frequency of the state transition of the external terminal that affects each pattern block from the verification pattern and adding the priority order. And a step of outputting the list, and a step of selecting by comparing determines a verification pattern required to verify one of the verification pattern by the information and the list of external terminals required for the verification.

The verification pattern extraction device according to claim 3 is
A first storage device for storing layout information such as delay information, peripheral information indicating circuit information adjacent to the corrected circuit in layout, and corrected logic information; and a second storage device for storing all verification patterns. A first external terminal extracting unit that extracts external terminals related to the circuit modified from the layout information, and a second external terminal extracting unit that extracts external terminals related to peripheral circuits of the circuit modified from the layout information; An external terminal merging unit for merging the external terminal extracted from the first external terminal extraction unit and the external terminal extracted from the second external terminal extraction unit, and an influence on each pattern block classified by function from the verification pattern A third external terminal extracting unit for extracting an external terminal having a certain state, and a state transition of the external terminal having an influence on each pattern block from the verification pattern. A state transition frequency extracting unit for extracting a degree, a list output unit for outputting a list in which priority is added to each external terminal according to the state transition frequency, information on external terminals merged by the external terminal merging unit, and A feature is that a minimum verification pattern necessary for verification of layout is selected at the time of layout modification by having a judgment / selection processing device for judging / selecting a verification pattern to be used for verification based on the list output from the list output unit. To do.

As described above, the verification pattern extraction layout method of the present invention can suppress the verification time while ensuring the reliability of verification.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A verification pattern extracting method according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing a verification pattern extraction method according to the first embodiment of the present invention. Figure 1
First, a layout / wiring process is performed as an automatic layout design of an integrated circuit based on the logic information (S10).
1) Check if there are any design rule violations. Next, the actual wiring length is verified using the verification pattern 102 used in the tentative wiring length verification (S103), and if there is a problem in the verification, the layout is corrected based on the verification result (S1).
04) Output the layout data 105. If there is no problem in verification, the process proceeds to the mask creation (S103) process.
Next, from the layout data 105, the delay information 106,
The peripheral information 107 such as the signal name, mask layer, and wiring length of the wiring adjacent to the corrected wiring is extracted. Also,
The netlist 108 used for layout correction is also prepared. Here, with respect to the verification pattern 102, the patterns are classified according to the function to be confirmed, and the external terminals that have an effect on each are listed, and the frequency of state transition of each external terminal from the expected value is listed and output as pattern information 109. Next, the verification pattern 102 is determined and selected by referring to the verification pattern 102, the pattern information 109, the delay information 106, the peripheral information 107, and the netlist 108, and the verification pattern portion relating to the function affected by the correction is extracted pattern 111. (S110). Finally, actual wiring length verification is performed on the netlist 108 using the extraction pattern 111 (S112). As a result of the actual wiring length verification, if there is no problem, the process directly proceeds to the mask making process (S113). However, if a timing error has occurred as a result of the actual wiring length verification, the location where the timing error has occurred is checked, analyzed, and countermeasures are taken, and the layout correction information 114 is output to correct the layout data 105. Hereinafter, this flow is repeated until there is no problem in the actual wiring length verification.

A verification pattern extraction method according to the second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a flowchart showing the determination / selection processing steps of the verification pattern extraction method according to the second embodiment of the present invention.

In FIG. 2, first, the delay information 2 after correction is shown.
01 is compared with the delay information of the information 202 before the correction to extract the corrected circuit information (S203). At this time, the netlist information of the corrected netlist 204 and the netlist information of the information 202 before correction are also compared to confirm that the corrected circuit information matches. Next, which external terminal the modified wiring is connected to is traced by the netlist 204 of the integrated circuit from the block instance name of the modified wiring and the modified wiring name, and the external terminal related to the modification is extracted (S).
205). Further, the peripheral information 206 and the net list 204 of the integrated circuit are extracted from the peripheral circuit in the range adjacent to the correction location in the layout and affecting the operation, and the external terminals to which the circuit is connected are extracted (S207). ). At this time, the peripheral information 206 includes the information of the adjacent wiring and the intersecting wiring to the corrected wiring, but the contact resistance at the time of changing the wiring layer and the capacitance between layers due to the multilayering of the wiring layers. Etc. are also considered. Next, in order to avoid duplication of the external terminals extracted from the modified portion and its peripheral portion, the external terminals are merged and all external terminals affected by the modification are extracted from the layout information (S208). On the other hand, regarding the verification pattern 209,
First, the external terminals that affect each pattern are extracted as a list (S210), then the frequency of state transitions of the external terminals is extracted as the number of times (S211), and priority is given to verification from the frequency of state transitions. The list 212 in which the order is specified is output to clarify the function and the index in the external terminal for each pattern. Finally, by comparing and determining the external terminal information extracted from the layout information and the list 212 specifying the priority of each external terminal created from the verification pattern and selecting (S213), the verification pattern 214 corresponding to the correction.
Can be extracted.

A verification pattern extraction device according to the third embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram showing a verification pattern extraction device according to the third embodiment of the present invention.

In FIG. 3, reference numeral 301 is a layout information storage device, 302 is a verification pattern storage device, and 303 is a judgment / selection processing means. Here, the determination / selection processing means 3
Reference numeral 03 denotes an external terminal extracting unit 304 related to correction, an external terminal extracting unit 305 related to peripheral circuits, and an external terminal merging unit 30.
6, a verification pattern external terminal extraction unit 307, a state transition frequency extraction unit 308, a list output unit 309, and a judgment selection processing device 310.

The operation of the verification pattern extraction device configured as described above will be described below. First, the layout of the integrated circuit is modified based on the logic information, the delay information and peripheral information corresponding to the modification are extracted and stored in the layout information storage device 301, and the circuit is modified by comparing it with the delay information before modification. Extract information. Next, the layout storage device 301 is used by the external terminal extraction unit 304 related to the correction.
Then, the netlist stored in (1) is compared with the delay information, and the external terminal extracting unit 305 related to the peripheral circuit is compared with the peripheral information to extract and merge the corresponding external terminals.

On the other hand, all the patterns are taken out from the verification pattern storage device 302, and the verification pattern external terminal extraction unit 307 extracts the external terminals that have an influence on each pattern. Next, the state transition frequency extraction unit 308 recognizes the frequency of the state transition of the signal as the number of times, and the list output unit 309 assigns the priority order and outputs the list.
Finally, the determination / selection processing device 310 determines / selects these, and outputs a verification pattern required for verification of the correction.

As described above, by selecting and verifying the verification patterns required for the verification for the correction, the verification time can be suppressed while ensuring the reliability of the verification.

[0019]

As described above, the verification pattern extraction method and apparatus of the present invention extract external terminals affected by a modification, select a verification pattern required for verification for the modification, and perform verification. The verification time can be suppressed while ensuring the reliability of verification.

[Brief description of drawings]

FIG. 1 is a flowchart showing a verification pattern extraction method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing determination / selection processing steps of a verification pattern extraction method according to the second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a verification pattern extraction device according to a third embodiment of the present invention.

FIG. 4 is a flowchart showing steps from conventional layout design to mask creation.

[Explanation of symbols]

102 verification pattern 105 layout data 106 Delay information 107 Surrounding information 108 Netlist 109 pattern information 111 extraction pattern 114 Correction information 201 Delay information 202 Information before modification 204 Netlist 206 Surrounding information 209 Verification pattern 212 List 214 Verification pattern 301 Layout information storage device 302 verification pattern storage device 303 Judgment / selection processing means 304 External terminal extraction unit related to correction 305 External terminal extraction section related to peripheral circuits 306 External terminal merge section 307 Verification pattern external terminal extraction unit 308 State transition frequency extraction unit 309 List output part 310 Judgment / selection processing device 402 Layout data 403 delay information 404 Netlist 406 Verification pattern 408 Correction information

Claims (3)

[Claims] 1. When designing a semiconductor integrated circuit by repeating layout and actual wiring length verification, peripheral information indicating delay information from modified layout data and circuit information adjacent to the modified circuit in terms of layout and modified logic. A step of extracting information, a step of extracting an external terminal that has an influence on each pattern block classified by function from a verification pattern and a frequency of its state transition and outputting as pattern information, the delay information and the peripheral information A step of selecting a verification pattern classified according to a function required for correction by the logical information and the pattern information, and extracting a verification pattern optimized to a minimum necessary for verifying the correction. A verification pattern extraction method characterized by the above. 2. When extracting a verification pattern optimized to the minimum necessary for the verification of the modification, a step of extracting modified circuit information from the delay information and the delay information before modification, and the modified circuit information. And a step of extracting an external terminal related to the modified circuit from the logic information, a step of extracting an external terminal related to the peripheral circuit of the modified circuit from the peripheral information and the logic information, and an external terminal related to the modified circuit. A step of merging external terminals related to the peripheral circuit and outputting information of the external terminals necessary for verification; a step of extracting an external terminal having an influence on each pattern block classified by function from the verification pattern; Extracting a frequency of state transitions of the external terminals having an influence on each pattern block from the verification pattern and outputting a list with priority added, 2. The method for extracting a verification pattern according to claim 1, further comprising the step of comparing and determining information of external terminals necessary for verification and a verification pattern necessary for verification among the verification patterns based on the list. 3. A first storage device for storing layout information such as delay information, peripheral information indicating circuit information adjacent in layout to the corrected circuit, and logical information after correction, and a first storage device for storing all verification patterns. No. 2 storage device, a first external terminal extraction unit for extracting external terminals related to the circuit modified from the layout information, and a second external terminal for extracting external terminals related to peripheral circuits of the circuit modified from the layout information. A terminal extracting unit, an external terminal merging unit that merges the external terminal extracted from the first external terminal extracting unit and the external terminal extracted from the second external terminal extracting unit, and is classified according to functions based on the verification pattern. A third external terminal extraction unit that extracts an external terminal that affects each pattern block, and an external that affects each pattern block based on the verification pattern. A state transition frequency extraction unit that extracts the frequency of child state transitions, a list output unit that outputs a list in which priority is added to each external terminal according to the state transition frequency, and an external unit merged by the external terminal merge unit Selects the minimum verification pattern required for verification of correction at the time of layout correction by having a judgment / selection processing device for judging / selecting the verification pattern used for verification based on the terminal information and the list output from the list output section. A verification pattern extraction device characterized by: