JPH098789A - Clock reproducing device - Google Patents

Abstract

PURPOSE: To process and integrate data just after switching the device into a reception mode in a simplex system. CONSTITUTION: This device is provided with JK-F/Fs 3 and 4 for outputting signals active by the extent of the lead phase difference or lag phase difference of pulse signals from edge detectors 1 and 2 for detecting the change points of received and reproduced clock signals, OR gate 6 for outputting the OR between a third pulse signal to be outputted at the falling of the received clock signal and the HOLD signal of a CPU and up/down counter 7 for executing up/down to a counted value by the signals of the JK-F/Fs 3 and 4 and loading an initial value when the output of the OR gate 6 is active and then, this device is further provided with a latch circuit 8 for holding the counted value of the counter 7 by the third pulse signal, voltage controlled oscillator(VCO) 10 for changing an oscillation frequency by a counted value converting analog signal, and frequency divider 11 for dividing the frequency of an output signal from the VCO 10 and outputting the reproduced clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite communication device,
In particular, the present invention relates to a clock recovery device that enables reception data to be obtained immediately after switching in a simplex (transmission and reception are temporally switched for communication) satellite communication device.

[0002]

2. Description of the Related Art There are two main types of satellite communication.
One is simplex (half duplex) and the other is duplex (full duplex). Simplex is a method in which transmission and reception are switched over in time for communication, while duplex is a method in which transmission and reception are performed simultaneously. In voice communication such as telephone, it is uncomfortable if transmission and reception are not performed at the same time, and thus duplex is mostly used in conventional satellite communication.

FIG. 10 shows a block diagram of a clock recovery device used in a conventional duplex satellite communication device. This clock reproducing device includes a demodulator 23 that receives radio waves from a satellite and demodulates data, and a full-wave rectifier 24 that inputs received data and performs full-wave rectification to extract and output a clock component included in the received data. And a bandpass filter 25 for inputting the output signal of the full-wave rectifier 24 and filtering and outputting only a desired reception clock component, and inputting an output signal of the bandpass filter 25 and phase-synchronizing the reference signal with the signal. And an analog PLL circuit 26 that outputs a reception clock.

The operation of the clock regenerator having the above configuration will be described below. Since the carrier wave of the radio waves from the satellite is modulated by the data, the demodulator 2
Reference numeral 3 removes the carrier component from this radio wave, extracts only the data component, and outputs it as received data. By rectifying the received data, the full-wave rectifier 24 allows the waveform of the received data to fold back from the middle point of the amplitude to the upper side as shown in FIG. 11, extracting the clock component included in the received data. Output. Since the output signal of the full-wave rectifier 24 includes the (1 / integer) component of the clock component in addition to the desired clock component, the bandpass filter 25 selects and outputs only the desired clock component by filtering. . The analog PLL circuit 26 phase-locks the reference signal of the analog PLL circuit 26 with the output signal of the bandpass filter 25 to remove components other than the desired clock component and select and output only the reception clock. As a result, demodulator 2
Analog PL regardless of the pattern of the received data from 3
The L circuit 26 always outputs a reception clock having a constant frequency. Here, the received data is serial data, and it is necessary to divide the data into 8-bit data in order for the CPU to process the received data. Therefore, a fixed pattern (synchronous pattern) whose data is known is periodically included in the received data in advance. By counting the number of reception clocks synchronized with the reception data using this synchronization pattern as a guide, data is divided into 8-bit data.

[0005]

In recent years, the use of satellite communication has increased, and it is necessary to suppress the price of terminals in order to popularize satellite communication in the future. For this reason, in recent years, in systems that perform data communication, there are systems that perform communication in simplex instead of duplex in order to suppress the price of terminals. Specifically, a single synthesizer can be used by switching and using the synthesizer for switching the channel during transmission and during reception. However, in the simplex, since the synthesizer is set as the transmission channel during transmission, the radio wave from the satellite cannot be received. As a result, the received data output from the demodulator 23 becomes a random value, the analog PLL circuit 26 is out of lock, and the received clock output from the analog PLL circuit 26 is also in a free-run state and synchronized with the received data. Not because
The data delimiter for every 8 bits becomes indefinite. Therefore, when you start receiving the radio waves from the satellite again, the analog PL
Until the L circuit 26 locks the received data and detects the synchronization pattern, the data delimiter for every 8 bits is not fixed and the CPU cannot process the received data.

The present invention solves the above problems, and an object of the present invention is to provide a clock recovery device capable of processing data immediately after switching to the reception mode by the simplex method.

[0007]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a first pulse signal in which a received clock signal output from a demodulator is input, a change point of the clock signal is detected, and a first pulse signal is output. 1 edge detector, a second edge detector for inputting a reproduced clock signal, which will be described later, detecting a change point of the clock signal and outputting a second pulse signal, and the first edge detector. The first pulse signal and the second
And the second pulse signal from the edge detector of
Of the first JK-F / F, which outputs an up signal that becomes active by the amount of the lead phase difference when the phase of the pulse signal of is ahead of the phase of the second pulse signal, and conversely the first pulse A second JK-F / F which outputs a down signal which becomes active by the delay phase difference when the phase of the signal is delayed from the phase of the second pulse signal and the fall of the reception clock signal. A third edge detector that detects and outputs a third pulse signal, a third pulse signal from the third edge detector, and a HOLD signal from the CPU are input and the logical sum of both signals is calculated. And an output signal of the OR gate, the up signal from the first JK-F / F, the down signal from the second JK-F / F, and the output signal of the OR gate. Sometimes the count value is increased Of the first up / down counter, which counts down when the down signal is active, and loads an initial value which is half of the maximum count value when the output signal of the OR gate is active. A latch circuit for inputting the count value and the third pulse signal from the third edge detector and holding the count value of the first up-down counter when the third pulse signal is active, and the latched count A D / A converter for converting a value into an analog signal, a voltage controlled oscillator for changing the oscillation frequency according to the analog signal of the D / A converter, and an output signal of the voltage controlled oscillator for receiving a clock signal from the demodulator And a frequency divider which divides the frequency up to the same frequency and outputs as a reproduced clock signal.

Further, in addition to the above configuration, the first JK-
A first counter that inputs an up signal output from the F / F, counts up when the up signal is active, and outputs a first carry-up signal when the count value reaches a maximum, and a second JK- A second counter that inputs a down signal output from the F / F, counts up when the down signal is active, and outputs a second carry-up signal when the count value reaches a maximum, and a first carry-up. The signal and the second carry-up signal
The count value is incremented when the carry-up signal of is input before the second carry-up signal, and conversely when the second carry-up signal is input before the first carry-up signal. And a second up / down counter for outputting the count value as the initial value of the first up / down counter.

Further, instead of the first counter, two counters each having a half stage number of the first counter, a third counter and a fourth counter are connected in cascade, and a third counter is connected. The third carry-up signal output when the count value of the counter reaches the maximum, and the fourth carry-up signal
The fourth carry-up signal output when the count value of the counter becomes maximum and the switching signal from the CPU are input, and the third carry-up signal or the fourth carry-up signal is input according to the switching signal from the CPU. Instead of the first selector for selecting and outputting either one of the carry-up signals and the second counter as well, the fifth counter and the sixth counter are connected in tandem, and a fifth carry-up signal is generated. A sixth carry-up signal and a switching signal from the CPU are input, and either the fifth carry-up signal or the sixth carry-up signal is selected and output according to the switching signal from the CPU. 2 selectors and 1st
The output signal of the second selector and the output signal of the second selector are input, the count value is increased when the output signal of the first selector is active, and the count value is decreased when the output signal of the second selector is active. While doing
A second up / down counter for outputting the count value as an initial value of the first up / down counter is provided.

Furthermore, the EX-OR which inputs the up signal output from the first JK-F / F and the down signal output from the second JK-F / F and outputs the exclusive OR of both signals.
A fourth JK-F / which outputs a reset signal for inputting the output signal of the gate, the output signal of the EX-OR gate and the output signal of the third edge detector and resetting the entire device when both signals are active. F and are provided.

[0011]

According to the present invention, with the above configuration, in the simplex satellite communication device, the count value of the first up-down counter is held by the HOLD signal from the CPU before the reception clock from the demodulator is cut off. Even during transmission, it is possible to continue outputting the regenerated clock having substantially the same frequency and phase as the received clock.

Further, the first counter counts the sum of the advanced phase differences, the second counter counts the total of the delayed phase differences, and the second counter determines which of the carry-up signals of both counters becomes active earlier. The count value of the up / down counter is increased / decreased, and the count value is set as the initial value of the first up / down counter. Then, before the reception clock from the demodulator is cut off, HOLD from the CPU
By holding the count value of the second up / down counter by the signal, the phase of the reproduction clock being transmitted can be brought closer to the phase of the reception clock.

Further, two halves of the number of stages of the first counter and the second counter are connected in series, and a carry-up signal of either the first counter or the second counter is sent from the CPU. By inputting it to the second up / down counter by selecting it with the control signal of, the number of stages of the counter is reduced to reduce the lockup time until the device locks to the reception clock, and after locking, the number of stages of the counter is changed. The jitter (fluctuation) of the reproduced clock output from the frequency divider can be reduced by increasing the value.

Furthermore, if the device locks in a phase opposite to the phase of the received clock (pseudo lock), the first JK-
Since the up signal output by the F / F and the down signal output by the second JK-F / F always show opposite polarities, it is possible to reset the entire device with the exclusive OR signal of both signals. , It is possible to prevent the device from being pseudo-locked.

Thus, the received data can be divided into data of every 8 bits immediately after switching to reception without waiting until the synchronization pattern is detected when switching from transmission to reception.

[0016]

1 is a block diagram of a block reproducing device used in a satellite communication device according to a first embodiment of the present invention.

In FIG. 1, 1 is a first edge detector for inputting a received clock signal output from a demodulator, detecting a change point of the clock signal and outputting a pulse signal, and 2 is a frequency divider 11 described later. The second edge detector 3 which inputs the reproduction block signal from the first edge detector detects the change point of the clock signal and outputs the pulse signal, and the third edge detector 3 and the first pulse signal from the first edge detector 1 and the second edge detector 3. An up signal which receives the second pulse signal from the edge detector 2 and advances when the phase of the first pulse signal is ahead of the phase of the second pulse signal and becomes active by the phase difference. On the contrary, the first JK-F / F, which outputs
The second JK-F / F, 5 which outputs a down signal which becomes active by the delay phase difference when it is delayed from the phase of the pulse signal of, detects the falling of the reception clock signal and detects the third signal. A third edge detector that outputs a pulse signal, and 6 is an OR that inputs the third pulse signal from the third edge detector 5 and the HOLD signal from the CPU and outputs the OR of both signals. Gate, 7 is the first JK-F /
The up signal from F3, the down signal from the second JK-F / F4, and the output signal of the OR gate 6 are input, and the count value is increased when the up signal is active, and the count value is activated when the down signal is active. While the output signal of the OR gate 6 is active, the initial value which is half the maximum count value is loaded.
Up / down counter, 8 is the count value of the first up / down counter 7 and the third value from the third edge detector 5.
And a latch circuit that holds the count value of the first up / down counter 7 when the third pulse signal is active, and 9 is a D / A converter that converts the latched count value into an analog signal. 10 is D / A
A voltage-controlled oscillator that changes the oscillation frequency according to the analog signal of the converter 9, and a frequency-dividing 11 that divides the output signal of the voltage-controlled oscillator 10 to the same frequency as the reception clock signal from the demodulator and outputs it as a reproduction clock signal. It is a vessel.

Next, the operation of the clock regenerator of the present invention comprising the above components will be described. The clock recovery device of the present invention constitutes a kind of PLL circuit, and
PLL from the edge detector 1 to the D / A converter 9
Corresponds to the phase comparator of the circuit. FIG. 5 shows the first of the present invention.
6 is a time chart showing the operation of the phase comparison unit in the clock recovery device of the embodiment. FIG. 5 shows the case where the phase of the received clock is ahead of the phase of the recovered clock, and FIG. 6 shows the case where the phase of the received clock is behind the phase of the recovered clock. As can be seen from FIGS. 5 and 6, the first edge detector 1 and the second edge detector 2 output pulses at the rising edges of the reception clock and the reproduction clock, respectively. In addition, the third edge detector 5
Outputs a pulse at the falling edge of the reception clock, and the OR gate 6 outputs a pulse with a slight delay. First
The up signal which is the output of JK-F / F3 advances when the phase of the received clock leads the phase of the recovered clock, and becomes active by the phase difference. If the maximum count value of the first up / down counter 7 is 512 every time the output pulse of the OR gate 6 is input, the first up / down counter 7 loads 256 which is half of the maximum count value as an initial value, and While the up signal of JK-F / F3 is active, the count value increases at the rising edge of the system clock. Since the count value of the first up / down counter 7 is latched by the output pulse of the third edge detector 5, the count value is held by the latch circuit 8 for one cycle of the reception clock. The held count value becomes larger as the advance phase difference of the reception clock with respect to the reproduction clock becomes larger,
On the contrary, if the advance phase difference is small, the counter value is 25, which is the initial value.
No increase from 6. Similarly, as can be seen from FIG. 6, the larger the delay phase difference of the received clock with respect to the recovered clock, the smaller the count value, and conversely, if the delay phase difference is small, the counter value does not decrease from the initial value of 256.

When the counter value is converted into a VCO voltage which is an analog signal by the D / A converter 9, the higher the counter value, the higher the VCO voltage, and the smaller the counter value, the VCO voltage.
The CO voltage will be low. The voltage controlled oscillator 10 works so as to increase the oscillation frequency when the VCO voltage becomes high and, conversely, lower the oscillation frequency when the VCO voltage becomes low. The frequency divider 11 divides the oscillation frequency of the voltage controlled oscillator 10 to the same frequency as the reception clock and outputs it as a reproduction clock.

Therefore, when the phase of the received clock is ahead of the phase of the recovered clock, the count value of the first up / down counter 7 increases and the VCO voltage rises. As a result, the oscillation frequency of the voltage controlled oscillator 10 increases and the frequency of the reproduction clock also increases. Therefore, considering the phase per clock cycle, the phase of the reproduction clock advances, and the phase difference between the reception clock and the reproduction clock decreases. . On the contrary, when the phase of the reception clock is behind the phase of the reproduction clock, the count value of the first up / down counter 7 decreases and the VCO voltage decreases. As a result, the oscillation frequency of the voltage controlled oscillator 10 becomes low and the frequency of the recovered clock also becomes low. Therefore, considering the phase per clock cycle, the phase of the recovered clock is delayed, and the phase difference between the received clock and the recovered clock is reduced. . Therefore, as shown in FIGS. 5 and 6, the present clock regenerator detects the phase difference between the received clock and the regenerated clock for each cycle of the received clock and reduces the phase difference by VC.
By changing the O voltage, a reproduction clock synchronized with the reception clock is created.

Then, before the reception clock from the demodulator is switched from the reception mode to the transmission mode, the count value of the first up / down counter 7 is held by the HOLD signal from the CPU to hold the VCO voltage. Is fixed, and the oscillation frequency of the voltage controlled oscillator 10 is also constant at the frequency locked to the reception clock. Therefore, it is possible to continue outputting the regenerated clock having substantially the same frequency and phase as the received clock even during transmission.

Next, since the reception clock output from the demodulator is the clock component included in the reception data, the reception data may be changed to 1, 0, 1, 0 alternately. For example, the extracted clock signal can also be obtained as a clean sine wave with no jitter. However, in general, the value of 1 or 0 of the received data changes randomly, so that the clock signal extracted from the received data has 1 / n times (n is an integer of 2 or more) the frequency component of the original clock signal. Frequency components are also included. Further, the waveform of the received data does not always follow the same locus depending on the content of the data, and therefore there is fluctuation in the waveform in terms of time. Therefore, the clock signal extracted from the received data becomes a signal with jitter, but when the C / N of the received data becomes poor, the jitter of the clock signal increases, and when the received data is sampled with the clock signal, the received data is sampled. The frequency of sampling by mistake increases. Therefore, it is necessary to remove the jitter of the clock signal in the clock reproduction.

In the conventional clock regenerator, the analog PLL circuit is phase-synchronized with the clock signal having jitter to remove components other than the desired clock component and select and output only the reception clock. Therefore, in order to remove the jitter, the response speed of the PLL loop must be made as slow as possible so that the PLL does not follow the jitter, but only the desired clock signal. Therefore, the constant of the loop filter that determines the response speed of the loop is increased, but conversely, there is a problem that it takes too long to pull the PLL loop until it locks to the desired clock signal. In addition, the components themselves that make up the loop filter also become large.

On the other hand, the clock recovery device of the present invention integrates the phase difference between one clock of the received clock at each fall of the received clock to obtain the VCO voltage. Therefore, even if the phase difference is changed instantaneously due to the jitter, the phase difference is averaged and V
Since it does not appear in the change of the CO voltage, the jitter can be removed. On the other hand, until the clock recovery device locks the received clock, even if the phase difference between one clock of the same clock is integrated, it always exists in the phase difference and appears as a change in the VCO voltage. The problem of taking too much does not occur.

FIG. 2 is a block diagram of a clock reproducing apparatus according to the second embodiment of the present invention. Components having the same functions as those in the first embodiment are designated by the same reference numerals and their description is omitted. The first edge detector 1 to the frequency divider 11 are the same as the first embodiment except that the OR gate 6 is omitted. In FIG. 2, reference numeral 12 inputs the up signal output from the first JK-F / F3, counts up when the up signal is active, and outputs the first carry-up signal when the count value becomes maximum. First counter, 13 is second
The second counter 14 which inputs the down signal output from the JK-F / F4 and counts up when the down signal is active and outputs the second carry-up signal when the count value becomes maximum, The first carry-up signal and the second carry-up signal are input, and when the first carry-up signal is input before the second carry-up signal, the count value is increased, and vice versa.
The second up-down counter outputs the count value as the initial value of the first up-down counter 7 while decreasing the count value when the carry-up signal of is input before the first carry-up signal. .

Next, the operation of the clock regenerator according to the second embodiment of the present invention will be described below. Figure 7
FIG. 4 shows changes in the VCO voltage after the clock recovery device in the first embodiment of the present invention locks to the reception clock. Assuming that the frequency and phase of the recovered clock match that of the received clock when the VCO voltage is 2.5V, the VCO voltage should ideally remain constant at 2.5V as indicated by the dotted line, but Due to the fact that the clock itself has jitter and that the clock recovery device itself follows the received clock with the feedback loop of the PLL circuit, the VCO voltage changes as shown by the solid line. If the count value of the first up / down counter 7 is held at point A in FIG. 7 by the HOLD signal from the CPU, the VCO voltage is 2.5 V, so the frequency and phase of the regenerated clock signal are the received clock signal. Matches that of. However, if the count value is held at point B in FIG. 7, the VCO voltage is not 2.5 V, and therefore the frequency and phase of the reproduced clock signal do not match that of the received clock signal, and therefore gradually shift. In order to solve this problem, instead of simply holding the count value of the first up / down counter 7, the VCO voltage that is constantly fluctuating is averaged, and this averaged VCO voltage is output from the CPU. HOLD
It may be held by a signal.

The component added in the clock recovery device in the second embodiment of the present invention is a circuit for averaging the above VCO voltage. The operation of the averaging circuit will be described below.

In the diagram showing the change of the VCO voltage in FIG. 8A, in order to average the VCO voltage, the areas of the vertical stripes above 2.5V and the horizontal stripes below 2.5V are measured. All areas should be added up. Specifically, the area of the vertical stripe portion is the time during which the up signal, which is the output of the first JK-F / F3, is active. When the phase of the received clock leads the phase of the recovered clock, the up signal advances and becomes active by the phase difference. vice versa,
The area of the horizontal stripe is the time during which the down signal, which is the output of the second JK-F / F4, is active. When the phase of the received clock is behind the phase of the recovered clock, the down signal becomes active after the phase difference. Therefore, when the up signal of the first JK-F / F3 is active, the first counter 12 counts up and the areas of the vertical stripes are integrated. Similarly, when the down signal of the second JK-F / F4 is active, the second
The counter 13 counts up and integrates the area of the horizontal stripes. Then, if the first counter 12 becomes FULL before the second counter 13, the count value of the second up / down counter 14 is incremented by one, and vice versa.
The second counter 13 is set to F before the first counter 12.
When it becomes UL, the count value of the second up / down counter 14 is decreased by one. As a result, the count value of the second up / down counter 14 changes in such a direction that the area of the vertical stripes and the area of the horizontal stripes are always equal. Further, the first counter 12 and the second counter 13 are reset each time the count value of the second up / down counter 14 changes. Further, the count value of the second up / down counter 14 is loaded as the initial value of the first up / down counter 7 at the falling edge of the reception clock signal. As a result, the first up / down counter 7 starts from the previous averaged VCO voltage value each time, and therefore has a minimum change. Therefore, the change of the VCO voltage of the clock recovery device in the second embodiment of the present invention becomes small as shown in FIG. 8 (b). And the second
Since the count value of the up / down counter 14 means the averaged VCO voltage value before that,
If this count value is held by the OLD signal, the phase shift of the reproduced clock signal can be further reduced.

FIG. 3 is a block diagram of a clock reproducing apparatus according to the third embodiment of the present invention. From the first edge detector 1 to the frequency divider 11 and the second up / down counter 1
4 has the same configuration as that of the second embodiment. In FIG. 3, 1
5, 16, 17, and 18 have a second number of counter stages, respectively.
Of the first counter 12 shown in the above embodiment, and outputs the third, fourth, fifth and sixth carry-up signals when the count value becomes FULL, respectively. , Fifth and sixth counters, 19 is a third carry-up signal according to a switching signal from the CPU,
A first selector 20 for selecting one of the fourth carry-up signals and outputting it to the second up-down counter 14 is also a fifth carry-up signal or a sixth carry-up signal in response to a switching signal from the CPU. This is a second selector that selects one of the carry-up signals of and outputs it to the second up-down counter 14.

Next, the operation of the clock regenerator according to the third embodiment of the present invention will be described below. Second
In the above embodiment, the larger the number of stages of the first and second counters, the smaller the jitter of the reproduction clock, but conversely, the initial value of the second up / down counter 14 is 2.5V when the VCO voltage is 2.5V. Since it starts from the VCO voltage of 2.8 due to variations in the characteristics of the voltage controlled oscillator.
In the case of locking to the reception clock with V, the frequency is immediately synchronized with the reception clock by the first up / down counter 7, but the phase is synchronized with the reception clock by the second up / down counter 14. Value is VCO
It takes 2.8V when converted to voltage. The count value of the second up / down counter 14 changes by one only after the first or second counter 12, 13 becomes FULL, and therefore the count value of the first up / down counter 14 becomes stable until the count value becomes stable. It is greatly related to the number of steps. Therefore, when the power is turned on or when the transmission mode is switched to the reception mode, the time until the phase of the regenerated clock is synchronized with the phase of the reception clock is equal to the number of stages of the first and second counters.
It increases in proportion to 2 and 13. Therefore, until the phase of the recovered clock is synchronized with the phase of the received clock, the number of stages of the counter is reduced to reduce the lockup time, and after the phases are synchronized, the number of stages of the counter is increased to reduce the jitter. The number of stages of the counter is switched by the select signal from the CPU.

FIG. 4 is a block diagram of a clock recovery device according to a fourth embodiment of the present invention. The configuration from the first edge detector 1 to the second selector 20 is the same as that of the third embodiment. In FIG. 4, 21 is the first JK-F / F3
Of the EX-OR gate 21 and the output signal of the EX-OR gate 21 and the exclusive OR of the two signals are input. The third JK-F / F is a third JK-F / F which inputs the output signal of the third edge detector 5 and outputs a reset signal for resetting the entire apparatus when both signals are active.

Next, the operation of the clock regenerator according to the fourth embodiment of the present invention will be described below. First, FIG. 9 shows the relationship between the phase difference between the received clock and the recovered clock and the VCO voltage. The clock recovery device of the present invention changes the VCO voltage so that the phase difference becomes zero. That is, at point C, the VCO voltage is lowered to move closer to point D where the phase difference is zero, and conversely at point E, VC
By increasing the O voltage, it works so as to approach the point D where the phase difference is zero. However, the same VCO voltage as point D with zero phase difference also exists at point F. The PLL loop may be locked even at point F having a phase difference of 180 degrees with the received clock (called pseudo lock). In this pseudo lock state, when the output pulse of the third edge detector 5 is active, one of the outputs of the first or second JK-F / F is "H" and the other is "L". Become. In the normal lock, both outputs of the first and second JK-F / Fs 3 and 4 are "L", as is apparent from FIGS. 5 and 6.
Utilizing this, when the output signal of the third edge detector 5 becomes active, the up signal output by the first JK-F / F3 and the down signal output by the second JK-F / F4. By outputting a signal that resets the entire device when the exclusive OR of the signals becomes "H", the PLL loop is prevented from being pseudo-locked.

[0033]

As described above, according to the present invention, in a simplex satellite communication device, a reception clock having less jitter than that of a conventional analog PLL can be reproduced during reception without sacrificing lockup time, and transmission. It is possible to continue outputting the regenerated clock having the same frequency and phase as the received clock.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock recovery device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a clock recovery device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a clock recovery device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a clock recovery device according to a fourth embodiment of the present invention.

FIG. 5 is a time chart of each part of the phase comparison unit in the first embodiment of the present invention.

FIG. 6 is a time chart of each part of the phase comparison unit in the first embodiment of the present invention.

FIG. 7 is a diagram showing changes in the VCO voltage of the clock recovery device according to the first embodiment of the present invention.

FIG. 8 (a) shows a change in VCO voltage of the clock recovery device in the first embodiment of the present invention. FIG. 8 (b) shows a change in VCO voltage of the clock recovery device in the second embodiment of the present invention. Figure

FIG. 9 shows a phase difference and V in the clock recovery device of the present invention.
Diagram showing the relationship with CO voltage

FIG. 10 is a block diagram of a conventional clock recovery device.

FIG. 11 is a waveform of each part of a conventional clock recovery device.

[Explanation of symbols]

 1 1st edge detector 2 2nd edge detector 3 1st JK-F / F 4 2nd JK-F / F 5 3rd edge detector 6 OR gate 7 1st up-down counter 8 Latch circuit 9 D / A converter 10 Voltage controlled oscillator 11 Frequency divider 12 First counter 13 Second counter 14 Second up / down counter 15 Third counter 16 Fourth counter 17 Fifth counter 18 Sixth Counter 19 first selector 20 second selector 21 EX-OR gate 22 third JK-F / F

Claims (4)

[Claims] 1. A first edge detector for inputting a received clock signal output from a demodulator, detecting a changing point of the clock signal and outputting a first pulse signal, and inputting a reproduced clock signal described later. A second edge detector that detects a change point of the clock signal and outputs a second pulse signal, a first pulse signal from the first edge detector, and a second edge detector from the second edge detector. A first JK- which inputs the second pulse signal and outputs an up signal which becomes active by an amount corresponding to the phase difference when the phase of the first pulse signal leads the phase of the second pulse signal. F / F, on the contrary, first
The second JK-F / F which outputs a down signal which becomes active by the delay phase difference when the phase of the pulse signal is delayed from the phase of the second pulse signal, and the rising of the reception clock signal. A third edge detector that detects a falling edge and outputs a third pulse signal, a third pulse signal from the third edge detector, and a HOLD signal from the CPU are input, and the logical sum of both signals is input. And an output signal of the OR gate, the up signal from the first JK-F / F, the down signal from the second JK-F / F, and the output signal of the OR gate are input. The count value is increased when active and the count value is decreased when the down signal is active, while the initial value that is half the maximum count value is loaded when the output signal of the OR gate is active. Up / down counter, the count value of the first up / down counter, and the third pulse signal from the third edge detector are input, and the first up / down counter is activated when the third pulse signal is active. A latch circuit that holds the count value of the counter, a D / A converter that converts the latched count value into an analog signal, a voltage-controlled oscillator that changes the oscillation frequency according to the analog signal of the D / A converter, and the voltage A clock regenerator comprising: a frequency divider that divides the output signal of the controlled oscillator to the same frequency as the reception clock signal from the demodulator and outputs the regenerated clock signal. 2. A first edge detector for inputting a received clock signal output from a demodulator, detecting a changing point of the clock signal and outputting a first pulse signal, and a reproduced clock signal described later. A second edge detector that detects a change point of the clock signal and outputs a second pulse signal, a first pulse signal from the first edge detector, and a second edge detector from the second edge detector. A first JK- which inputs the second pulse signal and outputs an up signal which becomes active by an amount corresponding to the phase difference when the phase of the first pulse signal leads the phase of the second pulse signal. F / F, on the contrary, first
The second JK-F / F which outputs a down signal which becomes active by the delay phase difference when the phase of the pulse signal is delayed from the phase of the second pulse signal, and the rising of the reception clock signal. A third edge detector that detects a falling edge and outputs a third pulse signal, and an up signal output by the first JK-F / F are input, and the up signal counts up when the up signal is active. The first counter that outputs the first carry-up signal when the maximum value and the down signal that the second JK-F / F outputs are input and count up by counting when the down signal is active. A second counter that outputs a second carry-up signal when the value becomes maximum, and a first carry by inputting the first carry-up signal and the second carry-up signal The count value is increased when the UP signal is input before the second carry-up signal, and conversely, when the second carry-up signal is input before the first carry-up signal, the count value is increased. A second up / down counter that outputs a count value as an initial value of the first up / down counter while down, an up signal from the first JK-F / F, and the second JK-F / F. From the CPU and the output signal of the second up / down counter and the HOLD signal from the CPU are input, and the count value of the second up / down counter is used as the initial value of the first up / down counter to raise the reception clock signal. A first up-down counter that loads in a downward direction, a count value of the first up-down counter, and a third value from the third edge detector. D converting a latch circuit the third pulse signal inputs the pulse signal holds the count value of the first up-down counter when active, the latched count value into an analog signal
/ A converter, and a voltage controlled oscillator that changes an oscillation frequency according to an analog signal of the D / A converter,
A clock regenerator comprising: a frequency divider that divides the output signal of the voltage-controlled oscillator to the same frequency as the reception clock signal from the demodulator and outputs the regenerated clock signal. 3. A first edge detector for inputting a received clock signal output from a demodulator, detecting a change point of the clock signal and outputting a first pulse signal, and inputting a reproduced clock signal described later. A second edge detector that detects a change point of the clock signal and outputs a second pulse signal, a first pulse signal from the first edge detector, and a second edge detector from the second edge detector. A first JK- which inputs the second pulse signal and outputs an up signal which becomes active by an amount corresponding to the phase difference when the phase of the first pulse signal leads the phase of the second pulse signal. F / F, on the contrary, first
The second JK-F / F which outputs a down signal which becomes active by the delay phase difference when the phase of the pulse signal is delayed from the phase of the second pulse signal, and the rising of the reception clock signal. A third edge detector that detects a falling edge and outputs a third pulse signal, an up signal output from the first JK-F / F, and a HOLD signal from the CPU are input to activate the up signal. A third counter that sometimes counts up and outputs a third carry-up signal when the count value reaches a maximum, and a third carry-up signal output by the third counter are input to count up and count. A fourth counter that outputs a fourth carry-up signal when the value becomes maximum, a third carry-up signal, a fourth carry-up signal, and a switching signal from the CPU And a second selector JK-F / F which outputs a first selector for selecting and outputting either the third carry-up signal or the fourth carry-up signal in accordance with the switching signal from the CPU. Up signal and C
A HOLD signal from the PU is input, and a fifth counter that counts up when the up signal is active and outputs a fifth carry-up signal when the count value reaches the maximum and a fifth counter are output. A sixth counter for inputting a fourth carry-up signal, counting up, and outputting a sixth carry-up signal when the count value reaches a maximum, a fifth carry-up signal, and a sixth carry-up signal. A second selector for inputting a signal and a switching signal from the CPU and selecting and outputting either the fifth carry-up signal or the sixth carry-up signal according to the switching signal from the CPU; Input the output signal of the first selector and the output signal of the second selector, and increase the count value when the output signal of the first selector is active. While the output signal of the second selector is down the count value when active, the second up-down counter that outputs a count value as an initial value of the first up-down counter, said first JK
-The up signal from the F / F, the down signal from the second JK-F / F, the output signal from the second up / down counter, and the HOLD signal from the CPU are input to the second up / down counter. A first up / down counter that loads the count value as an initial value of the first up / down counter at the falling edge of the reception clock signal, the count value of the first up / down counter, and the third edge detector. A latch circuit that receives the third pulse signal and holds the count value of the first up / down counter when the third pulse signal is active, and a D / A converter that converts the latched count value into an analog signal. ,
A voltage-controlled oscillator that changes an oscillation frequency according to an analog signal of the D / A converter, and an output signal of the voltage-controlled oscillator is divided to the same frequency as a reception clock signal from the demodulator and output as a reproduction clock signal. And a clock recovery device having a frequency divider. 4. An EX-OR for inputting an up signal output by a first JK-F / F and a down signal output by a second JK-F / F and outputting an exclusive OR of both signals. A third JK- for inputting a gate, the output signal of the EX-OR gate and the output signal of the third edge detector and outputting a reset signal for resetting the entire device when both signals are active. The clock recovery device according to claim 3, further comprising an F / F.