JPH098460A - Electronic component mounting board - Google Patents

Abstract

PURPOSE: To provide an electronic component mounting board which can improve the efficiency of a wiring while the whole thickness of the board is prevented from being increased. CONSTITUTION: A first group of pads are formed on the outermost layer of a build-up layer B1 formed by laminating alternately interlayer insulating layers 8a and 8b and internal layer conductor layers 9a and 9b. The layers 8a and 8b of the layer B1 consist of a photosensitive resin, which is hardly soluble to an acid or an oxidizing agent, and heat-resistant resin particles, which are soluble to the acid and the oxidizing agent. A wiring is always provided in the forward direction and centrifugally toward the outer peripheral parts of a board while the layer 9a linking the pads 12, which constitute the first group of the pads, with each other and an internal layer conductor layer 9a linking pads 13, which constitute a second group of the pads 13, with each other are respectively connected with the layers 8a and 8b and interlayer insulating layers 8a and 8b through via holes 11 formed in the layers 8a and 8b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board for mounting electronic parts.

[0002]

2. Description of the Related Art Conventionally, as a printed wiring board for mounting a bare chip such as a flip chip or a package such as a BGA, an electronic component mounting substrate 21 as shown in FIG. 3 has been known. There is.

In this type of electronic component mounting substrate 21, a double-sided plate having conductor layers formed on the front and back sides, which are mainly formed by a subtractive method, is used as a base substrate 22. A component mounting area is provided in the center of the surface of the base substrate 22. In the same area, a first pad group including a large number of pads 23 is formed in a dense state. The formation position of each pad 23 corresponds to the position of the bump BP on the bottom surface of the bare chip C1 which is an electronic component. On the other hand, a second pad group including a large number of pads 24 is formed on the outer peripheral portion of the back surface of the base substrate 22. Bumps 25 are formed on these pads 24 as projecting electrodes for connecting to the motherboard. Further, a large number of through holes 26 penetrating the front and back are formed on the outer peripheral portion of the base substrate 22. These through holes 26 and the pads 23 on the front surface side are connected via a conductor pattern 27 formed on the surface of the base substrate 22. Further, the through hole 26 and the pad 24 on the back surface side are similarly connected via a conductor pattern 28 formed on the back surface of the base substrate 22. As a result, in the electronic component mounting board 21, the first pad group and the second pad group are electrically connected to each other.

[0004]

However, in the case of the conventional electronic component mounting substrate 21, as shown in FIG. 3, the wiring which has been once pulled out to the outer peripheral portion on the front surface side is pulled back toward the center on the rear surface side. It has a structure. Therefore, the wiring connecting the pads 23 and 24 is apt to be longer than necessary, and the wiring efficiency is poor. Further, in the electronic component mounting apparatus using such an electronic component mounting substrate 21, there is a problem that it is difficult to achieve high speed.

Further, in order to connect the pads 23 and 24 with the shortest wiring length, it is considered that the through hole 26 may be formed not in the outer peripheral portion of the substrate but in the central portion of the substrate. However, in this case, an unwiring space (dead space) is formed by the formation area of the through hole 26.
Therefore, when trying to secure a space for wiring, there is a situation in which the size of the entire device cannot be avoided.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an electronic component mounting substrate capable of improving wiring efficiency while avoiding an increase in size of the whole. .

[0007]

In order to solve the above-mentioned problems, the invention according to claim 1 is a first connection comprising a plurality of connection terminals densely formed in the central portion on the front surface side. In the electronic component mounting board, in which the terminal group and a second connection terminal group formed of a plurality of connection terminals formed on the outer peripheral portion on the back surface side are electrically connected, the first connection terminal group includes: Formed on the outermost layer of the build-up layer, which is formed by alternately stacking an interlayer insulating layer and an inner conductor layer, which are composed of a photosensitive resin hardly soluble in an acid or an oxidant and heat-resistant resin particles soluble in an acid or an oxidant. The inner conductor layer connecting the first connection terminal group and the second connection terminal group is always connected in the forward direction toward the outer peripheral portion of the substrate while being connected by the via hole formed in the interlayer insulating layer. And the wires are centrifugally wired. The component mounting board as its gist.

According to a second aspect of the present invention, in the first aspect, the interlayer insulating layer is a composite resin of a resin that is hardly soluble in an acid or an oxidant and is made by sensitizing a thermosetting resin, and a thermoplastic resin. The main point is that the heat-resistant resin particles are soluble in an acid or an oxidizing agent.

According to a third aspect of the present invention, in the second aspect, the resin which is hardly soluble in the acid or the oxidizing agent and which is obtained by sensitizing a thermosetting resin is at least selected from an epoxy acrylate and a photosensitive polyimide. It is any one resin, and the gist is that the thermoplastic resin is at least one resin selected from polyether sulfone, polysulfone, phenoxy resin, and polyethylene.

The invention according to claim 4 is the invention according to claim 2 or 3, wherein the heat resistant resin particles are at least one selected from amino resin particles and epoxy resin particles. And

[0011]

According to the first to fourth aspects of the invention, the length of the wiring connecting the first and second connection terminals is shortened because the wiring is not pulled back. Further, since the heat resistant resin particles are contained in the interlayer insulating layer, light scattering is likely to occur during exposure. Therefore, even if the via hole has a high aspect ratio, the undeveloped residue is less likely to occur during the formation thereof. Therefore, a small-diameter via hole can be formed easily and reliably. Therefore, since the via hole can be formed in the central portion where the wiring is densely arranged, the wiring can be arranged in the forward direction from the central portion to the outer peripheral portion through the via hole, and the wiring is not pulled back. The wiring length between the second connection terminals becomes shorter.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail below with reference to FIG. In this electronic component mounting substrate 1, a double-sided plate 2 is used as a base substrate. The double-sided plate 2 has conductor layers 3 and 4 formed by a subtractive method on both the front surface S1 and the back surface S2 of a resin base material 5. Through-holes 6 are formed over the entire surface of the double-sided plate 2 for establishing conduction between the conductor layers 3 and 4.
Are formed. The through holes 6 are filled with a conductive resin 7 containing a metal powder such as copper.

Interlayer insulating layers 8a, 8b and conductor layers 9a, 9 are provided on the front surface S1 and the back surface S2 of the double-sided plate 2 which is a base substrate.
Buildup layers B1 and B2 are formed by alternately stacking b and B, respectively.

Build-up layer B formed on the surface S1 side
In 1, the permanent resist 10 is formed on the upper surface of the first interlayer insulating layer 8a located in the inner layer. The inner conductor layer 9a is formed in the portion where the permanent resist 10 is not formed. The inner conductor layer 9a and the inner conductor layer 3 on the double-sided plate 2 side are the first interlayer insulating layer 8a.
Are electrically connected by a via hole 11 provided in the. In addition, a second layer provided on the interlayer insulating layer 8a
A permanent resist 10 is similarly formed on the interlayer insulating layer 8b. An outer conductor layer 9b is formed on a portion where the permanent resist 10 is not formed. The outer conductor layer 9b and the inner conductor layer 9a are electrically connected to each other by a via hole 11 provided in the second interlayer insulating layer 8b. In addition, the second interlayer insulating layer 8b
The central part of is a bare chip C1 of an LSI as an electronic component.
It is a component mounting area for mounting. In this area, a first pad group including a large number of pads 12 as connection terminals is formed in a dense state. The positions of these pads 12 correspond to the positions of the bumps BP formed on the bottom surface of the bare chip C1.

Build-up layer B formed on the surface S2 side
2, a permanent resist 10 is formed on the first interlayer insulating layer 8a located in the inner layer. The inner conductor layer 9a is formed on the portion where the permanent resist 10 is not formed.
Are formed. The inner conductor layer 9a and the inner conductor layer 4 on the double-sided plate 2 side are electrically connected to each other by a via hole 11 provided in the first interlayer insulating layer 8a. Further, a permanent resist 10 is similarly formed on the second interlayer insulating layer 8b provided on the interlayer insulating layer 8a. An outer conductor layer 9b is formed on a portion where the permanent resist 10 is not formed. The outer conductor layer 9b and the inner conductor layer 9a are electrically connected to each other by a via hole 11 provided in the second interlayer insulating layer 8b. In addition, a second pad group including a large number of pads 13 as connection terminals is formed on the outer peripheral portion of the second interlayer insulating layer 8b. Bumps 14 are formed on these pads 13 as projecting electrodes for electrical connection with the motherboard (not shown).

In this electronic component mounting substrate 1, the first
The pads 12 constituting the pad group of are outer conductor layers 9b,
Via hole 11, inner conductor layer 9a, via hole 11
And to the through hole 6 through the inner conductor layer 3. The inner conductor layer 4 connected to the through hole 6 is connected to the pad 13 constituting the second pad group via the via hole 11, the inner conductor layer 9a, the via hole 11 and the outer conductor layer 9b. There is. In addition, the inner conductor layers 3, 4, 9a and the outer conductor layer 9b are the via holes 1
While being connected by 1, the wires are always wired forward and centrifugally toward the outer peripheral portion of the substrate. Note that some of the pads 12 and 13 may be directly connected to the upper surface of the via hole 11 without being connected to the outer conductor layer 9b. The via hole 11 in the first interlayer insulating layer 8a and the via hole 11 in the second interlayer insulating layer 8b may be arranged in series.

Here, the interlayer insulating layers 8a and 8b constituting the buildup layers B1 and B2 are composed of a photosensitive resin which is hardly soluble in an acid or an oxidant, and heat resistant resin particles which are soluble in the acid or the oxidant. It is necessary. The reason for this is that when heat-resistant resin particles are contained, light is likely to be scattered during exposure, so that the via hole 11 having a high aspect ratio is used.
Even in this case, it is difficult for the residual development to occur during the formation. In addition, when only a photosensitive resin is used,
It becomes difficult to form the via hole 11 having a small diameter (about 80 μm or less).

The interlayer insulating layers 8a and 8b are composed of a composite resin of a resin and a thermoplastic resin which are poorly soluble in an acid or an oxidizing agent and which are made by sensitizing a thermosetting resin, and a heat-resistant resin soluble in an acid or an oxidizing agent. It is preferably composed of particles. The reason is to form an anchor for improving the adhesion between the interlayer agent and the copper plating. The acid or oxidizing agent referred to herein means, for example, chromic acid, chromate, permanganate, etc. used in the surface roughening step.

The resin which is hardly soluble in the acid or the oxidant and which is obtained by sensitizing a thermosetting resin is at least one resin selected from epoxy acrylate and photosensitive polyimide (photosensitive PI). preferable. The reason is that it has high heat resistance and high strength.

The thermoplastic resin is preferably at least one resin selected from polyether sulfone (PES), polysulfone (PSF), phenoxy resin and polyethylene (PE). The reason is that while maintaining the characteristics of the thermosetting resin, high T
This is because it is possible to impart a high elastic modulus.

The heat-resistant resin particles are preferably at least one selected from amino resin particles and epoxy resin (EP resin) particles. The reason is that the characteristics of the interlayer insulating layer are not deteriorated. Since the epoxy resin cured with the amine-based curing agent has a hydroexiether structure, particles made of this resin have an advantageous property of being particularly easily dissolved.
As the amino resin particles, for example, melamine resin,
Urea resin, guanamine resin, etc. can be selected. Among them, the choice of melamine resin is important for electrical characteristics, PC
It is preferable in that the T and HHBT characteristics are improved.

The heat-resistant resin particles preferably have a particle size of 10 μm or less. The reason is that the interlayer film thickness can be reduced and a fine pattern can be formed.
As the shape of the heat resistant resin particles, various shapes such as true spheres, crushed pieces, and aggregated particles can be selected.

The electronic component mounting substrate 1 having such a configuration
Can be produced, for example, by the following procedure. The method for preparing the additive adhesive for forming the interlayer insulating layers 8a and 8b is as follows. A sensitizing oligomer (C) in which 25% of the epoxy groups of a cresol novolac type epoxy resin is acrylated
NA25, molecular weight 4000), PES (molecular weight 1700)
0), imidazole curing agent (Shikoku Kasei, trade name: 2B
4MZ-CN), trimethyltriacrylate (TMPTA) which is a photosensitive monomer, and a photoinitiator (manufactured by Ciba-Geigy, trade name: I-907), and mixed with DMF in the following composition, and to this mixture: Epoxy resin powder (Toray, trade name: Trepearl EP-B) having an average particle size of 5.5 μm, 20 parts by weight, an average particle size of 0.5 μm
After mixing 10 parts by weight of the above, the viscosity is adjusted to 120 cps with a homodisper stirrer, and then kneaded with a three-roll mill to obtain an adhesive for additives. Then, after applying the adhesive to both sides of the double-sided plate 2,
Drying is performed at 0 ° C., and UV curing and heat curing are further performed.
As a result, first, the first interlayer insulating layer 8a is formed.

Next, the surface of the first interlayer insulating layer 8a is treated with a roughening agent such as chromic acid to form a roughened surface having a large number of anchor recesses. Then, the inner layer conductor layer 9a and the via hole 11 are formed by applying catalyst nuclei, forming the permanent resist 10, activation treatment, and electroless copper plating according to a conventional method.

Further, the same adhesive for additive is applied and cured on both sides to form the second interlayer insulating layer 8b. Then, the surface of the obtained second interlayer insulating layer 8b is treated with a roughening agent to form a roughened surface. After that, catalyst nucleation, formation of permanent resist 10, activation treatment and electroless copper plating are performed to form outer conductor layer 9b, pads 12 and 13 and via holes 11 at predetermined portions. Through the above steps, the desired electronic component mounting substrate 1 is completed. Then, by mounting the bare chip C1 on the electronic component mounting substrate 1 thus obtained, the electronic component mounting apparatus M1 as shown in FIG. 1 can be obtained.

In the present embodiment, the pads 12,
The inner conductor layers 3, 4, 9b and the outer conductor layer 9b connecting between 13 are connected by via holes 11 and are always wired forward and centrifugally toward the outer peripheral portion of the substrate. Therefore, this is different from the conventional structure in which the wiring that has been once pulled to the outer peripheral portion is pulled back toward the center (see FIG. 3). Therefore, the length of the wiring connecting between the pads 12 and 13 is shortened by the amount that such wiring is not pulled back, and the wiring efficiency is surely improved. Therefore, it is possible to realize the electronic component mounting apparatus M1 having a high processing speed.

Further, in this embodiment, the buildup layer B1
, B2 are formed by using an additive adhesive composed of a photosensitive resin hardly soluble in acid or the like and heat-resistant resin particles soluble in acid or the like. Therefore, it is difficult for an undeveloped residue to occur on the bottom surface of the via hole forming recess during exposure. Therefore, it is possible to easily and surely form the via hole 11 having a smaller diameter than the conventional one. Of course, the conductor layers 9a and 9b formed by the additive method are finer than those formed by the conventional subtractive method. That is, the above configuration is extremely convenient for downsizing the electronic component mounting substrate 1.

Further, in this electronic component mounting substrate 1,
The wiring is formed not only on the conductor layers 3 and 4 of the double-sided plate 2 but also on the conductor layers 9a and 9b of the buildup layers B1 and B2. For this reason, even if the double-sided plate 2 has the through hole 6, it does not particularly affect the wiring, and it is not necessary to secure a space for wiring as in the conventional case. This means that the electronic component mounting board 1 can be surely prevented from increasing in size.

Then, in this electronic component mounting substrate 1,
Build-up layers B1 and B2 having substantially the same thickness are provided on the front surface S1 and the back surface S2. Therefore, the magnitudes of the stresses applied to both sides of the double-sided plate 2 become substantially equal, and as a result, the stresses tend to cancel each other. Therefore, it is possible to realize the electronic component mounting substrate 1 which is hard to warp.

The present invention can be modified as follows, for example. (1) FIG. 2 shows an electronic component mounting apparatus M2 in which a bare chip C1 is mounted on an electronic component mounting substrate 18 of another example. In this electronic component mounting substrate 18, the surface S
The build-up layer B3 having a three-layer structure is provided only on the 1st side. On the other hand, the pads 13 forming the second pad group are
It is connected to the conductor layer 4 formed on the back surface S2 side. The conductor layer 4 on the back surface S2 side is entirely covered with the solder resist 19. Even with such a configuration, the same operational effect as that of the embodiment can be obtained.

(2) The number of build-up layers B1 to B3 (the number of layers of the interlayer insulating layers 8a and 8b) is not limited to two layers or three layers, but only one layer or four layers, five layers, 6
It may be a layer, a 7 layer, an 8 layer ... Further, the number of stacked layers on the front surface S1 side and the number of stacked layers on the back surface S2 side do not necessarily have to be the same.

(3) Instead of the embodiment using the double-sided plate 2 as the base substrate, a 4-layer plate, a 5-layer plate, a 6-layer plate, a 7-layer plate, 8
You may use multilayer boards, such as a layer board. In addition, it is advantageous to select the double-sided plate 2 when priority is given to cost reduction, and it is advantageous to select a multi-layer plate when it is desired to achieve higher density and size reduction.

(4) Pins or the like can be provided on the pads 13 forming the second connection terminal group, instead of the bumps 14 of the embodiment. Further, it is of course possible to adopt a configuration in which neither the bump 14 nor the pin is provided.

(5) The component mounting area is 1 as in the embodiment.
There may be only one or a plurality. (6) The back surface S of the pad 13 that constitutes the second pad group is
It may be provided over the entire buildup layer B2 on the second side. With this configuration, more pads 13
Can be arranged.

(7) The conductor layers 9a and 9b constituting the buildup layers B1 to B3 may be metal plating other than electroless copper plating (for example, electroless nickel plating or electroless gold plating). Further, instead of the metal layer formed by a chemical film forming method such as plating, it is possible to select a metal layer formed by a physical thin film method such as sputtering.

(8) The electronic component mounted on the electronic component mounting substrate 1 may be a semiconductor package such as BGA, QFN, or PGA having a short pin, in addition to the bare chip 2 of the embodiment.

(9) A combination of a resin obtained by sensitizing a thermosetting resin, a thermoplastic resin and a heat resistant resin (R1 + R2 +
R3) may be those listed below in addition to the combinations of the examples. That is, R1 + R2 + R
3 = epoxy acrylate + PES + amino resin, epoxy acrylate + PSF + EP, epoxy acrylate + phenoxy resin + EP, epoxy acrylate + P
E + EP, epoxy acrylate + PSF + amino resin, epoxy acrylate + phenoxy resin + amino resin, epoxy acrylate + PE + amino resin, epoxy acrylate + PES + amino resin and EP, epoxy acrylate + PSF + amino resin and EP, epoxy acrylate + phenoxy resin + amino resin and E
P, epoxy acrylate + PE + amino resin and E
P, Photosensitive PI + PES + EP, Photosensitive PI + PES +
Amino resin, photosensitive PI + PSF + EP, photosensitive PI +
Phenoxy resin + EP, photosensitive PI + PE + EP, photosensitive PI + PSF + amino resin, photosensitive PI + phenoxy resin + amino resin, photosensitive PI + PE + amino resin, photosensitive PI + PES + amino resin and EP, photosensitive PI +
PSF + amino resin and EP, photosensitive PI + phenoxy resin + amino resin and EP, photosensitive PI + PE + amino resin and EP, epoxy acrylate and photosensitive PI +
PES + amino resin, epoxy acrylate and photosensitive PI + PSF + EP, epoxy acrylate and photosensitive PI + phenoxy resin + EP, epoxy acrylate and photosensitive PI + PE + EP, epoxy acrylate and photosensitive PI + PSF + amino resin, epoxy acrylate and photosensitive PI + phenoxy resin + amino resin, epoxy Acrylate and photosensitive PI + PE + amino resin,
Epoxy acrylate and photosensitive PI + PES + amino resin and EP, epoxy acrylate and photosensitive PI +
PSF + amino resin and EP, epoxy acrylate and photosensitive PI + phenoxy resin + amino resin and EP,
Epoxy acrylate and photosensitive PI + PE + amino resin and EP. Of course, other possible combinations not listed here are also acceptable.

Here, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiments and other examples will be listed below together with their effects. (1) In any one of claims 1 to 3, the build-up layers are provided on both sides of a base substrate. With this configuration, the wiring efficiency can be further improved and warpage is less likely to occur.

(2) In claim 1, the interlayer insulating layer is 25% acrylated epoxy acrylate, P
Consists of ES, epoxy resin particles (mixture of 5.5 μm and 0.5 μm) and photosensitive monomer. With this configuration, the wiring efficiency can be further improved.

(3) In the technical idea (2), the epoxy resin particles are replaced with melamine resin particles. With this configuration, the wiring efficiency can be further improved. In addition,
The technical terms used in this specification are defined as follows.

"Acid or oxidizing agent: chromic acid, chromate, permanganate, used in the surface roughening step,
Refers to hydrochloric acid, phosphoric acid, formic acid, sulfuric acid, hydrofluoric acid and the like. "

[0042]

As described above in detail, according to the inventions described in claims 1 to 4, it is possible to provide an electronic component mounting substrate capable of improving wiring efficiency while avoiding an increase in size of the whole. You can In particular, according to the invention described in claims 2 to 4, it is possible to more surely avoid the increase in size of the whole.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an electronic component mounting substrate of an embodiment.

FIG. 2 is a schematic cross-sectional view showing another example of an electronic component mounting board.

FIG. 3 is a schematic cross-sectional view showing a conventional electronic component mounting substrate.

[Explanation of symbols]

1, 18 ... Substrate for mounting electronic parts, 8a, 8b ... Interlayer insulating layer, 9a ... Inner conductor layer, 11 ... Via hole, 12, 1
3 ... Pads as connection terminals, S1 ... Front surface, S2 ... Back surface, B1, B2, B3 ... Buildup layer.

Claims (4)

[Claims] 1. A first connection terminal group composed of a plurality of connection terminals formed in a dense state in a central portion on the front surface side, and a second connection terminal composed of a plurality of connection terminals formed on an outer peripheral portion on the back surface side. In the electronic component mounting substrate, in which a connection terminal group is electrically connected, the first connection terminal group is a photosensitive resin that is hardly soluble in an acid or an oxidant and a heat-resistant resin that is soluble in an acid or an oxidant The inner layer formed on the outermost layer of a buildup layer formed by alternately laminating an interlayer insulating layer and an inner conductor layer composed of particles, and connecting the first connection terminal group and the second connection terminal group. A board for mounting electronic parts, wherein the conductor layers are connected by via holes formed in the interlayer insulating layer and are always wired in a forward direction toward the outer peripheral portion of the board in a centrifugal manner. 2. The interlayer insulating layer is a composite resin of a resin and a thermoplastic resin, which are hardly soluble in an acid or an oxidant and have a thermosetting resin sensitized, and a heat-resistant resin particle in which an acid or an oxidant is soluble. The electronic component mounting substrate according to claim 1, comprising: 3. The resin which is sparingly soluble in an acid or an oxidant and which is obtained by sensitizing a thermosetting resin is at least one resin selected from epoxy acrylate and photosensitive polyimide. The electronic component mounting board according to claim 2, wherein is at least one resin selected from polyether sulfone, polysulfone, phenoxy resin, and polyethylene. 4. The electronic component mounting substrate according to claim 2, wherein the heat resistant resin particles are at least one selected from amino resin particles and epoxy resin particles.