JP3181193B2 - Substrate for mounting electronic circuit components - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit component mounting board having connection terminals on both sides.

[0002]

2. Description of the Related Art Conventionally, a so-called electronic circuit component mounting board has been known as a printed wiring board for mounting electronic circuit components.

In this type of electronic circuit component mounting board, a double-sided board having a conductor layer formed by a subtractive method on both front and back surfaces of a base material is used as a base board. In the central part of the surface of the base substrate, usually, an LSI bare chip such as a flip chip,
An area for surface mounting a package such as a BGA is provided. In the area, a first pad group including a large number of pads is formed in a dense state. On the other hand, a second pad group including a large number of pads is formed on the outer peripheral portion on the back surface of the base substrate. And
Bumps are formed on these pads as bump electrodes for connection with the motherboard. Also,
A large number of through holes penetrating the front and back are formed in the outer peripheral portion of the base substrate. These through holes and the first
Each of the pads constituting the pad group is connected via a conductor pattern formed on the surface of the base substrate. Further, the through-holes and the respective pads constituting the second pad group are similarly connected via conductor patterns formed on the back surface of the base substrate. As a result, in the electronic circuit component mounting board, the first pad group and the second pad group are electrically connected to each other.

[0004]

When a conductor pattern is formed on the front surface side, it is not so much to draw the conductor pattern from the pads located on the outer periphery of the first pad group toward the outer periphery of the base substrate. Not difficult. On the other hand, with respect to the pads located at the center of the pad group, the pads located outside thereof become an obstacle, so that it is difficult to draw out the conductor pattern to the outer periphery.
Therefore, in order to draw out the conductor pattern from the pad, the wiring density must be reduced as a whole. Therefore, there is a problem that the density and size of the electronic circuit component mounting board cannot be sufficiently increased.

In recent years, multilayer boards such as four-layer boards and six-layer boards using mass lamination technology have been manufactured. However, even if such a multilayer board is used as a base substrate, it cannot be said that there is a certain limit to high density and miniaturization.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an electronic circuit component mounting substrate capable of achieving high density and miniaturization.

[0007]

According to a first aspect of the present invention, a first connection terminal group is provided at a predetermined position on one surface of a base substrate having a through hole.
The second connection terminal group is formed in a dense state, and the second connection terminal group is formed at least on the outer peripheral portion of the opposite surface, and the first connection terminal group and the second connection terminal group are electrically connected through a through hole. In the connected electronic circuit component mounting board, on the side of the base board where the first connection terminal group is formed,
An inner conductor layer and an insulating layer are alternately laminated, a build-up multilayer wiring layer is formed in which the inner conductor layers are electrically connected to each other through via holes, and the inner conductor layers are electrically connected to the through holes. Wherein the first connection terminal group comprises:
A connection terminal formed at the outermost layer of the build-up multilayer wiring layer and located at the center of the first connection terminal group is electrically connected to an inner conductor layer of the build-up multilayer wiring layer via a via hole. Connected to the first connection terminal
Connections located outside the connection terminals located in the center of the group
The connection terminal is connected to the outer conductor layer extending toward the outer peripheral portion of the substrate.
The gist is an electronic circuit component mounting substrate characterized by being continued .

According to a second aspect of the present invention, the first connection terminal group is formed at a predetermined position on one surface of the base substrate having a through hole in a dense state, and the first connection terminal group is formed on at least the outer peripheral portion of the opposite surface. An electronic circuit component mounting board in which a second connection terminal group is formed and the first connection terminal group and the second connection terminal group are electrically connected via through holes; Has a built-up multilayer wiring layer in which inner conductor layers and insulating layers are alternately laminated, the inner conductor layers are electrically connected to each other via holes, and the inner conductor layers are electrically connected to through holes. Are formed, and the first connection terminal group and the second connection terminal group are
Each of the connection terminals formed on the outermost layer of the build-up multilayer wiring layer and located at the center of the first connection terminal group and the connection terminals constituting the second connection terminal group are connected via via holes. And electrically connected to the inner conductor layer of the build-up multilayer wiring layer by the first connection terminal.
Connections located outside the connection terminals located in the center of the group
The connection terminal is connected to the outer conductor layer extending toward the outer peripheral portion of the substrate.
The gist is an electronic circuit component mounting substrate characterized by being continued .

[0009]

According to the first and second aspects of the present invention, the connection terminal located at the center of the first connection terminal group is connected to the inner conductor layer via the via hole. It is not necessary to draw out the conductor layer to the part. Therefore, even when wiring is performed, the connection terminal located outside the connection terminal does not become an obstacle. In addition, since the via holes and the inner conductor layer are formed in the build-up multilayer wiring layer, the wiring density can be increased as compared with the related art.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below in detail with reference to FIG. This electronic circuit component mounting substrate 1
Here, a double-sided board 2 is used as a base substrate. The double-sided board 2 is formed by connecting the conductor layers 3 and 4 formed by the subtractive method to the front surface S1 and the back surface S2 of the resin base material 5.
Have both. Through holes 6 for conducting between the conductor layers 3 and 4 are provided on the entire surface of the double-sided board 2.
Are formed. These through holes 6 are filled with a conductive resin 7 containing a metal powder such as copper.

On the front surface S1 and the back surface S2 of the double-sided board 2 as a base substrate, interlayer insulating layers 8a and 8b and conductor layers 9a and 9b are provided.
b) and a build-up multilayer wiring layer B1 formed by alternately stacking
, B2 are formed respectively.

In the build-up multilayer wiring layer B1 formed on the surface S1 side, a permanent resist 10 is formed on the upper surface of the first interlayer insulating layer 8a located in the inner layer.
An inner conductor layer 9a is formed in a portion where the permanent resist 10 is not formed. The inner conductor layer 9a and the inner conductor layer 3 on the double-sided board 2 are electrically connected by via holes 11 provided in the first interlayer insulating layer 8a. Further, a permanent resist 10 is similarly formed on the second interlayer insulating layer 8b provided on the interlayer insulating layer 8a. An outer conductor layer 9b is formed in a portion where the permanent resist 10 is not formed. The outer conductor layer 9b and the inner conductor layer 9a are connected to the via hole 1 provided in the second interlayer insulating layer 8b.
1 electrically connected. The central portion of the second interlayer insulating layer 8b is a component mounting area for mounting a bare chip C1 of an LSI as an electronic circuit component. In this area, a first pad group including a large number of pads 12A and 12B as connection terminals is formed in a dense state. Note that these pads 12A,
The position 12B corresponds to the formation position of the bump BP formed on the bottom surface of the bare chip C1. Note that the outermost one in the first pad group is referred to as “external pad 12B”. The pad located at the center of the first pad group, that is, the pad located inside the external pad 12B is referred to as "internal pad 12A".

[0013] In the build-up multilayer wiring layer B2 formed on the back surface S2 side, on the first interlayer insulating layer 8a that is located in an inner layer, a permanent resist 10 is formed. An inner conductor layer 9a is formed in a portion where the permanent resist 10 is not formed. The inner conductor layer 9
a and the inner conductor layer 4 on the side of the double-sided board 2 are electrically connected by via holes 11 provided in the first interlayer insulating layer 8a. Similarly, the permanent resist 10 is formed on the second interlayer insulating layer 8b provided on the interlayer insulating layer 8a.
Are formed. An outer conductor layer 9b is formed in a portion where the permanent resist 10 is not formed. The outer conductor layer 9b and the inner conductor layer 9a are
Are electrically connected by via holes 11 provided in the interlayer insulating layer 8b. Also, the second interlayer insulating layer 8
A second pad group including a large number of pads 13 as connection terminals is formed on the outer peripheral portion of b. Bumps 14 are formed on these pads 13 as protruding electrodes for establishing electrical connection with a motherboard (not shown).

In this electronic circuit component mounting board 1,
External pad 12B of the first pad group
Is electrically connected to the via hole 11 via an outer conductor layer 9b extending toward the outer peripheral portion of the substrate. On the other hand, the internal pad 12A located inside is
It is directly electrically connected to the upper surface of the via hole 11 without passing through the outer conductor layer 9b. The via hole 11 of the second interlayer insulating layer 8b is further electrically connected to the through hole 6 via the inner conductor layer 9a, the via hole 11, and the inner conductor layer 3. The inner conductor layer 4 connected to the through hole 6 is connected to the pad 1 forming the second pad group via the via hole 11, the inner conductor layer 9a, the via hole 11, and the outer conductor layer 9b.
3 is electrically connected. The inner conductor layers 3, 4, 9a and the outer conductor layer 9b connecting the first pad group and the second pad group are always wired forward and centrifugally toward the outer peripheral portion of the substrate.

Here, the build-up multilayer wiring layers B1, B
It is preferable that the interlayer insulating layers 8a and 8b constituting 2 are made of a photosensitive resin hardly soluble in an acid or an oxidizing agent and heat-resistant resin particles soluble in an acid or an oxidizing agent. The reason is that if heat-resistant resin particles are included, light scattering is likely to occur at the time of exposure, and therefore, even if the via hole 11 has a high aspect ratio, development residue hardly occurs at the time of formation. Therefore, the via hole 11 having a smaller diameter (about 80 μm or less in diameter) can be formed as compared with the case where a mere photosensitive resin is used.

The interlayer insulating layers 8a and 8b are composed of a composite resin of a resin which is hardly soluble in an acid or an oxidizing agent and which is made of a thermosetting resin and a thermoplastic resin, and a heat-resistant resin which is soluble in an acid or an oxidizing agent. It preferably comprises particles. Here, the acid or oxidizing agent refers to, for example, hydrochloric acid, phosphoric acid, chromic acid, chromate, permanganate and the like used in the surface roughening step.

[0017] The resin which is insoluble in an acid or an oxidizing agent and which is obtained by sensitizing a thermosetting resin is at least one resin selected from epoxy acrylate and photosensitive polyimide (photosensitive PI). preferable. Further, the thermoplastic resin is a polyether sulfone (PE
It is preferably at least one resin selected from S), polysulfone (PSF), phenoxy resin and polyethylene (PE). Further, it is preferable that the heat-resistant resin particles are at least one selected from amino resin particles and epoxy resin (EP resin) particles. Since the epoxy resin has a hydroethoxy ether structure, particles made of this resin have an advantageous property of being particularly easily dissolved. Further, as the amino resin particles, for example, melamine resin, urea resin, guanamine resin and the like can be selected. Among them, it is preferable to select a melamine resin.

The electronic circuit component mounting board 1 having such a configuration can be manufactured by, for example, the following procedure. The preparation method of the additive adhesive for forming the interlayer insulating layers 8a and 8b is as follows. An oligomer (CNA25, molecular weight 4000) of a cresol novolac type epoxy resin having photosensitized 25% of the epoxy group acrylated, PES (molecular weight 17)
000), imidazole curing agent (Shikoku Chemicals, trade name:
2B4MZ-CN), trimethyltriacrylate (TMPTA) which is a photosensitive monomer, and a photoinitiator (trade name: I-907, manufactured by Ciba Geigy).
F, and 20 parts by weight of an epoxy resin powder (manufactured by Toray, trade name: Trepearl EP-B) having an average particle size of 5.5 μm, and an average particle size of 0.5 μm.
After mixing 10 parts by weight of a μm product, the viscosity is adjusted to 120 cps with a homodisper stirrer, followed by kneading with a three-roll mill to obtain an additive adhesive.
Next, this adhesive is applied to both sides of the double-sided board 2, and then vacuum-dried at 25 ° C., followed by UV curing and heat curing. As a result, first, a first interlayer insulating layer 8a is formed.

Next, the surface of the first interlayer insulating layer 8a is treated with a roughening agent such as chromic acid to form a roughened surface having a large number of anchor recesses. Thereafter, the inner conductor layer 9a and the via hole 11 are formed by applying a catalyst nucleus, forming a permanent resist 10, activating and electroless copper plating according to a conventional method.

Further, the same adhesive for additive is applied and cured on both sides to form a second interlayer insulating layer 8b. Next, the surface of the obtained second interlayer insulating layer 8b is treated with a roughening agent to form a roughened surface. Thereafter, a catalyst nucleus is provided, a permanent resist 10 is formed, an activation process, and electroless copper plating are performed to form outer conductor layers 9b, pads 12A, 12B, 13 and via holes 11 in predetermined portions. Through the above steps, a desired electronic circuit component mounting substrate 1 is completed. The bare chip C is placed on the electronic circuit component mounting substrate 1 thus obtained.
1, the electronic circuit component mounting device M as shown in FIG.
You can get one.

According to the electronic circuit component mounting board 1 of the present embodiment, the internal pads 12A located at the center of the first pad group are not connected to the outer conductor layer 9b, and are not connected to the vias. It is directly electrically connected to the upper surface of the hole 11. That is, each internal pad 12
A is electrically connected to the inner conductor layer 9a through the via hole 11. Therefore, on the second interlayer insulating layer 8b on which the first pad group is formed, it is not necessary to draw out the outer conductor layer 9a to the outer peripheral portion of the substrate. Therefore, even if the external pad 12B is located outside the internal pad 12A,
They do not particularly hinder the wiring. As a result, the outer conductor layer 9b pulled out from the internal pad 12A does not exist as described above.
The outer conductor layer 9b drawn from the external pad 12B can be densely wired. That is, the overall wiring density can be increased as compared with the conventional configuration.

In the present embodiment, in forming the interlayer insulating layers 8a and 8b constituting the build-up multilayer wiring layers B1 and B2, a photosensitive resin which is hardly soluble in an acid or the like and a heat-resistant resin particle which is soluble in an acid or the like are used. And an additive adhesive is used. For this reason, development residue hardly occurs on the bottom surface of the via hole forming concave portion during exposure. Therefore, the via hole 11 having a smaller diameter than the conventional one can be formed easily and reliably. Of course, the conductor layers 9a and 9b formed by the additive method are finer than those formed by the conventional subtractive method. Therefore, the wiring density can be increased as compared with the conventional structure such as the subtractive method .

As described above, according to the electronic circuit component mounting board 1 of the present embodiment, higher density and smaller size can be achieved as compared with the conventional one. In this embodiment, since the build-up multilayer wiring layers B1 and B2 are formed on both surfaces, it is possible to achieve a higher density and a smaller size than when, for example, only the surface S1 is formed.

Further, in the electronic circuit component mounting substrate 1, build-up multilayer wiring layers B1, B2 having substantially the same thickness are provided on the front surface S1 and the back surface S2. For this reason,
The magnitudes of the stresses applied to both sides of the double-sided board 2 become substantially equal, and as a result, the stresses tend to cancel each other. Therefore, it is possible to realize the electronic circuit component mounting board 1 that is hardly warped.

The present invention can be modified, for example, as follows. (1) FIG. 2 shows an electronic circuit component mounting apparatus M2 in which a bare chip C1 is mounted on an electronic circuit component mounting board 18 of another example. This electronic circuit component mounting board 18
In this example, a build-up multilayer wiring layer B3 having a three-layer structure is provided only on the surface S1 side. On the other hand, the pad 13 constituting the second pad group is formed by the conductor layer 4 formed on the back surface S2 side.
It is connected to the. The conductor layer 4 on the back surface S2 side
The whole is covered with a solder resist 19. Even with such a configuration, the same operation and effect as those of the embodiment can be obtained.

(2) Build-up multilayer wiring layers B1 to B3
Is not limited to two or three layers, but only one layer or four or five layers.
, Six, seven, eight,... The surface S
The number of laminations on one side and the number of laminations on the back side S2 need not necessarily be the same.

(3) Instead of the embodiment using the double-sided board 2 as the base substrate, a 4-layer board, 5-layer board, 6-layer board, 7-layer board, 8
A multilayer plate such as a layer plate may be used. In addition, it is advantageous to select the double-sided board 2 when priority is given to cost reduction, and it is advantageous to select a multilayer board to achieve further higher density and smaller size.

(4) A pin or the like can be provided on the pad 13 constituting the second connection terminal group instead of the bump 14 of the embodiment. Further, it is of course possible to adopt a configuration in which neither the bump 14 nor the pin is provided.

(5) The component mounting area is 1 as in the embodiment.
There may be only one or a plurality. (6) The pad 13 constituting the second pad group has a rear surface S
It may be provided over the whole of the build-up multilayer wiring layer B2 on the second side. With this configuration, more pads 13 can be arranged.

(7) Build-up multilayer wiring layers B1 to B3
May be metal plating other than electroless copper plating (for example, electroless nickel plating or electroless gold plating). Instead of a metal layer formed by a chemical film forming method such as plating, it is also possible to select a metal layer formed by a physical thin film method such as sputtering.

(8) The electronic circuit components mounted on the electronic circuit component mounting board 1 are, for example, BGA, QFN, and PGA having short pins in addition to the bare chip 2 of the embodiment.
And the like.

[0032]

Here, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiments and other examples are listed below together with their effects. (1) In Claims 1 and 2, the insulating layer constituting the build-up multilayer wiring layer is made of a photosensitive resin. With this configuration, higher density and smaller size can be achieved.

(2) In Claims 1 and 2, the insulating layer constituting the build-up multilayer wiring layer is made of a photosensitive resin which is hardly soluble in an acid or an oxidizing agent, and a heat-resistant resin particle which is soluble in an acid or an oxidizing agent. Consisting of With this configuration, higher density and smaller size can be achieved.

"Adhesive for additive: A resin adhesive used for forming an insulating layer, which contains a component that is hardly soluble in acids and the like and a component that is soluble in acid."

[0036]

As described above in detail, according to the first aspect of the present invention, since the connection is made to the inner conductor layer via the via hole of the build-up multilayer wiring layer, the density is increased and the size is reduced. Can be provided. According to the second aspect of the present invention, further higher density and smaller size can be achieved. Furthermore, wiring design becomes easy.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of an electronic circuit component mounting board according to an embodiment.

FIG. 2 is a schematic sectional view of another example of an electronic circuit component mounting substrate.

[Explanation of symbols]

1, 18 ... board for mounting electronic circuit parts, 2 ... base board,
6 ... through-hole, 8a, 8b ... insulating layer, 3, 4, 9a
... inner conductor layer, 9b ... outer conductor layer, 11 ... via hole, 12A ... internal pad as a connection terminal located at the center of the first connection terminal group, 12B ... first connection
External unit as a connection terminal located outside the terminal group
Le Pad, 13 ... pad as a connection terminal which constitute the second connecting terminal groups, B1, B2, B3 ... build-up multilayer wiring layer.

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-63-172490 (JP, A) JP-A-6-3144752 (JP, A) JP-A-6-275959 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H05K 3/46

Claims (2)

(57) [Claims] A first connection terminal group is formed at a predetermined position on one surface of a base substrate having a through hole in a dense state, and a second connection terminal group is formed on at least the outer peripheral portion of the opposite surface. An electronic circuit component mounting substrate formed and electrically connected to a first connection terminal group and a second connection terminal group via through holes, wherein the first connection terminal group of the base substrate is formed. On the side to be built, the inner conductor layers and the insulating layers are alternately laminated, the inner conductor layers are electrically connected via holes, and the inner conductor layers are electrically connected to the through holes. A multilayer wiring layer is formed; the first connection terminal group is formed on an outermost layer of the build-up multilayer wiring layer; and a connection terminal located at a central portion of the first connection terminal group is: The building via via hole Is up multilayer interconnection layer electrically connected to the inner conductor layers, connection end located in the center of the first connecting terminal groups
Connection terminals located outside of the board
Characterized in that the substrate is connected to an outer conductor layer extending through the substrate. 2. The first connection terminal group is formed at a predetermined position on one surface of a base substrate having a through hole in a dense state, and the second connection terminal group is formed on at least the outer peripheral portion of the opposite surface. An electronic circuit component mounting board formed, wherein the first connection terminal group and the second connection terminal group are electrically connected via through holes, wherein an inner conductor layer is provided on both surfaces of the base substrate. Insulating layers are alternately laminated, the inner conductor layers are electrically connected to each other through via holes, and the build-up multilayer wiring layer in which the inner conductor layers are electrically connected to the through holes is formed. The first connection terminal group and the second connection terminal group are respectively formed on the outermost layer of the build-up multilayer wiring layer, and the connection terminal and the second connection terminal located at the center of the first connection terminal group are respectively formed. Configure connection terminals Connection terminal is electrically connected to the inner conductor layer of the build-up multilayer interconnection layer through the via hole, a center of the first connecting terminal groups
Connection terminal located outside of the connection terminal located in the section
An electronic circuit component mounting board, characterized in that connected to the outer conducting layer extending toward the substrate outside peripheral portion becomes Te <br/>.