JPH0982873A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0982873A
JPH0982873A JP23802295A JP23802295A JPH0982873A JP H0982873 A JPH0982873 A JP H0982873A JP 23802295 A JP23802295 A JP 23802295A JP 23802295 A JP23802295 A JP 23802295A JP H0982873 A JPH0982873 A JP H0982873A
Authority
JP
Japan
Prior art keywords
solder
semiconductor device
rod
substrate
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23802295A
Other languages
Japanese (ja)
Other versions
JP2735045B2 (en
Inventor
Katsushi Terajima
克司 寺島
Chikayuki Kato
周幸 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7238022A priority Critical patent/JP2735045B2/en
Publication of JPH0982873A publication Critical patent/JPH0982873A/en
Application granted granted Critical
Publication of JP2735045B2 publication Critical patent/JP2735045B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To set outer terminals extending from the lower opening of the connection holes of a board as high as prescribed and uniform in height, enhanced in reliability, and formed through a simpler process by a method wherein a solder rod is inserted into the connection holes of the board, and the protruding part of the solder rod from the second main surface of the board is made to serve as an outer terminal. SOLUTION: A semiconductor device 1 is mounted on a first main surface 31 of a board 2, and an outer terminal 10 is made protrude from the second main surface of the board 2. A conductive wiring 6 and an outer terminal 10 are electrically connected to a connection through-hole 7 or a connection half hole provided to the board 2 through a connecting means. A solder rod 9 is made to protrude continuously from the second main surface 32 of the board 2 through the connection through-hole 7 to serve as an outer terminal 10. The tip of the outer terminal 10 is kept unchanged in shape when it is cut and not formed into a hemisphere which appears when solder is fused. By this setup, the outer terminal 10 can be mounted without being thermally treated and cleaned, so that a device of high quality can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に係わり、特に表面実装型で外部端子となる
ピンを格子状に配列するPGA(Pin Grid A
rray)またはBGA(Ball Grid Arr
ay)タイプの半導体装置におけるスルーホール等の接
続ホールの直下に設けた外部端子の構造およびその形成
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a surface mount type PGA (Pin Grid A) in which pins serving as external terminals are arranged in a grid pattern.
rray) or BGA (Ball Grid Arr)
The present invention relates to a structure of an external terminal provided directly below a connection hole such as a through hole in an ay) type semiconductor device and a method for forming the external terminal.

【0002】[0002]

【従来の技術】図6に、例えば特開昭62−12374
3号公報に開示されてあるような従来技術のBGA型半
導体装置の断面図を示す。プリント基板2の第1の主面
(表面)31上に半導体素子1をマウント材3により搭
載し、ボンディングワイヤー4にてプリント基板上の導
体配線6と電気的に接続した後、封止樹脂5により封止
する。
2. Description of the Related Art FIG. 6 shows, for example, JP-A-62-12374.
FIG. 3 is a cross-sectional view of a BGA type semiconductor device of the related art as disclosed in Japanese Patent Publication No. The semiconductor element 1 is mounted on the first main surface (front surface) 31 of the printed circuit board 2 by the mount material 3, electrically connected to the conductor wiring 6 on the printed circuit board by the bonding wire 4, and then the sealing resin 5 is formed. To seal.

【0003】基板2にはスルーホール7が設けられてお
り、このスルーホールにディッピング法による溶融半田
や半田ペースト塗布後の加熱リフロー法等により、上面
で導体配線6に接続する充填半田15を充填し、さらに
基板の第2の主面(裏面)32から半田溶融により先端
が半球状となった半田を突出させた半田突出部16を形
成して外部端子10としている。
A through hole 7 is formed in the substrate 2, and the through hole 7 is filled with a filling solder 15 for connecting to the conductor wiring 6 on the upper surface by a molten solder by a dipping method or a heat reflow method after applying a solder paste. Further, a solder protrusion 16 is formed from the second main surface (rear surface) 32 of the substrate, the solder having a semi-spherical tip due to melting of the solder is formed to form the external terminal 10.

【0004】また図7にピン挿入タイプの従来技術のP
GA型半導体装置の断面図を示す。金属膜で構成されか
つ導電配線6に接続するスルーホール導電膜8が予じめ
内壁に形成してあるスルーホール7に、半田メッキを予
め施して有る金属ピン17を挿入した後、ピン先端部に
半田ディップによりボール状の半田溜り18を形成して
外部端子10としている。スルーホールの直径は0.2
〜0.4mmである。半田メッキを含めたピン径はスル
ーホール導電膜8の内径で定まるスルーホールの直径と
同じか、もしくはやや大きい突起を持たせることもあ
る。この場合、スルーホール導電膜8の金属膜および半
田メッキを含めた金属ピンの変形を伴ないながら金属ピ
ンを圧入して挿入する。半田メッキ厚は5μm前後と薄
いためにピン挿入後は不安定であるから半田ディップに
よる半田コートを施し固定する必要がある。また、基板
の第2の主面(裏面)32から突出するピン先端の半田
溜り18は半田ボールの役目をして、先端が半田の半球
状の外部端子10となる。
Further, FIG. 7 shows a prior art P of a pin insertion type.
A sectional view of a GA type semiconductor device is shown. After inserting a metal pin 17 which has been pre-plated with solder into a through hole 7 which is made of a metal film and which is formed in advance on the inner wall of the through hole conductive film 8 which is connected to the conductive wiring 6, the tip end of the pin is inserted. A ball-shaped solder pool 18 is formed by solder dipping to form the external terminal 10. Through hole diameter is 0.2
~ 0.4 mm. The pin diameter including the solder plating may have a projection that is the same as or slightly larger than the diameter of the through hole determined by the inner diameter of the through hole conductive film 8. In this case, the metal pin of the through-hole conductive film 8 and the metal pin including the solder plating are deformed and the metal pin is press-fitted and inserted. Since the thickness of the solder plating is as thin as about 5 μm, it is unstable after the pins are inserted. Therefore, it is necessary to apply a solder coat with a solder dip for fixing. Further, the solder pool 18 at the tip of the pin protruding from the second main surface (back surface) 32 of the substrate serves as a solder ball, and the tip becomes the external terminal 10 having a hemispherical shape of solder.

【0005】[0005]

【発明が解決しようとする課題】上記図6に示す半田充
填タイプでは、半田の充填が難しくボイドが発生しやす
い上、さらに先端に於ける半球状の半田の突出量のばら
つきが大きいため充分な高さを得ることが難しい。表面
実装後のスタンドオフ高さは0.25mm以上必要であ
り、これは実装後の洗浄を行うための最少高さであるた
め半導体装置としては突出部の高さを0.5mm以上確
保する必要がある。しかし突出部の高さのばらつきは大
きく、0.2mmから1mmを越えるものが出ることも
珍しくないうえコプラナリティを0.15mm以下にす
ることは殆ど不可能である。さらに実装後の溶融半田は
中にボイドがあるとスルーホールの中を逆上するため、
突出部の半田量は減少してしまい、充分な実装半田接続
が得られないという不具合がある。またフラックスがス
ルーホール内に残留することが多く、スルーホール内の
導電膜を腐食させ断線不良の原因とも成りやすかった。
In the solder filling type shown in FIG. 6 described above, it is difficult to fill the solder, and voids are likely to occur. Further, there is a large variation in the amount of protrusion of the hemispherical solder at the tip, which is sufficient. It's difficult to get high. The standoff height after surface mounting is required to be 0.25 mm or more, which is the minimum height for cleaning after mounting. Therefore, it is necessary to secure the protrusion height of 0.5 mm or more for a semiconductor device. There is. However, there is a large variation in the height of the protruding portion, and it is not uncommon for some of the protrusions to exceed 0.2 mm to 1 mm, and it is almost impossible to reduce the coplanarity to 0.15 mm or less. Furthermore, if there is a void in the molten solder after mounting, it goes upside down in the through hole,
The amount of solder on the protruding portion is reduced, and there is a problem in that sufficient mounting solder connection cannot be obtained. In addition, the flux often remains in the through hole, which easily corrodes the conductive film in the through hole and is likely to cause disconnection failure.

【0006】一方、図7に示す従来技術でも同様に半田
ディップによる半田のボリュウムの不均一性が大きく、
それをコントロールすることは非常に難しい。加えて、
ピン抜けを防止するためピン挿入部はスルーホール径よ
り大きいものを使い、圧入により挿入し、さらにピンは
堅く、このために基板はピン挿入後、基板の体積膨張に
より基板全体の反りを招きやすかった。そのためにピン
の先端長のばらつきを招きコプラナリティを大きく阻害
することになった。さらに基板が薄い場合はピンの固定
が不安定な上、垂直に立てることが困難でコプラナリテ
ィはますます悪化するという課題があった。
On the other hand, in the prior art shown in FIG. 7, similarly, the non-uniformity of the solder volume due to the solder dip is large,
It's very difficult to control. in addition,
To prevent the pin from falling out, use a pin insertion part with a diameter larger than the through hole and insert it by press-fitting, and the pin is harder.Therefore, after the pin is inserted into the board, the volume expansion of the board tends to cause the entire board to warp. It was For this reason, the tip length of the pin is varied, which greatly hinders coplanarity. Furthermore, when the board is thin, the pins cannot be fixed in a stable manner, and it is difficult to stand vertically, which further deteriorates coplanarity.

【0007】さらに図6および図7に示す両従来技術の
半導体装置に言えることであるが、外部端子を形成する
ために半田を完全に溶融する熱履歴とフラックス洗浄工
程が必要なために工数が増加しかつ品質に問題を起こし
易かった。外部端子を形成するための溶融半田へのディ
ッピング法は240℃前後の加熱処理を必要とし、さら
にフラックスの使用は避けられないから、処理後はフラ
ックス洗浄をしなければならなかった。また半導体装置
の組立前に外部端子接続を行う場合などは、予め半導体
素子搭載部、及びインナリードをテーピング等により保
護する必要がある為、より工数の増加を余儀なくされ
た。プリント基板を用いた半導体装置は水分の吸湿が多
く、表面実装時のリフロー加熱温度240℃前後に全体
が加熱されると、基板の剥離、樹脂のクラック等を起こ
しやすくなる欠陥を有しており、このために実装前の乾
燥ベークは必要不可欠であった。よってプリント基板を
用いる半導体装置の組立の際の外部端子の取付けにおけ
る半田付けにおいても同様で、半田ディッピング、リフ
ロー前には半導体装置を乾燥ベークしなければならない
為に工数がかかる課題があった。
Further, as can be said for the semiconductor devices of both prior arts shown in FIGS. 6 and 7, the number of steps is reduced because a heat history for completely melting the solder and a flux cleaning step are required to form the external terminals. Increased and prone to quality problems. The dipping method to the molten solder for forming the external terminals requires a heat treatment at about 240 ° C., and since the use of flux is unavoidable, the flux must be washed after the treatment. In addition, when connecting external terminals before assembling a semiconductor device, it is necessary to protect the semiconductor element mounting portion and the inner leads by taping or the like in advance, which necessitates an increase in the number of steps. A semiconductor device using a printed circuit board has a lot of moisture absorption, and has a defect that when the entire surface is heated to a reflow heating temperature of about 240 ° C during surface mounting, peeling of the board and cracking of the resin are likely to occur. For this reason, a dry bake before mounting was essential. Therefore, the same applies to soldering when attaching external terminals when assembling a semiconductor device using a printed circuit board, and the semiconductor device must be dried and baked before solder dipping and reflow, which poses a problem of requiring man-hours.

【0008】したがって本発明の目的は、基板の接続ホ
ール下の半田外部端子を、所定の高さを有して均一に、
信頼性良く、かつ工程を簡素化して形成することができ
る半導体装置およびその製造方法を提供することであ
る。
Therefore, an object of the present invention is to uniformly arrange the solder external terminals under the connection holes of the board with a predetermined height.
It is an object of the present invention to provide a semiconductor device which can be formed with high reliability and a simplified process, and a manufacturing method thereof.

【0009】[0009]

【課題を解決するための手段】本発明の特徴は、半導体
素子を基板の第1の主面上に搭載し、前記基板の第2の
主面から外部端子が突出し、前記基板に配置された導体
配線と前記外部端子とが前記基板に設けられたスルーホ
ールもしくはハーフホールの接続ホール内の接続手段を
通して電気的に接続されている半導体装置において、前
記接続ホール内から連続的に半田棒を前記基板の第2の
主面から突出させて前記外部端子を形成し、前記外部端
子の先端は、半田溶融後の半球状態となっておらずに前
記半田棒を切断した状態となっている半導体装置にあ
る。
A feature of the present invention is that a semiconductor element is mounted on a first main surface of a substrate, and external terminals project from the second main surface of the substrate, and the semiconductor device is arranged on the substrate. In a semiconductor device in which a conductor wire and the external terminal are electrically connected through a connecting means in a through hole or a half hole provided in the substrate, a solder bar is continuously provided from the inside of the connection hole. A semiconductor device in which the external terminal is formed by projecting from the second main surface of the substrate, and the tip of the external terminal is not in a hemispherical state after solder melting but in a state in which the solder rod is cut. It is in.

【0010】本発明の他の特徴は、半導体素子を基板の
第1の主面上に搭載し、前記基板の第2の主面から外部
端子が突出し、前記基板に配置された導体配線と前記外
部端子とが前記基板に設けられたスルーホールもしくは
ハーフホールの接続ホール内の接続手段を通して電気的
に接続されている半導体装置を製造する方法において、
前記接続ホールに半田棒を挿入し、前記半田棒が前記基
板の第2の主面から突出した突出部を前記外部端子とし
た半導体装置の製造方法にある。
Another feature of the present invention is that the semiconductor element is mounted on the first main surface of the substrate, the external terminals are projected from the second main surface of the substrate, and the conductor wiring and the conductor wiring arranged on the substrate are provided. In a method of manufacturing a semiconductor device in which an external terminal is electrically connected through a connecting means in a through hole or a half hole connecting hole provided in the substrate,
In the method of manufacturing a semiconductor device, a solder rod is inserted into the connection hole, and the protruding portion of the solder rod protruding from the second main surface of the substrate is used as the external terminal.

【0011】上記半導体装置あるいは半導体装置の製造
方法において、前記半田棒の半田が前記接続ホール内壁
の導電膜と溶融固着せず機械的に挿入したままの状態で
あることができる。あるいは半田棒を機械的に挿入した
後、少なくとも一部に未溶融部を有するようにして、一
部の半田のみを溶融した状態にすることもできる。ま
た、前記半田棒をたがいに異なる融点を有する2種類以
上の半田から構成し、棒の軸中心方向に配置された半田
の融点を棒外周表面部の半田の融点より高くすることが
できる。あるいは、前記半田棒の軸中心方向に金属また
は合金からなる心材を有することができる。また、前記
半田棒のフラックスを含有した半田を用いることができ
る。
In the above semiconductor device or the method of manufacturing a semiconductor device, the solder of the solder bar may be in a state of being mechanically inserted without being melted and fixed to the conductive film on the inner wall of the connection hole. Alternatively, after the solder rod is mechanically inserted, at least a part of the solder bar may have an unmelted portion so that only a part of the solder is melted. Further, the solder rod is composed of two or more kinds of solder having different melting points, and the melting point of the solder arranged in the axial direction of the rod can be made higher than the melting point of the solder on the outer peripheral surface of the rod. Alternatively, a core material made of metal or alloy can be provided in the axial center direction of the solder rod. Further, solder containing the flux of the solder rod can be used.

【0012】[0012]

【発明の実施の形態】以下、図面を参照して本発明を説
明する。
DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

【0013】図1(A)は本発明の第1の実施の形態の
半導体装置およびその製造方法を示す断面図、図1
(B)は図1(A)の要部を拡大して示す断面図であ
る。
FIG. 1A is a sectional view showing a semiconductor device and a method of manufacturing the same according to the first embodiment of the present invention.
FIG. 1B is a cross-sectional view showing an enlarged main part of FIG.

【0014】ガラスエポキシ基板等の絶縁基板の第1の
主面(表面)31に導電配線6のパターンを形成したプ
リント基板2には、金属膜のスルーホール導電膜8によ
り内壁を構成した複数のスルーホール7が基板の第1の
主面(表面)31から第2の主面(裏面)32に貫通し
て設けられ、この導電膜8が接続手段の少なくとも一部
として導電配線6の所定部分にそれぞれ接続している。
On the printed board 2 in which the pattern of the conductive wiring 6 is formed on the first main surface (front surface) 31 of an insulating substrate such as a glass epoxy substrate, a plurality of inner walls are formed by the through-hole conductive film 8 of a metal film. A through hole 7 is provided so as to penetrate from the first main surface (front surface) 31 of the substrate to the second main surface (back surface) 32, and the conductive film 8 serves as at least a part of the connecting means and a predetermined portion of the conductive wiring 6. Are connected to each.

【0015】プリント基板2の表面上の導電配線6の素
子搭載部に半導体素子1をマウント材3により接着搭載
し、ボンディングワイヤー4により半導体素子の電極と
プリント基板上の導電配線6のそれぞれの部分とを電気
的に接続した後、封止樹脂5により封止される。
The semiconductor element 1 is bonded and mounted on the element mounting portion of the conductive wiring 6 on the surface of the printed circuit board 2 by the mounting material 3, and the electrodes of the semiconductor element and the conductive wiring 6 on the printed circuit board are bonded by the bonding wires 4. After being electrically connected to each other, they are sealed with the sealing resin 5.

【0016】そして、予めワイヤー状に押し出し、また
は噴出法により冷却固化し、所定の長さになるように機
械的に切断した半田棒9をスルーホール導電膜8が内壁
に施してあるスルーホール7内に機械的に圧入して、第
2の主面から所定の長さ突出させる。半田棒のこの突出
した半田突出部16がそのまま外部電極となる。場合に
よってはその後、半田が完全に溶融する温度より低い温
度で熱処理し、一部の半田のみを溶融してスルーホール
導電膜8に融着する状態にしてもよい。いずれの場合も
外部端子10となる半田突出部16の先端は、半田溶融
後の半球状となっておらず、半田棒を切断した状態であ
る。また半田棒はスルーホールに挿入後に、多数の外部
端子間で高さ(突出量)のばらつきがなく所定の長さに
なるように機械的に切断することもできる。
Then, a through-hole 7 having a through-hole conductive film 8 formed on the inner wall of a solder rod 9 which has been extruded in the shape of a wire in advance or cooled and solidified by an ejection method and mechanically cut into a predetermined length. It is mechanically press-fitted into the second main surface so as to protrude from the second main surface by a predetermined length. This protruding solder protrusion 16 of the solder rod serves as an external electrode as it is. Depending on the case, after that, heat treatment may be performed at a temperature lower than the temperature at which the solder is completely melted, and only a part of the solder may be melted and fused to the through-hole conductive film 8. In any case, the tip of the solder protrusion 16 that becomes the external terminal 10 is not in a hemispherical shape after melting the solder, but is in a state in which the solder rod is cut. After the solder rod is inserted into the through hole, it can be mechanically cut into a predetermined length without variation in height (projection amount) among a large number of external terminals.

【0017】半田棒9の半田は共晶半田Sn63−Pb
37が好ましい。また、半田棒9の直径及び導電膜8の
内径で規定されるスルーホール7の直径は0.1〜0.
8mm程度が選択範囲で0.2〜0.4mmが適してお
り、半田突出部16の半田棒の長さ、すなわち基板の裏
面から先端までの長さは0.2〜0.8mm程度が選択
範囲で0.4〜0.6mmが最適である。この半田突出
部16は圧入された半田棒9がそのまま突出したもので
あるからスルーホールの平面形状を反映した平面形状を
有している。すなわちこの実施の形態では円形のスルー
ホールであるから半田の突出部16は円筒形状になって
おり、従来のように半田溶融、半田ディップによる半球
状にはなっていない。
The solder of the solder rod 9 is eutectic solder Sn63-Pb.
37 is preferred. The diameter of the through hole 7 defined by the diameter of the solder bar 9 and the inner diameter of the conductive film 8 is 0.1 to 0.
About 8 mm is suitable in the selected range of 0.2 to 0.4 mm, and the length of the solder rod of the solder protruding portion 16, that is, the length from the back surface of the board to the tip is selected to be about 0.2 to 0.8 mm. The optimum range is 0.4 to 0.6 mm. The solder protrusion 16 has a planar shape that reflects the planar shape of the through hole because the press-fitted solder rod 9 is directly protruded. That is, in this embodiment, since it is a circular through hole, the solder protrusion 16 has a cylindrical shape, and does not have a hemispherical shape due to solder melting and solder dipping as in the conventional case.

【0018】この半田突出部16の半田棒9の長さは実
装時の溶融半田の量と接続バンプ高さから決定される。
さらに半田棒の基板挿入部には加締め効果を持たせるた
めに突起を設けておくと良い。この半田棒は実装時の加
熱リフローで溶融しバンプ接続する。
The length of the solder rod 9 of the solder protrusion 16 is determined by the amount of molten solder and the height of the connection bump during mounting.
Further, it is preferable to provide a protrusion on the board insertion portion of the solder rod in order to have a crimping effect. This solder rod is melted by heat reflow at the time of mounting and bump-connected.

【0019】図2は図1の第1の実施の形態の半導体装
置の実装後の半田接続状態を示す部分拡大断面図であ
る。
FIG. 2 is a partially enlarged sectional view showing a solder connection state after mounting the semiconductor device of the first embodiment shown in FIG.

【0020】半田棒の突出部が実装時の加熱リフローに
より溶融して、実装基板20の表面上に形成されてある
配線膜21上に、半田棒の半田突出部16(図1)すな
わち円筒状の外部端子10(図1)からバンプ状に半田
接続部19を形成して接続する。尚この実装の際には、
実装基板側に半田ペーストを予め印刷して半田量を補給
しても良い。
The protruding portion of the solder rod is melted by heat reflow during mounting, and the solder protruding portion 16 (FIG. 1) of the solder rod, that is, a cylindrical shape is formed on the wiring film 21 formed on the surface of the mounting substrate 20. Solder connection portions 19 are formed in a bump shape from the external terminals 10 (see FIG. 1) and connected. When implementing this,
The amount of solder may be replenished by printing solder paste on the mounting board side in advance.

【0021】図3は本発明の第2の実施の形態の要部を
示す断面図であり、図1(B)に対応している。半導体
装置を構成するプリント基板2にスルーホール導電膜8
を内壁に被着したスルーホール7が設けられており、こ
こに半田棒9が圧入され、外部電極10となる半田突出
部16を有している。この実施の形態の半田棒9は軸中
心方向に心材11を外円周部には外周部半田12を有す
る。心材11には例えばSn10−Pb90の高融点半
田を用い、外周部半田12には低融点半田の例えば共晶
半田Sn63−Pb37を用いる。高融点半田はその融
点が実装時の加熱リフロー温度相当かより高い温度にな
る組成を選択すればよい。また心材に鉄ニッケル42合
金、または銅、リン青銅等の金属、合金を使用すること
もできる。この場合の半田棒は引伸し法により細線化し
た半田棒を用いると良い。応力軽減を考えれば、基板と
半田の膨張率に近い銅系合金が優れる。半田棒は先端を
突出させておき、その長さは実装後のスタンドオフの必
要高さから選択すると良い。この実施の形態では0.5
〜2mm程度が適当であるが特に0.5〜1mmが好ま
しい。また、心材の径は0.1〜0.3mm程度で外円
周部の半田厚は0.05〜0.2mm程度が好ましい。
なお、心材に金属、合金系を使用する場合は必要に応じ
てニッケルメッキ等の緩衝金属を介しても良い。以上の
場合であれば、スタンドオフの高さを所望の値にコント
ロールすることができる上、実装後のリペアも心材が有
るために実装基板から外した後でも外部端子としての機
能を維持され再実装が可能である。突出部の先端の形
状、半田棒の切断時期あるいは必要に応じて外円周部半
田の一部のみを導電膜に溶着することは第1の実施の形
態と同様である。
FIG. 3 is a sectional view showing an essential part of the second embodiment of the present invention, which corresponds to FIG. 1 (B). A through-hole conductive film 8 is formed on a printed circuit board 2 which constitutes a semiconductor device.
Is formed on the inner wall of the through hole 7, and the solder rod 9 is press-fitted into the through hole 7 and has a solder protruding portion 16 serving as an external electrode 10. The solder rod 9 of this embodiment has a core material 11 in the axial center direction and an outer peripheral portion solder 12 in the outer circumferential portion. For the core material 11, for example, Sn10-Pb90 high melting point solder is used, and for the outer peripheral portion solder 12, for example, eutectic solder Sn63-Pb37 of low melting point solder is used. The composition of the high melting point solder may be selected such that the melting point thereof is equivalent to or higher than the heating reflow temperature during mounting. Further, iron-nickel 42 alloy, or metal or alloy such as copper or phosphor bronze can be used for the core material. In this case, it is preferable to use a solder rod thinned by a drawing method as the solder rod. Considering the stress reduction, a copper-based alloy having an expansion coefficient close to that of the substrate and the solder is superior. It is recommended that the tip of the solder rod be made to protrude and the length thereof be selected from the required height of the standoff after mounting. In this embodiment, 0.5
Approximately 2 mm is suitable, but 0.5-1 mm is particularly preferable. Further, it is preferable that the diameter of the core material is about 0.1 to 0.3 mm and the solder thickness of the outer circumferential portion is about 0.05 to 0.2 mm.
When a metal or alloy is used for the core material, a buffer metal such as nickel plating may be interposed if necessary. In the above cases, the height of the standoff can be controlled to a desired value, and since the repair after mounting also has the core material, the function as an external terminal is maintained even after removing it from the mounting board. Can be implemented. Similar to the first embodiment, the shape of the tip of the protruding portion, the cutting timing of the solder rod, or if necessary, only a part of the outer circumferential solder is welded to the conductive film.

【0022】図4は図3の第2の実施の形態の半導体装
置の実装後の半田接続状態を示す部分拡大断面図であ
る。心材11は加熱リフロー時でも溶融しないが突出部
の外円周部半田12は溶融してバンプ状の半田接続部1
9を形成して実装基板20の配線膜21に接続する。こ
の場合も半田ペーストの補給が有ればなお良好な接続が
可能である。
FIG. 4 is a partially enlarged sectional view showing a solder connection state after mounting the semiconductor device of the second embodiment shown in FIG. The core material 11 is not melted during heating reflow, but the solder 12 on the outer circumferential portion of the protruding portion is melted and the bump-shaped solder connection portion 1 is formed.
9 is formed and connected to the wiring film 21 of the mounting substrate 20. Even in this case, if the solder paste is supplied, a good connection can be achieved.

【0023】図5は本発明の第3の実施の形態の要部を
示す断面図であり、図1(B)や図3に対応している。
プリント基板2の内部に内部導電配線22が設けられて
おり、ハーフホール導電膜14を内壁とするハーフホー
ル13が基板2の第2の主面(裏面)32からこの内部
導電配線22に達して設けられており、ここに下から半
田棒9を挿入する。なお、この実施の形態の接続ホール
は、第1の主面31から第2の主面32まで基板2を貫
通したスールーホールではなく、第2の主面32から基
板内部までのものであるからハーフホールという。基板
のハーフホールは基板を積層形成する前に、基板の圧入
部に当たる基板積層部2Aのみにスルーホールを形成
し、残りの基板積層部2Bを張り合わせて一枚の基板に
仕上げることにより設けることができる。ハーフホール
への半田棒の挿入の仕方は先に述べたとおりである。こ
の実施の形態では基板の上部が閉じているため、実装後
の半田、心材の這いあがりを防止することができ、より
スタンドオフ値の精度、コプラナリティの確保に有効で
ある。
FIG. 5 is a sectional view showing an essential part of a third embodiment of the present invention, which corresponds to FIG. 1 (B) and FIG.
The internal conductive wiring 22 is provided inside the printed circuit board 2, and the half hole 13 having the half hole conductive film 14 as an inner wall reaches the internal conductive wiring 22 from the second main surface (back surface) 32 of the substrate 2. It is provided, and the solder rod 9 is inserted therein from below. It should be noted that the connection hole of this embodiment is not a sulu hole penetrating the substrate 2 from the first main surface 31 to the second main surface 32, but from the second main surface 32 to the inside of the substrate. It is called a half hole. The half-holes of the board are provided by forming through holes only in the board stacking section 2A corresponding to the press-fitting section of the board and stacking the remaining board stacking sections 2B to complete one board before stacking the boards. it can. The method of inserting the soldering rod into the half hole is as described above. In this embodiment, since the upper part of the substrate is closed, it is possible to prevent the solder and the core material from crawling up after mounting, and it is more effective to secure the accuracy of the standoff value and the coplanarity.

【0024】特に図示はしないが、上記半田棒の半田に
フラックス入りタイプを選択すれば、実装時のフラック
ス供給が不要になり、工数の低減もしくはより安定な実
装を実現することが可能となる。
Although not shown in the figure, if a flux-filled type is selected for the solder of the solder rod, the flux supply at the time of mounting becomes unnecessary, and the number of steps can be reduced or more stable mounting can be realized.

【0025】なお、本発明の実施の形態ではBGAを例
にして説明したが、リード付き当てタイプのバットリー
ド(Butt Lead)PGタイプにも適用されるこ
とは言うに及ばない。
Although the embodiment of the present invention has been described by taking the BGA as an example, it goes without saying that the present invention is also applicable to a butted lead PG type of a lead type pad.

【0026】[0026]

【発明の効果】以上説明したように本発明は、基板のス
ルーホールやハーフホールの接続ホールに半田棒を挿入
することで外部端子として配列することを可能にできる
ことから多ピンで高密度の実装が可能にしたまま、半導
体装置の外部端子の取付けを非加熱処理で且つ、フラッ
クス洗浄無しで行なうことが出来る。これは半導体装置
の組立工程に於ける工数低減、資材、光熱費等の低減を
もたらすばかりでなく、工程の省略となる加熱処理、洗
浄の廃止が可能でより品質の高い、また信頼性の高い半
導体装置を実現することが可能となる。またプリント基
板は水分の吸湿が多いため加熱リフロー時に水分気化に
よる基板の剥離、樹脂の劣化を招きやすく、必要に応じ
て加熱リフロー前に乾燥ベークまで要求されるから、従
来の外部端子ではその形成前に半導体装置の乾燥ベーク
を必要としていたが、本発明では外部端子形成前のこの
ような乾燥ベークは不必要になる。
As described above, according to the present invention, it is possible to arrange the terminals as the external terminals by inserting the soldering rods into the through holes or the connecting holes of the half holes of the board. It is possible to attach the external terminals of the semiconductor device without heat treatment and without cleaning the flux. This not only reduces the number of man-hours in the assembly process of the semiconductor device, reduces the materials and utility costs, but also enables the elimination of the heat treatment and cleaning, which eliminates the process, and has higher quality and higher reliability. It becomes possible to realize a semiconductor device. Also, since the printed circuit board absorbs a large amount of moisture, it is easy to cause peeling of the substrate due to water vaporization and deterioration of the resin during heating reflow.If necessary, a dry bake is required before heating reflow. Although the dry baking of the semiconductor device was required before, such dry baking before the formation of the external terminals is unnecessary in the present invention.

【0027】そして本発明は半田棒を接続ホールに挿入
したまま外部端子とするものであるから基板からの突出
部の高さを所望の値に設定することができ、各外部端子
間の高さのばらつきを抑制した良好なコプラナリティを
有し、半田のボリュウムの良好な均一性を維持すること
ができる。またボイドを発生させることなくホール内を
充填させ、基板の反りを抑制することもできる。さらに
熱処理等を行なわないで外部端子を形成することができ
るから、接続ホール内の断線を回避しかつ半導体装置の
組立て前の外部端子の形成が容易となる。
Further, according to the present invention, since the solder rod is used as the external terminal while being inserted into the connection hole, the height of the protruding portion from the substrate can be set to a desired value, and the height between the external terminals can be set. It has a good coplanarity in which the dispersion of the solder is suppressed, and the good uniformity of the solder volume can be maintained. Further, it is possible to suppress the warpage of the substrate by filling the inside of the hole without generating voids. Further, since the external terminals can be formed without performing heat treatment or the like, disconnection in the connection holes can be avoided and the external terminals can be easily formed before the semiconductor device is assembled.

【0028】また、半田棒に軸中心に心材を用いれば、
実装後のスタンドオフを所望の大きさに確保でき、実装
歩留まりはもとより、実装後の応力緩和の効果から信頼
性も向上する。さらに半田棒の取付けに熱処理を必要と
しないため、半田棒にフラックスを含有させることが可
能で有り、実装後の酸化防止をし接続信頼性を確保する
ことが可能である。
Further, if the core material is used in the center of the shaft for the solder rod,
The standoff after mounting can be secured in a desired size, and not only the mounting yield but also the reliability is improved due to the effect of stress relaxation after mounting. Further, since heat treatment is not required to attach the solder rod, it is possible to contain flux in the solder rod, and it is possible to prevent oxidation after mounting and ensure connection reliability.

【0029】以上により、従来技術に比べ、組立労間費
を50%〜20%低減しながら、より信頼性の高い半導
体装置を提供することができる。
As described above, it is possible to provide a more reliable semiconductor device while reducing the labor cost for assembly by 50% to 20% as compared with the prior art.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態を示す図であり、
(A)は半導体装置の断面図、(B)は(A)の要部を
拡大して示す断面図である。
FIG. 1 is a diagram showing a first embodiment of the present invention,
7A is a cross-sectional view of a semiconductor device, and FIG. 6B is a cross-sectional view showing an enlarged main part of FIG.

【図2】本発明の第1の実施の形態の半導体装置の実装
状態の要部を示す断面図である。
FIG. 2 is a cross-sectional view showing a main part of a mounted state of the semiconductor device according to the first embodiment of the present invention.

【図3】本発明の第2の実施の形態の半導体装置の要部
を示す断面図である。
FIG. 3 is a sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention.

【図4】本発明の第2の実施の形態の半導体装置の実装
状態の要部を示す断面図である。
FIG. 4 is a sectional view showing a main part of a mounted state of a semiconductor device according to a second embodiment of the present invention.

【図5】本発明の第3の実施の形態の半導体装置の実装
状態の要部を示す断面図である。
FIG. 5 is a sectional view showing a main part of a mounted state of a semiconductor device according to a third embodiment of the present invention.

【図6】従来技術の半導体装置を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional semiconductor device.

【図7】他の従来技術の半導体装置を示す断面図であ
る。
FIG. 7 is a cross-sectional view showing another conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 基板 2A,2B 基板積層部 3 マウント材 4 ボンディングワイヤ 5 封止樹脂 6 導電配線 7 スルーホール 8 スルーホール導電膜 9 半田棒 10 外部端子 11 心材 12 外円周部半田 13 ハーフホール 14 ハーフホール導電膜 15 充電半田 16 半田突出部 17 金属ピン 18 半田溜り 19 半田接続部 20 実装基板 21 配線膜 22 内部導体配線 31 第1の主面(表面) 32 第2の主面(裏面) 1 Semiconductor Element 2 Substrate 2A, 2B Substrate Laminated Section 3 Mounting Material 4 Bonding Wire 5 Sealing Resin 6 Conductive Wiring 7 Through Hole 8 Through Hole Conductive Film 9 Solder Bar 10 External Terminal 11 Core Material 12 Outer Circumferential Solder 13 Half Hole 14 Half-hole conductive film 15 Charged solder 16 Solder protrusion 17 Metal pin 18 Solder pool 19 Solder connection 20 Mounting board 21 Wiring film 22 Internal conductor wiring 31 First main surface (front surface) 32 Second main surface (back surface)

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を基板の第1の主面上に搭載
し、前記基板の第2の主面から外部端子が突出し、前記
基板に配置された導体配線と前記外部端子とが前記基板
に設けられたスルーホールもしくはハーフホールの接続
ホール内の接続手段を通して電気的に接続されている半
導体装置において、前記接続ホール内から連続的に半田
棒を前記基板の第2の主面から突出させて前記外部端子
を形成し、前記外部端子の先端は、半田溶融後の半球状
態となっておらずに前記半田棒を切断した状態となって
いることを特徴とする半導体装置。
1. A semiconductor element is mounted on a first main surface of a substrate, an external terminal projects from a second main surface of the substrate, and the conductor wiring and the external terminal arranged on the substrate are the substrate. In a semiconductor device electrically connected through a connecting means in a through hole or a half hole provided in a semiconductor device, a solder rod is continuously protruded from the second main surface of the substrate from the inside of the connecting hole. The semiconductor device is characterized in that the external terminal is formed by using the external terminal, and the tip of the external terminal is not in a hemispherical state after melting the solder but is in a state in which the solder rod is cut.
【請求項2】 前記半田棒の半田が前記接続ホール内壁
の導電膜と溶融固着せず機械的に挿入されてなるか、ま
たは少なくとも一部に未溶融部を有することを特徴とす
る請求項1記載の半導体装置。
2. The solder of the solder rod is mechanically inserted without being melted and fixed to the conductive film on the inner wall of the connection hole, or at least a part thereof has an unmelted portion. The semiconductor device described.
【請求項3】 前記半田棒はたがいに異なる融点を有す
る2種類以上の半田から構成され、棒の軸中心方向に配
置された半田の融点が棒外周表面部の半田の融点より高
いことを特徴とする請求項1または請求項2記載の半導
体装置。
3. The solder rod is composed of two or more kinds of solder having different melting points, and the melting point of the solder arranged in the axial center direction of the rod is higher than the melting point of the solder on the outer peripheral surface of the rod. The semiconductor device according to claim 1 or 2.
【請求項4】 前記半田棒の軸中心方向に金属または合
金からなる心材を有することを特徴とする請求項1また
は請求項2記載の半導体装置。
4. The semiconductor device according to claim 1, further comprising a core material made of metal or alloy in the axial center direction of the solder rod.
【請求項5】 前記半田棒の半田にフラックスを含有し
ていることを特徴とする請求項1または請求項2記載の
半導体装置。
5. The semiconductor device according to claim 1, wherein the solder of the solder rod contains a flux.
【請求項6】 半導体素子を基板の第1の主面上に搭載
し、前記基板の第2の主面から外部端子が突出し、前記
基板に配置された導体配線と前記外部端子とが前記基板
に設けられたスルーホールもしくはハーフホールの接続
ホール内の接続手段を通して電気的に接続されている半
導体装置を製造する方法において、前記接続ホールに半
田棒を挿入し、前記半田棒が前記基板の第2の主面から
突出した突出部を前記外部端子としたことを特徴とする
半導体装置の製造方法。
6. A semiconductor device is mounted on a first main surface of a substrate, external terminals project from the second main surface of the substrate, and conductor wiring arranged on the substrate and the external terminals are provided on the substrate. In a method of manufacturing a semiconductor device that is electrically connected through a connecting means in a connection hole of a through hole or a half hole provided in, a solder rod is inserted into the connection hole, and the solder rod is the first substrate of the substrate. 2. A method for manufacturing a semiconductor device, characterized in that a protruding portion protruding from the second main surface is used as the external terminal.
【請求項7】 前記半田棒を挿入した後、半田を完全に
溶融する温度より低い温度で熱処理を行ない、少なくと
も一部に未溶融部を有して、前記接続ホール内壁の導電
膜と半田棒の一部とを溶融固着させることを特徴とする
請求項6記載の半導体装置の製造方法。
7. After inserting the solder rod, a heat treatment is performed at a temperature lower than a temperature at which the solder is completely melted, and at least a part has an unmelted portion, and the conductive film on the inner wall of the connection hole and the solder rod. 7. The method for manufacturing a semiconductor device according to claim 6, wherein a part of the semiconductor device is melted and fixed.
【請求項8】 前記半田棒はたがいに異なる融点を有す
る2種類以上の半田から構成され、棒の軸中心方向に配
置された半田の融点が棒外周表面部の半田の融点より高
いことを特徴とする請求項6または請求項7記載の半導
体装置の製造方法。
8. The solder rod is composed of two or more kinds of solder having different melting points, and the melting point of the solder arranged in the axial center direction of the rod is higher than the melting point of the solder on the outer peripheral surface of the rod. The method for manufacturing a semiconductor device according to claim 6 or 7.
【請求項9】 前記半田棒の軸中心方向に金属または合
金からなる心材を有することを特徴とする請求項6また
は請求項7記載の半導体装置の製造方法。
9. The method of manufacturing a semiconductor device according to claim 6, further comprising a core material made of a metal or an alloy in the axial center direction of the solder rod.
【請求項10】 前記半田棒の半田にフラックスを含有
していることを特徴とする請求項6または請求項7記載
の半導体装置の製造方法。
10. The method of manufacturing a semiconductor device according to claim 6, wherein the solder of the solder rod contains a flux.
JP7238022A 1995-09-18 1995-09-18 Semiconductor device and manufacturing method thereof Expired - Lifetime JP2735045B2 (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7238022A JP2735045B2 (en) 1995-09-18 1995-09-18 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0982873A true JPH0982873A (en) 1997-03-28
JP2735045B2 JP2735045B2 (en) 1998-04-02

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0942636A3 (en) * 1998-03-12 2001-03-14 Lucent Technologies Inc. Solder bonding printed circuit board
EP0959648A4 (en) * 1997-01-30 2004-06-23 Ibiden Co Ltd Printed wiring board and manufacturing method therefor
CN109152241A (en) * 2018-09-07 2019-01-04 江门市奔力达电路有限公司 A method of making edges of boards metal half bore

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4489821B2 (en) * 2008-07-02 2010-06-23 新光電気工業株式会社 Semiconductor device and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63207076A (en) * 1987-02-24 1988-08-26 藤好 克聡 Manufacture of terminal
JPS63283147A (en) * 1987-05-15 1988-11-21 Seiko Keiyo Kogyo Kk Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63207076A (en) * 1987-02-24 1988-08-26 藤好 克聡 Manufacture of terminal
JPS63283147A (en) * 1987-05-15 1988-11-21 Seiko Keiyo Kogyo Kk Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0959648A4 (en) * 1997-01-30 2004-06-23 Ibiden Co Ltd Printed wiring board and manufacturing method therefor
US7222776B2 (en) 1997-01-30 2007-05-29 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor
EP0942636A3 (en) * 1998-03-12 2001-03-14 Lucent Technologies Inc. Solder bonding printed circuit board
CN109152241A (en) * 2018-09-07 2019-01-04 江门市奔力达电路有限公司 A method of making edges of boards metal half bore

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