JPH0982757A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0982757A JPH0982757A JP7231171A JP23117195A JPH0982757A JP H0982757 A JPH0982757 A JP H0982757A JP 7231171 A JP7231171 A JP 7231171A JP 23117195 A JP23117195 A JP 23117195A JP H0982757 A JPH0982757 A JP H0982757A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- indium
- bump
- semiconductor chip
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置とその製
造方法、特に、インジウムを主成分としたバンプを使用
し、第１の半導体チップに形成された第１の電極と、第
２の半導体チップまたは基板に形成された第２の電極と
を、電気的に接続させた半導体装置とその製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a first electrode formed on a first semiconductor chip using a bump containing indium as a main component, and a second semiconductor chip. Alternatively, the present invention relates to a semiconductor device in which a second electrode formed over a substrate is electrically connected and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】インジウムを主成分としたバンプを使用
した半導体装置として、例えばハイブリッド型撮像装置
がある。2. Description of the Related Art As a semiconductor device using a bump containing indium as a main component, there is, for example, a hybrid type image pickup device.
【０００３】図２はハイブリッド型撮像素子の主要構成
の説明図であり、撮像装置１は、信号処理回路が形成さ
れた回路素子２に、多数の光−電気変換素子が形成され
た検知素子３を搭載してなる。FIG. 2 is an explanatory view of the main structure of the hybrid type image pickup device. In the image pickup apparatus 1, a sensing device 3 in which a large number of photoelectric conversion elements are formed in a circuit device 2 in which a signal processing circuit is formed. It will be equipped with.
【０００４】検知素子３の下面に形成された多数の光−
電気変換素子の電極と、回路素子２の上面に形成された
多数の電極とは、インジウムを主成分としたパッド４に
よって接続されている。A large number of light beams formed on the lower surface of the sensing element 3
The electrodes of the electric conversion element and the many electrodes formed on the upper surface of the circuit element 2 are connected by the pad 4 containing indium as a main component.
【０００５】一般にパッド４は、リフトオフ法によって
回路素子２または検知素子３の所定部に形成され、回路
素子２と検知素子３はパッド４を挟んだ状態で加圧し、
パッド４の溶融温度に加熱することによって、回路素子
２と検知素子３とを接続するようになる。Generally, the pad 4 is formed on a predetermined portion of the circuit element 2 or the sensing element 3 by the lift-off method, and the circuit element 2 and the sensing element 3 pressurize with the pad 4 sandwiched therebetween.
By heating to the melting temperature of the pad 4, the circuit element 2 and the sensing element 3 are connected.
【０００６】[0006]
【発明が解決しようとする課題】以上説明したように、
インジウムを主成分としたバンプを使用した従来の半導
体装置では、第１の半導体チップに形成された第１の電
極と、第２の半導体チップまたは基板に形成された第２
の電極とは、バンプを介在させた状態で加圧加熱し、対
向する電極間を電気的に接続させる。As described above,
In a conventional semiconductor device using a bump containing indium as a main component, a first electrode formed on a first semiconductor chip and a second electrode formed on a second semiconductor chip or substrate.
The electrodes are heated under pressure with the bumps interposed to electrically connect the opposing electrodes.
【０００７】バンプ接続における従来技術の問題点の説
明図である図３において、回路素子２に形成された第１
の電極５と検知素子３に形成された第２の電極６とを接
続した各バンプ４は、太鼓状に膨らむようになる。な
お、図中において７と８は、電極５または６との間に形
成された絶縁層（パッシベーション）である。In FIG. 3, which is an explanatory view of the problems of the prior art in bump connection, the first element formed on the circuit element 2 is shown.
Each bump 4 connecting the second electrode 5 formed on the detection element 3 with the second electrode 5 swells like a drum. In the figure, 7 and 8 are insulating layers (passivation) formed between the electrodes 5 and 6.
【０００８】一方、半導体装置は高性能・小型化が進ん
でおり、例えばハイブリッド型撮像装置において画素の
大きさおよびその整列ピッチが小さくなり、従来40μm
程度であったピッチを20μm 程度にしたいという要望が
ある。On the other hand, semiconductor devices have been advanced in performance and miniaturization. For example, in a hybrid type image pickup device, the size of pixels and the arrangement pitch thereof have become small, and the conventional 40 μm.
There is a desire to reduce the pitch from about 20 μm.
【０００９】かかる高性能・小型化要望に対し従来技術
では追従が困難、即ち、例えば前記ハイブリッド型撮像
装置において、従来技術で形成されたパッド４を有する
回路素子２に、従来技術によって位置合わせした検知素
子３を接続させたとき、図３に示す如く、パッド４の形
成位置のずれ（位置のばらつき）によって太鼓状に膨ら
んで隣接バンプ４が接触することがある。It is difficult for the conventional technique to follow such a demand for high performance and miniaturization, that is, for example, in the hybrid type image pickup device, the circuit element 2 having the pad 4 formed by the conventional technique is aligned by the conventional technique. When the sensing element 3 is connected, as shown in FIG. 3, the adjacent bump 4 may bulge like a drum due to a shift (dispersion in position) of the formation position of the pad 4.
【００１０】さらに、回路素子２と検知素子３との位置
合わせ精度が悪かったり、電極６の形成位置がずれてい
ると、図３の中央部に示すバンプ４′の如く、所定の電
極６からはみ出して形成されるようになる。このように
電極６から絶縁層８上にはみ出した形成されバンプ４′
は、そのはみ出し部の密着力が弱いため、装置１の使用
中に絶縁層８上で拡がり、隣接する所定外の電極６また
はその電極６に接続したバンプ４と接触することがあっ
た。Further, if the alignment accuracy between the circuit element 2 and the detection element 3 is poor or the position where the electrode 6 is formed is deviated, the bump 6'shown in the central portion of FIG. It will be formed to protrude. In this way, the bumps 4'formed on the insulating layer 8 from the electrodes 6 are formed.
Since the protruding portion has a weak adhesive force, it may spread on the insulating layer 8 during use of the device 1 and come into contact with the adjacent non-predetermined electrode 6 or the bump 4 connected to the electrode 6.
【００１１】前記問題点を解決する簡易手段として、例
えばバンプ４接続時の加圧力を小さくしてバンプ４の太
鼓状の膨らみを少なくすると、電極６とバンプ４との接
合力が不足し、電気的安定性が損なわれるようになる。As a simple means for solving the above-mentioned problems, for example, when the pressure applied when connecting the bumps 4 is reduced to reduce the drum-shaped bulge of the bumps 4, the bonding force between the electrodes 6 and the bumps 4 becomes insufficient, resulting in an electrical failure. Stability is impaired.
【００１２】[0012]
【課題を解決するための手段】インジウムバンプが太鼓
状になって発生する前記課題を解決する本発明は、第１
の半導体チップに形成された第１の電極と、第２の半導
体チップまたは基板に形成された第２の電極とが、イン
ジウムを主成分としたバンプで接続された半導体装置に
おいて、該第１の電極と第２の電極とが、該第１および
第２の電極の表面にインジウムの融点より低い温度でイ
ンジウムとの共晶体を作る金属で形成された第１および
第２の金属層を介在せしめ、加熱されたことで該第１お
よび第２の金属層との接合部で共晶体が生成された該バ
ンプで接続されてなること、を特徴とした半導体装置
と、第１の半導体チップに形成された第１の電極の表面
に、インジウムの融点より低い温度でインジウムとの共
晶体を作る第１の金属層を形成し、該第１の半導体チッ
プを搭載する第２の半導体チップまたは基板に形成され
た第２の電極の表面に、インジウムの融点より低い温度
でインジウムとの共晶体を作る第２の金属層を形成し、
該第１および第２の金属層の一方の上に、インジウムを
主成分としたバンプを形成し、該バンプと該第１および
第２の金属層の他方とを当接せしめ、該第１および第２
の金属層と該バンプとが共晶体を作る温度に加熱して該
第１の電極と第２の電極とを電気的に接続させること、
を特徴とした半導体装置の製造方法である。SUMMARY OF THE INVENTION The present invention for solving the above-described problem that an indium bump is formed in a drum shape is firstly provided.
In the semiconductor device in which the first electrode formed on the semiconductor chip and the second electrode formed on the second semiconductor chip or the substrate are connected by a bump containing indium as a main component. The electrodes and the second electrodes interpose first and second metal layers formed on the surfaces of the first and second electrodes with a metal that forms a eutectic with indium at a temperature lower than the melting point of indium. A first semiconductor chip and a semiconductor device characterized in that the first semiconductor chip and the first and second metal layers are connected to each other by the bumps in which a eutectic crystal is formed at a junction with the first and second metal layers. A first metal layer for forming a eutectic with indium at a temperature lower than the melting point of indium is formed on the surface of the formed first electrode, and a second semiconductor chip or substrate on which the first semiconductor chip is mounted is formed. Surface of the formed second electrode To form a second metal layer to make eutectic of indium at a temperature below the melting point of indium,
A bump containing indium as a main component is formed on one of the first and second metal layers, and the bump and the other of the first and second metal layers are brought into contact with each other. Second
Heating to a temperature at which the metal layer and the bump form a eutectic to electrically connect the first electrode and the second electrode,
Is a method of manufacturing a semiconductor device.
【００１３】このような半導体装置とその製造方法は、
インジウムパッドを、インジウムの融点より低い温度で
インジウムと共晶体を作る金属で挟むため、第１の半導
体チップと第２の半導体チップまたは基板との接続に際
し、従来技術で必要した加圧力が不要、即ち、パッドを
その溶融温度程度に加熱すると、加圧しなくても前記第
１および第２の金属層とパッドとの間に共晶体が生成さ
れ、バンプを太鼓状に変形させることなく前記共晶体に
よって、確実な電気的接続が行なわれるようになる。Such a semiconductor device and its manufacturing method are
Since the indium pad is sandwiched by the metal that forms a eutectic with indium at a temperature lower than the melting point of indium, the pressure required by the conventional technique is not required when connecting the first semiconductor chip and the second semiconductor chip or the substrate, That is, when the pad is heated to about its melting temperature, a eutectic crystal is generated between the first and second metal layers and the pad without applying pressure, and the eutectic crystal is formed without deforming the bump into a drum shape. As a result, a reliable electrical connection is made.
【００１４】[0014]
【発明の実施の形態】図１は本発明をハイブリッド型撮
像装置に適用した実施例の説明図である。図２のハイブ
リッド型撮像素子に本発明を適用した実施例である図１
において、(a) は回路素子２に対する検知素子３の位置
決めの説明図、(b) はバンプ４を形成した回路素子２に
形成されたバンプ４に検知素子３を当接させた状態の説
明図、(c) は加熱されたバンプ４が回路素子２と検知素
子３に接合した状態の説明図である。FIG. 1 is an explanatory diagram of an embodiment in which the present invention is applied to a hybrid type image pickup device. 1 is an embodiment in which the present invention is applied to the hybrid type image pickup device of FIG.
2A is an explanatory view of positioning of the detection element 3 with respect to the circuit element 2, and FIG. 6B is an explanatory view of a state in which the detection element 3 is brought into contact with the bump 4 formed on the circuit element 2 on which the bump 4 is formed. , (C) are explanatory views of a state in which the heated bump 4 is bonded to the circuit element 2 and the detection element 3.
【００１５】図１において、回路素子（第２の半導体チ
ップまたは基板）２の上面には、所定の開口部を有する
絶縁層（パッシベーション）７を形成したのち、該開口
部を埋める電極51を、インジウムの融点より低い温度で
インジウムと共晶体を作る金属、例えば金・錫・タリウ
ム・パラジウム等にてパターン形成したのち、電極51の
上にインジウムを主成分としたバンプ４をパターン形成
し、検知素子（第１の半導体チップ）３には、所定の開
口部を有する絶縁層（パッシベーション）８を形成した
のち、該開口部を埋める電極61を、インジウムの融点よ
り低い温度でインジウムと共晶体を作る金属、例えば金
・錫・タリウム・パラジウム等にてパターン形成する。In FIG. 1, an insulating layer (passivation) 7 having a predetermined opening is formed on the upper surface of a circuit element (second semiconductor chip or substrate) 2 and then an electrode 51 filling the opening is formed. After patterning with a metal that forms a eutectic with indium at a temperature lower than the melting point of indium, for example, gold, tin, thallium, palladium, etc., the bumps 4 containing indium as a main component are patterned on the electrode 51 to detect. After forming an insulating layer (passivation) 8 having a predetermined opening in the element (first semiconductor chip) 3, an electrode 61 filling the opening is formed of eutectic with indium at a temperature lower than the melting point of indium. A pattern is formed with a metal to be made, for example, gold, tin, thallium, palladium, or the like.
【００１６】絶縁層７と８は、溶融したバンプに対する
濡れ性のないことが望ましい、そこで、本実施例では従
来と同じ二酸化シリコン(SiO2)にて形成し、その厚さも
従来のものと同じく5000Åとし、電極51と61の厚さも従
来の電極５および６と同じく１μm 程度とした。It is desirable that the insulating layers 7 and 8 have no wettability with respect to the melted bumps. Therefore, in this embodiment, the insulating layers 7 and 8 are formed of the same silicon dioxide (SiO 2 ) as the conventional one, and the thickness thereof is also the same as the conventional one. The thickness of the electrodes 51 and 61 is about 1 μm, which is the same as the conventional electrodes 5 and 6.
【００１７】そして、図１(a) に示す如く、所定の電極
51と61が上下方向に対向するように、回路素子２と検知
素子３とを位置決めしたのち、図１(b) に示す如く、電
極51の下面をバンプ４の上面に当接させる。その当接時
において、バンプ４および電極51の形成位置のばらつき
および回路素子２と検知素子３位置合わせ誤差によっ
て、電極51とバンプ４とが横方向に多少食い違うように
なるものもできる。Then, as shown in FIG. 1 (a), a predetermined electrode
After positioning the circuit element 2 and the sensing element 3 so that 51 and 61 face each other in the vertical direction, the lower surface of the electrode 51 is brought into contact with the upper surface of the bump 4 as shown in FIG. At the time of contact, the electrodes 51 and the bumps 4 may be slightly different from each other in the lateral direction due to variations in the formation positions of the bumps 4 and the electrodes 51 and alignment errors of the circuit element 2 and the sensing element 3.
【００１８】次いで、前記当接を維持した状態で、バン
プ４と電極51, 61が共晶体を生成する温度、例えば約17
0 ℃に加熱すると、バンプ４と電極51および61の当接部
には、バンプ４の主部材であるインジウムと電極51, 61
の形成部材との共晶体が生成され、溶融されたバンプ４
は電極51と61を電気的に接続させる。Then, with the contact maintained, the temperature at which the bump 4 and the electrodes 51, 61 form a eutectic, for example, about 17
When heated to 0 ° C., the indium, which is the main member of the bump 4, and the electrodes 51 and 61 contact the bump 4 and the electrodes 51 and 61.
A eutectic with the forming member of the
Electrically connects electrodes 51 and 61.
【００１９】その際、電極51をバンプ４に押圧させない
ため、バンプ４は太鼓状に膨らむことなく、かつ、電極
51とバンプ４との前記食い違いがあっても、溶融バンプ
４は共晶体生成時の表面張力によって、濡れ性のよい電
極51の表面に引かれる如くなり、絶縁層８の上にはみ出
すことがない。At this time, since the electrode 51 is not pressed against the bump 4, the bump 4 does not bulge like a drum and the electrode 4 does not swell.
Even if there is the above-mentioned discrepancy between the bumps 51 and the bumps 4, the molten bumps 4 are attracted to the surface of the electrode 51 having good wettability by the surface tension when the eutectic is formed, and do not protrude onto the insulating layer 8. .
【００２０】なお、前記実施例ではインジウムの融点よ
り低い温度でインジウムと共晶体を作る金属にて電極51
と61を形成している。しかし、かかるインジウム共晶体
生成金属にてなる金属層を従来の電極５と６の上に形成
するまたは、バンプ４を従来の電極６の上に形成し電極
51をインジウム共晶体生成金属で形成してもよいこと
は、本発明の前記実施例から明白である。In the above embodiment, the electrode 51 is made of a metal that forms a eutectic with indium at a temperature lower than the melting point of indium.
And form 61. However, a metal layer made of such an indium eutectic-forming metal is formed on the conventional electrodes 5 and 6, or the bump 4 is formed on the conventional electrode 6 and the electrode is formed.
It is clear from the above embodiments of the present invention that 51 may be formed of an indium eutectic forming metal.
【００２１】[0021]
【発明の効果】以上説明したように本発明によれば、電
極間接続後のバンプが太鼓状にならず、従って隣のバン
プに接触し難くなると共に、所定電極からはみ出して形
成されないようになる。そのため、接続すべき電極およ
びバンプに従来と同程度のばらつきがあっても、電気的
接続の信頼性が確保される。As described above, according to the present invention, the bumps after connecting the electrodes do not have a drum shape, and thus it is difficult to contact the adjacent bumps, and the bumps are not formed so as to protrude from the predetermined electrode. . Therefore, even if the electrodes and bumps to be connected have the same degree of variation as in the conventional case, the reliability of electrical connection is ensured.
【図１】 本発明をハイブリッド型撮像装置に適用した
実施例の説明図FIG. 1 is an explanatory diagram of an embodiment in which the present invention is applied to a hybrid type image pickup device.
【図２】 ハイブリッド型撮像素子の主要構成の説明図FIG. 2 is an explanatory diagram of a main configuration of a hybrid image sensor.
【図３】 インジウムバンプを使用した従来の接続の問
題点の説明図FIG. 3 is an explanatory diagram of problems of conventional connection using indium bumps.
２ 回路素子（第１の半導体チップ） ３ 検知素子（第２の半導体チップまたは基板） ４ インジウムバンプ 51 電極 (第１の電極） 61 電極 (第２の電極） 2 circuit element (first semiconductor chip) 3 sensing element (second semiconductor chip or substrate) 4 indium bump 51 electrode (first electrode) 61 electrode (second electrode)
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/146 Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 27/146
Claims (4)
し、第１の半導体チップに形成された第１の電極と、第
２の半導体チップまたは基板に形成された第２の電極と
が接続された半導体装置において、 該第１の電極と第２の電極とが、該第１および第２の電
極の表面にインジウムの融点より低い温度でインジウム
との共晶体を作る金属で形成された第１および第２の金
属層を介在せしめ、該接続のための加熱によって該第１
および第２の金属層との接合部に生成された共晶体によ
り、該第１および第２の電極とバンプとが接続されてな
ること、 を特徴とする半導体装置。1. A first electrode formed on a first semiconductor chip and a second electrode formed on a second semiconductor chip or a substrate are connected by using a bump containing indium as a main component. In the semiconductor device, the first electrode and the second electrode are formed of a metal that forms a eutectic with indium at a temperature lower than the melting point of indium on the surfaces of the first and second electrodes. And a second metal layer interposed between the first metal layer and the first metal layer by heating for the connection.
And a bump connected to the first and second electrodes by a eutectic crystal formed at a joint with the second metal layer.
し、第１の半導体チップに形成された第１の電極と、第
２の半導体チップまたは基板に形成された第２の電極と
が接続された半導体装置において、 該第１の電極と第２の電極とが、インジウムの融点より
低い温度でインジウムとの共晶体を作る金属で形成され
てなり、 該第１および第２の電極と該バンプとの接合部に、該接
続のための加熱によって生成された共晶体により、該第
１および第２の電極とバンプとが接続されてなること、 を特徴とする半導体装置。2. A first electrode formed on a first semiconductor chip and a second electrode formed on a second semiconductor chip or a substrate are connected by using a bump containing indium as a main component. In the semiconductor device, the first electrode and the second electrode are formed of a metal that forms a eutectic with indium at a temperature lower than the melting point of indium, the first and second electrodes and the bump. The semiconductor device, wherein the first and second electrodes and the bump are connected to a joint portion with the eutectic body generated by heating for the connection.
電極の表面に、インジウムの融点より低い温度でインジ
ウムとの共晶体を作る金属にて第１の金属層を形成し、 該第１の半導体チップを搭載する第２の半導体チップま
たは基板に形成された第２の電極の表面に、該金属にて
なる第２の金属層を形成し、 該第１および第２の金属層の一方の上に、インジウムを
主成分としたバンプを形成し、 対向するように配設された該バンプと該第１および第２
の金属層の他方とを当接せしめ、 該第１および第２の金属層と該バンプとが共晶体を作る
温度に加熱して該第１の電極と第２の電極とを電気的に
接続させること、 を特徴とする半導体装置の製造方法。3. A first metal layer is formed on the surface of the first electrode formed on the first semiconductor chip, using a metal that forms a eutectic with indium at a temperature lower than the melting point of indium. A second metal layer made of the metal is formed on the surface of the second electrode formed on the second semiconductor chip or the substrate on which the first semiconductor chip is mounted, and the second metal layer of the first and second metal layers is formed. A bump containing indium as a main component is formed on one side, and the bump and the first and second bumps arranged so as to face each other.
The other metal layer is brought into contact with the other metal layer and heated to a temperature at which the first and second metal layers and the bump form a eutectic, thereby electrically connecting the first electrode and the second electrode. A method of manufacturing a semiconductor device, comprising:
電極と、該第１の半導体チップを搭載する第２の半導体
チップまたは基板に形成された第２の電極とを、インジ
ウムの融点より低い温度でインジウムとの共晶体を作る
金属にて形成し、 対向するように配設された該第１および第２の電極の一
方の上に、インジウムを主成分としたバンプを形成し、 該バンプを該第１および第２の電極の他方に当接せし
め、 該金属と該バンプとが共晶体を作る温度に加熱して該第
１の電極と第２の電極とを電気的に接続させること、 を特徴とする半導体装置の製造方法。4. A first electrode formed on a first semiconductor chip and a second electrode formed on a second semiconductor chip or a substrate on which the first semiconductor chip is mounted are provided with a melting point of indium. Formed of a metal that forms a eutectic with indium at a lower temperature, and a bump containing indium as a main component is formed on one of the first and second electrodes arranged to face each other, The bump is brought into contact with the other of the first and second electrodes and heated to a temperature at which the metal and the bump form a eutectic to electrically connect the first electrode and the second electrode. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7231171A JPH0982757A (en) | 1995-09-08 | 1995-09-08 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7231171A JPH0982757A (en) | 1995-09-08 | 1995-09-08 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0982757A true JPH0982757A (en) | 1997-03-28 |
Family
ID=16919435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7231171A Withdrawn JPH0982757A (en) | 1995-09-08 | 1995-09-08 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0982757A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001073843A1 (en) * | 2000-03-29 | 2001-10-04 | Rohm Co., Ltd. | Semiconductor device |
| JP2011009489A (en) * | 2009-06-26 | 2011-01-13 | Sony Corp | Method for manufacturing semiconductor device, semiconductor device, and solid-state image pickup device |
| US9704915B2 (en) | 2010-07-09 | 2017-07-11 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device |
-
1995
- 1995-09-08 JP JP7231171A patent/JPH0982757A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001073843A1 (en) * | 2000-03-29 | 2001-10-04 | Rohm Co., Ltd. | Semiconductor device |
| US6815829B2 (en) | 2000-03-29 | 2004-11-09 | Rohm Co., Ltd. | Semiconductor device with compact package |
| JP2011009489A (en) * | 2009-06-26 | 2011-01-13 | Sony Corp | Method for manufacturing semiconductor device, semiconductor device, and solid-state image pickup device |
| US9704915B2 (en) | 2010-07-09 | 2017-07-11 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device |
| US10263034B2 (en) | 2010-07-09 | 2019-04-16 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device |
| US10651231B2 (en) | 2010-07-09 | 2020-05-12 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device |
| US11545519B2 (en) | 2010-07-09 | 2023-01-03 | Canon Kabushiki Kaisha | Member for solid-state image pickup device and method for manufacturing solid-state image pickup device |
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