JP3395926B2 - Electrode device - Google Patents

Electrode device

Info

Publication number
JP3395926B2
JP3395926B2 JP34051794A JP34051794A JP3395926B2 JP 3395926 B2 JP3395926 B2 JP 3395926B2 JP 34051794 A JP34051794 A JP 34051794A JP 34051794 A JP34051794 A JP 34051794A JP 3395926 B2 JP3395926 B2 JP 3395926B2
Authority
JP
Japan
Prior art keywords
organic insulating
substrate
insulating film
electrode
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP34051794A
Other languages
Japanese (ja)
Other versions
JPH08186152A (en
Inventor
実 石川
淳子 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP34051794A priority Critical patent/JP3395926B2/en
Publication of JPH08186152A publication Critical patent/JPH08186152A/en
Application granted granted Critical
Publication of JP3395926B2 publication Critical patent/JP3395926B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To improve the reliability of the connection between a substrate and a surface mounting type electronic part by electrically connecting the bump of the surface mounting type electronic part to the conducting layer of the uppermost layer, which is exposed through the opening of an organic insulating film. CONSTITUTION: A plurality of conducting layers 24 and 25 are formed within organic insulating films 23 and 27 forming a substrate 20 so that the conducting layers are sequentially aligned at a distance in the direction of the thickness of the organic insulating films 23 and 27. An opening 27A is formed in the insulating film 27 among the organic insulating films 23 and 27 so that a part of the conducting layer 24 is exposed at a part, where the insulating film faces the conducting layer 24 at the uppermost layer. Furthermore, the bump of the surface mounting type electronic part is electrically connected to the conducting layer 24 at the uppermost layer, which is exposed through the opening 27A. Thus, the reliability of the connection between the substrate and the surface mounting type electronic part can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【目次】以下の順序で本発明を説明する。 産業上の利用分野 従来の技術(図6〜図9) 発明が解決しようとする課題(図6〜図9) 課題を解決するための手段(図1〜図5) 作用(図1〜図5) 実施例(図1〜図5) 発明の効果[Table of Contents] The present invention will be described in the following order. Industrial applications Conventional technology (Figs. 6 to 9) Problems to be Solved by the Invention (FIGS. 6 to 9) Means for Solving the Problems (FIGS. 1 to 5) Action (Figs. 1-5) Example (FIGS. 1 to 5) The invention's effect

【0002】[0002]

【産業上の利用分野】本発明は電極装置に関し、例えば
フリツプチツプを熱圧着するようにして接合する基板の
電極に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode device, and is suitable for application to, for example, an electrode of a substrate to which a flip chip is joined by thermocompression bonding.

【0003】[0003]

【従来の技術】従来、フリツプチツプを基板に実装する
実装方法の1つとして、フリツプチツプの各パツド上に
それぞれ金属でなるバンプを形成し、これら各バンプを
配線基板の対応する電極上に熱圧着して電気的に接続す
るようにして行う方法(以下、これを熱圧着実装方法と
呼ぶ)がある。
2. Description of the Related Art Conventionally, as one mounting method for mounting a flip chip on a substrate, bumps made of metal are formed on each pad of the flip chip, and these bumps are thermocompression bonded onto corresponding electrodes on a wiring board. There is a method (hereinafter referred to as a thermocompression bonding mounting method) in which the electrical connection is made.

【0004】この場合フリツプチツプの各パツド上にバ
ンプを形成する方法としては、金属でなるワイヤの先端
を溶融して作つたボール状の塊を超音波圧着した後これ
を残りのワイヤから引きちぎるようにしてバンプ(スタ
ツドバンプ)を形成する方法を用いることがある。
In this case, as a method for forming bumps on each pad of the flip chip, a ball-shaped mass made by melting the tip of a wire made of metal is ultrasonically pressure-bonded and then torn off from the rest of the wire. A method of forming bumps (studded bumps) may be used.

【0005】[0005]

【発明が解決しようとする課題】ところで図6、図7
(A)及び(B)に示すように、一般的に基板1はシリ
コン基板等のマザーボード2上にポリイミド等の有機絶
縁材でなる有機絶縁膜層3を形成すると共に、当該有機
絶縁膜層3上に銅等の導電材で電極4や他の配線パター
ンを形成した後、有機絶縁膜層3上面に電極4や配線パ
ターンを避けて有機絶縁材で薄く(例えば1〔μm 〕程
度)コーテイングする(有機絶縁膜層5を形成する)こ
とにより形成されている。
Problems to be Solved by the Invention FIGS. 6 and 7
As shown in (A) and (B), in general, the substrate 1 has an organic insulating film layer 3 formed of an organic insulating material such as polyimide on a mother board 2 such as a silicon substrate, and the organic insulating film layer 3 is also formed. After forming the electrodes 4 and other wiring patterns with a conductive material such as copper, a thin organic insulating material (for example, about 1 [μm]) is coated on the upper surface of the organic insulating film layer 3 while avoiding the electrodes 4 and the wiring patterns. (The organic insulating film layer 5 is formed).

【0006】この場合有機絶縁材は、弾性が大きいため
に圧力によつて撓み易く、従つて上述のような電極構造
をもつ従来の基板1に対してフリツプチツプを上述の熱
圧着実装方法を用いて実装しようとすると、図8(A)
に示すように、当該フリツプチツプ10を各バンプ11
が基板1の対応する電極2と接触するように基板1上に
位置決めボンデイングした後、図8(B)のように当該
フリツプチツプ10を基板1に押しつけたときに、電極
4下層の有機絶縁膜層2が電極4を介して受ける圧力に
よつて大きく撓み、この結果図8(C)のように電極4
を形成する導電体が断裂することがあつた。
In this case, since the organic insulating material has a large elasticity, it is easily bent by pressure, and thus the flip chip is mounted on the conventional substrate 1 having the above-mentioned electrode structure by using the above thermocompression bonding method. If you try to implement it, you will see Fig. 8 (A).
As shown in FIG.
When the flip chip 10 is pressed against the substrate 1 as shown in FIG. 8B after positioning and bonding the substrate 1 so as to contact the corresponding electrode 2 of the substrate 1, the organic insulating film layer below the electrode 4 is formed. 2 is largely bent by the pressure received through the electrode 4, and as a result, the electrode 4 is deformed as shown in FIG.
The electrical conductor forming the rupture may break.

【0007】また一般的にスタツドパンプは、上述のよ
うに、フリツプチツプ10のパツド上に超音波圧着され
たワイアの先端部を引きちぎることにより形成されてお
り、このためワイヤの先端部を引きちぎる際に、図9
(A)に示すように、スタツドバンプ12の先端部にピ
ン状の突起12Aが形成されることがある。
In general, the stud pump is formed by tearing off the tip of the wire ultrasonically pressure-bonded onto the pad of the flip chip 10 as described above. Therefore, when the tip of the wire is torn off, it is formed. , Fig. 9
As shown in (A), a pin-shaped projection 12A may be formed at the tip of the stud bump 12.

【0008】このような場合、このスタツドバンプ12
を図9(B)のように基板1の対応する電極4に押しつ
けると、スタツドバンプ12の突起12Aによつて図9
(C)のように当該電極4に断裂が生じ、この結果基板
1の電極4とフリツプチツプ10のスタツドバンプ12
との間で接触不良が生じることがあつた。従つて従来の
基板1では、フリツプチツプ10を熱圧着実装方法を用
いて実装する場合に電極4とフリツプチツプ10のバン
プ11、12との間に接触不良が生じ易く、フリツプチ
ツプ10の接続の信頼性が低い問題があつた。
In such a case, this stud bump 12
9 is pressed against the corresponding electrode 4 of the substrate 1 as shown in FIG. 9B, the protrusion 12A of the stud bump 12 causes the protrusion of FIG.
As shown in (C), the electrode 4 is fractured, and as a result, the electrode 4 of the substrate 1 and the stud bump 12 of the flip chip 10 are broken.
Contact failure may occur between the and. Therefore, in the conventional substrate 1, when the flip chip 10 is mounted by using the thermocompression bonding method, contact failure is likely to occur between the electrode 4 and the bumps 11 and 12 of the flip chip 10, and the reliability of the connection of the flip chip 10 is improved. There was a low problem.

【0009】本発明は以上の点を考慮してなされたもの
で、基板及び表面実装型電子部品間の接続の信頼性を向
上させ得る電極装置を提案しようとするものである。
The present invention has been made in view of the above points, and an object thereof is to propose an electrode device which can improve the reliability of connection between a substrate and a surface-mounted electronic component.

【0010】かかる課題を解決するため本発明において
は、表面実装型電子部品(10)の対応するパツド上に
形成されたバンプ(11、12)を、圧着するようにし
て電気的に接続する基板(20)の電極(21)を形成
する電極装置において、基板(20)を形成する有機絶
縁材でなる有機絶縁膜(23、27)内部に、有機絶縁
膜(23、27)の厚み方向に順次距離を隔てて並ぶよ
うに形成された複数の導電層(24、25)と、各導電
層(24、25)をそれぞれ電気的に接続する接続手段
(26)と、有機絶縁膜(23、27)のうち、最上層
の導電層(24)と対向する部分に当該導電層(24)
の一部分が露出するように形成された開口(27A)と
を有し、有機絶縁膜(23)の開口(27A)を介して
露出する最上層の導電層(24)に表面実装型電子部品
(10)のバンプ(11、12)を電気的に接続するよ
うにした。
In order to solve such a problem, according to the present invention, a substrate for electrically connecting bumps (11, 12) formed on corresponding pads of a surface mount type electronic component (10) by pressure bonding. In the electrode device for forming the electrode (21) of (20), inside the organic insulating film (23, 27) made of an organic insulating material for forming the substrate (20), in the thickness direction of the organic insulating film (23, 27). A plurality of conductive layers (24, 25) formed so as to be sequentially spaced apart from each other, connection means (26) for electrically connecting the conductive layers (24, 25), and an organic insulating film (23, 27), the portion of the conductive layer (24) facing the uppermost conductive layer (24).
And an opening (27A) formed so that a part of the surface of the organic insulating film (23A) is exposed, and the uppermost conductive layer (24) exposed through the opening (27A) of the organic insulating film (23) has a surface-mounted electronic component ( The bumps (11, 12) of 10) were electrically connected.

【0011】また本発明においては、表面実装型電子部
品(10)は、フリツプチツプでなるようにした。
Further, in the present invention, the surface mount type electronic component (10) is made of flip chip.

【0012】さらに本発明においては、接続手段(2
6)は、有機絶縁膜(23、27)内部に形成されたバ
イアホールでなるようにした。
Further, in the present invention, the connecting means (2
6) is a via hole formed inside the organic insulating film (23, 27).

【0013】[0013]

【0014】[0014]

【0015】[0015]

【0016】[0016]

【作用】第1の発明では、基板(20)を形成する有機
絶縁材でなる有機絶縁膜(23、27)内部に、有機絶
縁膜(23、27)の厚み方向に順次距離を隔てて並ぶ
ように複数の導電層(24、25)を形成し、各導電層
(24、25)をそれぞれ電気的に接続すると共に、有
機絶縁膜(23、27)のうち、最上層の導電層(2
4)と対向する部分に当該導電層(24)の一部分が露
出するように形成された開口(27A)を設け、有機絶
縁膜(23)の開口(27A)を介して露出する最上層
の導電層(24)に表面実装型電子部品(10)のバン
プ(11、12)を電気的に接続するようにしたことに
より、表面実装型電子部品(10)のバンプ(11、1
2)を基板(20)の最上層の導電層(24)に熱圧着
する際に当該基板(20)を構成する有機絶縁膜(2
3)に発生する撓みを軽減して最上層の導電層(24)
の断裂を防止し得ると共に、この際当該バンプ(12)
に生じているピン状突起(12A)により最上層の導電
層(24)が断裂した場合においても下層の導電層(2
5)によつて基板(20)の導電層(24、25)と、
フリツプチツプ(10)のバンプ(11、12)との間
の導電を確保することができ、かくして基板及び表面実
装型電子部品間の接続の信頼性を向上させ得る電極装置
を実現できる。
In the first aspect of the invention, the organic insulating films (23, 27) made of the organic insulating material forming the substrate (20) are arranged inside the organic insulating film (23, 27) at a distance in the thickness direction of the organic insulating film (23, 27). Thus, the plurality of conductive layers (24, 25) are formed, and the respective conductive layers (24, 25) are electrically connected to each other, and the uppermost conductive layer (2 of the organic insulating films (23, 27) is formed.
4) An opening (27A) is formed in a portion facing the conductive layer (24) so as to expose a part of the conductive layer (24), and conductivity of the uppermost layer exposed through the opening (27A) of the organic insulating film (23). By electrically connecting the bumps (11, 12) of the surface-mounted electronic component (10) to the layer (24), the bumps (11, 1) of the surface-mounted electronic component (10) are connected.
The organic insulating film (2) that constitutes the substrate (20) when thermocompression-bonding 2) to the uppermost conductive layer (24) of the substrate (20).
The uppermost conductive layer (24) by reducing the bending generated in 3)
Of the bump (12) at the same time while preventing the rupture of
Even when the uppermost conductive layer (24) is ruptured by the pin-shaped projections (12A) generated on the lower conductive layer (2A), the lower conductive layer (2
5) by means of the conductive layers (24, 25) of the substrate (20),
It is possible to secure the conductivity between the flip chip (10) and the bumps (11, 12), and thus to realize an electrode device that can improve the reliability of the connection between the substrate and the surface mount electronic component.

【0017】[0017]

【0018】[0018]

【実施例】以下図面について、本発明の一実施例を詳述
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

【0019】図6、図7(A)及び(B)との対応部分
に同一符号を付して示す図1〜図2(B)は、基板20
に形成された実施例の電極21を示し、有機絶縁材(例
えばポリイミド)からなる有機絶縁層23上に形成され
た第1の導電体24に加え、有機絶縁層23内部に当該
第1の導電体24と対向するように銅等の導電材からな
る第2の導電体25が形成され、かつ第1及び第2の導
電体24、25が有機絶縁層23内部に形成された導電
体でなるバイアホール26によつて電気的に一体に接続
されることにより構成されている。
The substrate 20 is shown in FIGS. 1 to 2B, in which the same parts as those in FIGS. 6, 7A and 7B are designated by the same reference numerals.
Shows the electrode 21 of the example formed in FIG. 1, and in addition to the first conductor 24 formed on the organic insulating layer 23 made of an organic insulating material (for example, polyimide), the first conductive material is formed inside the organic insulating layer 23. A second conductor 25 made of a conductive material such as copper is formed so as to face the body 24, and the first and second conductors 24, 25 are conductors formed inside the organic insulating layer 23. It is configured by being electrically and integrally connected by a via hole 26.

【0020】この場合有機絶縁層23上には、第1の導
電体24の先端部を避けて有機絶縁材からなる有機絶縁
層27が形成されている。これによりこの基板20で
は、実装対象のフリツプチツプに形成されたバンプを、
電極21を形成する第1の導電体24に、当該第1の導
電体24上に形成された有機絶縁層27の開口27Aを
介して電気的に接続することができるようになされてい
る。
In this case, an organic insulating layer 27 made of an organic insulating material is formed on the organic insulating layer 23 while avoiding the tip portion of the first conductor 24. As a result, in this substrate 20, the bumps formed on the flip chip to be mounted are
The first conductor 24 forming the electrode 21 can be electrically connected to the first conductor 24 through the opening 27A of the organic insulating layer 27 formed on the first conductor 24.

【0021】従つてこの電極21では、例えば図1〜図
2(B)及び図8(A)〜(C)との対応部分に同一符
号を付した図3(A)のように、フリツプチツプ10の
バンプ11を基板20の対応する電極21の第1の導電
体24に接触させた後、図3(B)のように当該フリツ
プチツプ10を基板20に押しつけ、この状態で加熱
(例えば150 〔°〕程度)することにより図3(C)の
ようにフリツプチツプ10のバンプ11と基板20の電
極21とを接合させる熱圧着実装工程において、フリツ
プチツプ10のバンプ11が基板20の電極21に圧接
されたときに(図3(A))、第1の導電体24を介し
て当該第1の導電体24下層の有機絶縁層23が受ける
圧力(第1及び第2の導電体24、25間に介在する有
機絶縁層23のうち、第1の導電体24とフリツプチツ
プ10のバンプ11との接触部分の下方に位置する部分
が一番大きい)を、当該有機絶縁層23の下に配設され
た弾性の少ない第2の導電体25で受けて分散させ得る
ことにより、第2の導電体25下層の有機絶縁膜層23
の撓み量を微小に抑えることができる。従つて全体とし
て第1の導電体24下層部分の撓みを微小に抑えること
ができることにより、第1の導電体24自体の撓みを微
小に抑えることができ、かくして第1の導電体24の撓
みによる断裂及びこれに伴うフリツプチツプ10のバン
プ11と基板20の電極21との接続不良を防止し得る
ようになされている。
Therefore, in this electrode 21, for example, as shown in FIG. 3 (A) in which the same reference numerals are given to the portions corresponding to FIGS. 1-2 (B) and 8 (A)-(C), the flip chip 10 is used. After contacting the bumps 11 with the first conductors 24 of the corresponding electrodes 21 of the substrate 20, the flip chip 10 is pressed against the substrate 20 as shown in FIG. 3B and heated in this state (for example, 150 [°]). 3), the bumps 11 of the flip chip 10 are pressed against the electrodes 21 of the substrate 20 in the thermocompression bonding step of bonding the bumps 11 of the flip chip 10 and the electrodes 21 of the substrate 20 as shown in FIG. 3C. Sometimes (FIG. 3 (A)), the pressure applied to the organic insulating layer 23 below the first conductor 24 via the first conductor 24 (intervened between the first and second conductors 24 and 25). Of the organic insulating layer 23 1) and the bump 11 of the flip chip 10 has the largest portion below the contacting portion) with the second conductor 25 having a low elasticity disposed under the organic insulating layer 23. The organic insulating film layer 23 below the second conductor 25 can be received and dispersed.
The amount of deflection of the Therefore, since the bending of the lower layer portion of the first conductor 24 can be suppressed to a small extent as a whole, the bending of the first conductor 24 itself can be suppressed to a small extent, and thus the bending of the first conductor 24 can be suppressed. It is designed to prevent breakage and connection failure between the bumps 11 of the flip chip 10 and the electrodes 21 of the substrate 20 due to the breakage.

【0022】またこの電極21では、図1〜図2(B)
及び図9(A)〜(C)との対応部分に同一符号を付し
た図4(A)〜(C)のように、突起12Aを有するフ
リツプチツプ10のスタツドバンプ12を、基板20の
電極21の第1の導電体24に接触させ(図4
(A))、押しつけた後(図4(B))、加熱(例えば
150 〔°〕程度)して接合させる工程において、当該ス
タツドバンプ12が圧接されたときに(図4(B))、
スタツドバンプ12の突起12Aによつて第1の導電体
24が断裂を起こしたとしても図4(C)に示すよう
に、バイアホール26で当該第1の導電体24と電気的
に接続されている第2の導電体25にスタツドバンプ1
2の突起12Aが突き刺さるため、当該スタツドバンプ
12と基板20の電極21との導電を確保することがで
き、かくして第1の導電体24の破壊によるフリツプチ
ツプ10のスタツドバンプ12と基板20の電極21と
の接続不良を防止し得るようになされている。
Further, in this electrode 21, FIG. 1 to FIG.
4A to 4C in which parts corresponding to those in FIGS. 9A to 9C are denoted by the same reference numerals, the stud bump 12 of the flip chip 10 having the protrusion 12A is connected to the electrode 21 of the substrate 20. Of the first conductor 24 of FIG.
(A)), after pressing (FIG. 4 (B)), heating (eg,
When the stud bumps 12 are pressure-welded in the step of joining them by about 150 [°] (FIG. 4 (B)),
Even if the first conductor 24 is broken by the protrusion 12A of the stud bump 12, as shown in FIG. 4C, it is electrically connected to the first conductor 24 by the via hole 26. The stud bump 1 on the second conductor 25
Since the second projection 12A pierces, the conductivity between the stud bump 12 and the electrode 21 of the substrate 20 can be secured, and thus the stud bump 12 of the flip chip 10 and the electrode 21 of the substrate 20 due to the destruction of the first conductor 24. It is designed to prevent poor connection with the.

【0023】実施例の場合、第1の導電体24は、円盤
状の先端部24A(図1〜図2(B))の半径が120
〔μm 〕程度に選定されており、第2の導電体25は半
径が140 〔μm 〕程度に選定されている。
In the case of the embodiment, the radius of the disk-shaped tip portion 24A (FIGS. 1 and 2B) of the first conductor 24 is 120.
The radius of the second conductor 25 is selected to be about 140 [μm].

【0024】ここで実際上このような構造の電極21を
有する基板20は、図5(A)〜(G)に示すような工
程により形成することができる。すなわち、まずシリコ
ン基板2にポリアミド等の有機絶縁物質を、スピンコー
ト等によつて最終的な有機絶縁層23(図1〜図2
(B))の厚みよりも薄く塗布することにより第1の有
機絶縁膜層40を形成する(図5(A))。
Here, in practice, the substrate 20 having the electrode 21 having such a structure can be formed by the steps shown in FIGS. That is, first, an organic insulating material such as polyamide is applied to the silicon substrate 2 by spin coating or the like to form a final organic insulating layer 23 (see FIGS.
The first organic insulating film layer 40 is formed by applying a thinner layer than the thickness of (B)) (FIG. 5A).

【0025】続いてこの第1の有機絶縁膜層40上にス
パツタリング等の手法を用いて金属等の導電材からなる
導電層41を形成した後(図5(B))、当該導電層4
1上にフオトレジストを塗布することによりレジスト層
42を形成し、さらに当該レジスト層42をガラスマス
ク43等を用いて所定パターンに露光し(図5
(C))、現像することにより、このレジスト層42を
所望する回路パターンと同様のパターンに整形する(図
5(D))。
Subsequently, a conductive layer 41 made of a conductive material such as a metal is formed on the first organic insulating film layer 40 by a method such as sputtering (FIG. 5B), and then the conductive layer 4 is formed.
1 is coated with a photoresist to form a resist layer 42, and the resist layer 42 is exposed to a predetermined pattern using a glass mask 43 or the like (see FIG.
(C)), by developing, the resist layer 42 is shaped into a pattern similar to a desired circuit pattern (FIG. 5D).

【0026】次いでレジスト層42を介して露出する導
電層41をウエツト又はドライエツチングすることによ
り導電層41自体をレジスト層42と同様の回路パター
ン(すなわち所望する回路パターン)に整形し(図5
(E))、この後回路パターンを形成する導電層41及
び当該導電層41から露出する第1の有機絶縁膜層40
上に第2の有機絶縁膜層44を形成する。
Then, the conductive layer 41 exposed through the resist layer 42 is wet or dry-etched to shape the conductive layer 41 itself into a circuit pattern similar to that of the resist layer 42 (that is, a desired circuit pattern) (FIG. 5).
(E)), the conductive layer 41 that will later form a circuit pattern and the first organic insulating film layer 40 exposed from the conductive layer 41.
A second organic insulating film layer 44 is formed on top.

【0027】この後図5(A)〜(F)と同様の工程を
繰り返すと共に、この際第1の導電体24に相当する導
電層45(図5(G))部分の下層部に第2の導電体2
5に相当する導電層41部分を形成する。これにより図
1〜図2(B)に示すような構造の電極21をもつ多層
配線基板46を形成することができる。
Thereafter, the same steps as in FIGS. 5A to 5F are repeated, and at this time, a second layer is formed on the lower layer portion of the conductive layer 45 (FIG. 5G) corresponding to the first conductor 24. Conductor 2
A conductive layer 41 portion corresponding to 5 is formed. Thereby, the multilayer wiring board 46 having the electrodes 21 having the structure shown in FIGS. 1 to 2B can be formed.

【0028】なお第1の導電体24と第2の導電体25
とを電気的に接続するバイアホール26は、感光性のポ
リイミドを使用して露光し、又はポリイミドにレジスト
をかけてエツジングするなどすることにより形成するこ
とができる。以上の構成において、この電極21は、基
板20を形成する有機絶縁膜層23上及びその内部に第
1及び第2の導電体24、25を平行かつ距離を離して
積層すると共に、第1及び第2の導電体24、25をバ
イアホール26により電気的に接続することにより形成
される。
The first conductor 24 and the second conductor 25
The via hole 26 for electrically connecting to and can be formed by exposing using a photosensitive polyimide, or by applying a resist to the polyimide and aging. In the above-described structure, the electrode 21 includes the first and second conductors 24 and 25 laminated in parallel and at a distance from each other on and inside the organic insulating film layer 23 forming the substrate 20. It is formed by electrically connecting the second conductors 24 and 25 with via holes 26.

【0029】従つて上述のように、フリツプチツプ10
のバンプ11、12を熱圧着する際に、有機絶縁膜層2
3が第1の導電体24を介して受ける圧力によつて撓み
のを微小に抑えて第1の導電体24の断裂を防止し得る
と共に、この際バンプ12に突起12Aが生じているこ
とにより第1の導電体24が断裂した場合においても第
2の導電体25によつて基板20の電極21及びフリツ
プチツプ10のバンプ間の導電を確保することができ、
かくして基板20の電極21及びフリツプチツプ10の
バンプ11、12間の接触不良の発生率を効果的に低減
させることができる。
Therefore, as described above, the flip chip 10
When the bumps 11 and 12 are thermocompression bonded, the organic insulating film layer 2
3 can be prevented from being bent due to the pressure received via the first conductor 24 to prevent the first conductor 24 from rupturing, and at this time, the bump 12 has the protrusion 12A. Even when the first conductor 24 is broken, the second conductor 25 can ensure the conductivity between the electrode 21 of the substrate 20 and the bump of the flip chip 10.
Thus, it is possible to effectively reduce the incidence of contact failure between the electrode 21 of the substrate 20 and the bumps 11 and 12 of the flip chip 10.

【0030】以上の構成によれば、基板20を形成する
有機絶縁膜層23内部に第1及び第2の導電体24、2
5を平行かつ距離を離して積層すると共に、第1及び第
2の導電体24、25をバイアホール26により電気的
に接続することにより基板20の電極21を形成するよ
うにしたことにより、フリツプチツプ10のバンプ1
1、12を熱圧着する際に当該基板20を構成する有機
絶縁膜層23に発生する撓みを軽減して第1の導電体2
4の断裂を防止し得ると共に、この際当該バンプ12に
生じているピン状突起12Aにより第1の導電体24が
断裂した場合においても第2の導電体25によつて基板
20の電極21及びフリツプチツプ10のバンプ11、
12間の導電を確保することができ、かくして基板20
の電極21及びフリツプチツプ10のバンプ11、12
間の接触不良の発生率を効果的に低減させ得る電極を実
現できる。
According to the above structure, the first and second conductors 24, 2 are provided inside the organic insulating film layer 23 forming the substrate 20.
5 is laminated in parallel and at a distance, and the electrodes 21 of the substrate 20 are formed by electrically connecting the first and second conductors 24 and 25 with the via holes 26. Bump 1 of 10
The first conductor 2 is formed by reducing the bending that occurs in the organic insulating film layer 23 forming the substrate 20 when thermocompressing the first and the second conductors 12.
4 can be prevented, and at the same time, even if the first conductor 24 is torn by the pin-shaped projection 12A formed on the bump 12, the second conductor 25 causes the electrode 21 of the substrate 20 and Bump 11 of flip chip 10,
It is possible to ensure conductivity between the two, and thus the substrate 20
Electrode 21 and bumps 11 and 12 of flip chip 10
It is possible to realize an electrode that can effectively reduce the occurrence rate of contact failure between the electrodes.

【0031】なお上述の実施例においては、有機絶縁膜
層23をポリイミドで形成するようにした場合について
述べたが、本発明はこれに限らず、この他ベンゾシクロ
ブテン等の有機絶縁物質を用いて有機絶縁膜層23を形
成するようにしても良い。
In the above embodiments, the case where the organic insulating film layer 23 is made of polyimide has been described, but the present invention is not limited to this, and other organic insulating materials such as benzocyclobutene are used. Alternatively, the organic insulating film layer 23 may be formed.

【0032】また上述の実施例においては、実施例によ
る電極21を、第1及び第2の導電体24、25を有機
絶縁膜層23内部において平行かつ距離を開けて積層す
ることにより形成するようにした場合について述べた
が、本発明はこれに限らず、複数の導電体を有機絶縁膜
層23内部に平行かつそれぞれ距離を介して配置し、こ
れら各導電体をバイアホール26等を用いて電気的に接
続するようにして電極を形成するようにしても良い。こ
のようにしても実施例と同様の効果を得ることができ
る。
In the above-described embodiment, the electrode 21 according to the embodiment is formed by stacking the first and second conductors 24 and 25 inside the organic insulating film layer 23 in parallel and at a distance. However, the present invention is not limited to this, and a plurality of conductors are arranged inside the organic insulating film layer 23 in parallel with each other with a distance therebetween, and these conductors are formed using the via holes 26 and the like. The electrodes may be formed so as to be electrically connected. Even in this case, the same effect as that of the embodiment can be obtained.

【0033】さらに上述の実施例においては、本発明を
フリツプチツプ10のスタツドバンプ11、12を熱圧
着する基板20の電極21に適用するようにした場合に
ついて述べたが、本発明はこれに限らず、この他種々の
基板20の電極21に適用して好適なものである。
Further, in the above-mentioned embodiment, the case where the present invention is applied to the electrode 21 of the substrate 20 for thermocompression bonding the stud bumps 11 and 12 of the flip chip 10 has been described, but the present invention is not limited to this. Besides, it is suitable to be applied to the electrodes 21 of various substrates 20.

【0034】さらに上述の実施例においては、第1及び
第2の導電体24、25を、1つのバイアホール26に
より電気的に接続するようにした場合について述べた
が、本発明はこれに限らず、複数のバイアホール26に
より電気的に接続するようにしても良い。
Further, in the above embodiment, the case where the first and second conductors 24 and 25 are electrically connected by the single via hole 26 has been described, but the present invention is not limited to this. Instead, a plurality of via holes 26 may be used for electrical connection.

【0035】さらに上述の実施例においては、実施例に
よる電極21を図5(A)(G)に示すような工程によ
り形成するようにした場合について述べたが、本発明は
これに限らず、この電極21の形成方法としては、この
他種々の形成方法を適用できる。
Further, in the above-mentioned embodiment, the case where the electrode 21 according to the embodiment is formed by the steps shown in FIGS. 5A and 5G has been described, but the present invention is not limited to this. As the method of forming the electrode 21, various other forming methods can be applied.

【0036】さらに上述の実施例においては、第1の導
電体24の先端部24Aの半径を120 〔μm 〕程度に選
定し、かつ第2の導電体25の半径を140 〔μm 〕程度
に選定するようにした場合について述べたが、本発明は
これに限らず、第1及び第2の導電体24、25の大き
さ及び形状としては、この他種々の大きさ及び形状を適
用することができる。
Further, in the above-described embodiment, the radius of the tip portion 24A of the first conductor 24 is selected to be about 120 [μm] and the radius of the second conductor 25 is selected to be about 140 [μm]. However, the present invention is not limited to this, and various other sizes and shapes may be applied as the sizes and shapes of the first and second conductors 24 and 25. it can.

【0037】さらに上述の実施例においては、本発明を
フリツプチツプ10のバンプ11、12を接合する基板
20の電極21に適用するようにした場合について述べ
たが、本発明はこれに限らず、この他TAB(Tape Auto
mated Bonding)等の各バンプを接合するための電極にも
適用でき、さらにはCOB(チツプオンボード)やワイ
ヤーボンド法により信号線が接合される電極にも適用す
ることもできる。
Further, in the above-mentioned embodiment, the case where the present invention is applied to the electrode 21 of the substrate 20 for joining the bumps 11 and 12 of the flip chip 10 has been described, but the present invention is not limited to this. Other TAB (Tape Auto
It can also be applied to electrodes for bonding bumps such as mated bonding), and further to electrodes to which signal lines are bonded by COB (chip on board) or wire bonding method.

【0038】[0038]

【発明の効果】上述のように本発明によれば、基板を形
成する有機絶縁材でなる有機絶縁膜内部に、有機絶縁膜
の厚み方向に順次距離を隔てて並ぶように複数の導電層
を形成し、各導電層をそれぞれ電気的に接続すると共
に、有機絶縁膜のうち、最上層の導電層と対向する部分
に当該導電層の一部分が露出するように形成された開口
を設け、有機絶縁膜の開口を介して露出する最上層の導
電層に表面実装型電子部品のバンプを電気的に接続する
ようにしたことにより、表面実装型電子部品のバンプを
基板の最上層の導電層に熱圧着する際に当該基板を構成
する有機絶縁膜に発生する撓みを軽減して最上層の導電
層の断裂を防止し得ると共に、この際当該バンプに生じ
ているピン状突起により最上層の導電層が断裂した場合
においても下層の導電層によつて基板の導電層と、フリ
ツプチツプのバンプとの間の導電を確保することがで
き、かくして基板及び表面実装型電子部品間の接続の信
頼性を向上させ得る電極装置を実現できる。
As described above, according to the present invention, a plurality of conductive layers are arranged inside an organic insulating film made of an organic insulating material forming a substrate so as to be sequentially arranged in the thickness direction of the organic insulating film. The organic insulating film is formed and electrically connected to each other, and an opening formed so that a part of the conductive layer is exposed is provided in a portion of the organic insulating film facing the uppermost conductive layer. By electrically connecting the bumps of the surface-mounted electronic component to the uppermost conductive layer exposed through the opening of the film, the bumps of the surface-mounted electronic component are heated to the uppermost conductive layer of the substrate. At the time of crimping, it is possible to reduce the bending that occurs in the organic insulating film that constitutes the substrate and prevent the uppermost conductive layer from rupturing. If the lower layer is broken, A conductive layer by connexion substrate layer, it is possible to secure the conductivity between the bumps of the flip chip, thus can realize an electrode system capable of improving the reliability of the connection between the substrate and the surface mount electronic device.

【0039】[0039]

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例による基板電極の構成を示す斜視図であ
る。
FIG. 1 is a perspective view showing a structure of a substrate electrode according to an embodiment.

【図2】実施例による基板電極の構成を示す上面図及び
側面図である。
2A and 2B are a top view and a side view showing a configuration of a substrate electrode according to an example.

【図3】ベアチツプのバンプの熱圧着時における実施例
の電極の説明に供する断面図である。
FIG. 3 is a cross-sectional view for explaining an electrode of an embodiment when thermocompression bonding a bump of a bare chip.

【図4】ピン状の突起を有するバンプによる実施例の電
極の破壊の説明に供する断面図である。
FIG. 4 is a cross-sectional view for explaining the destruction of the electrode of the example by the bump having the pin-shaped protrusion.

【図5】実施例の電極をもつ基板の形成方法の説明に供
する断面図である。
FIG. 5 is a cross-sectional view for explaining a method for forming a substrate having electrodes according to an example.

【図6】従来の基板電極の構成を示す斜視図である。FIG. 6 is a perspective view showing a configuration of a conventional substrate electrode.

【図7】従来の基板電極の構成を示す上面図及び側面図
である。
7A and 7B are a top view and a side view showing a configuration of a conventional substrate electrode.

【図8】ベアチツプのバンプの熱圧着時における従来の
電極の説明に供する断面図である。
FIG. 8 is a cross-sectional view for explaining a conventional electrode during thermocompression bonding of a bump of a bare chip.

【図9】ピン状の突起を有するバンプによる従来の電極
の破壊の説明に供する断面図である。
FIG. 9 is a cross-sectional view for explaining the destruction of a conventional electrode by a bump having a pin-shaped protrusion.

【符号の説明】[Explanation of symbols]

20……基板、21……電極、23、27、40、44
……有機絶縁膜層、24、25……導電体、26……バ
イアホール、27A……開口。
20 ... Substrate, 21 ... Electrode, 23, 27, 40, 44
...... Organic insulating film layer, 24, 25 …… conductor, 26 …… via hole, 27A …… opening.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−100740(JP,A) 特開 平3−246047(JP,A) 特開 平4−82241(JP,A) 特開 平5−144872(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-63-100740 (JP, A) JP-A-3-246047 (JP, A) JP-A-4-82241 (JP, A) JP-A-5- 144872 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面実装型電子部品の対応するパツド上に
形成されたバンプを、圧着するようにして電気的に接続
する基板の電極を形成する電極装置において、 上記基板を形成する有機絶縁材でなる有機絶縁膜内部
に、上記有機絶縁膜の厚み方向に順次距離を隔てて並ぶ
ように形成された複数の導電層と、 各上記導電層をそれぞれ電気的に接続する接続手段と、 上記有機絶縁膜のうち、最上層の上記導電層と対向する
部分に当該導電層の一部分が露出するように形成された
開口とを具え、上記有機絶縁膜の上記開口を介して露出
する上記最上層の導電層に上記表面実装型電子部品の上
記バンプを電気的に接続することを特徴とする電極装
置。
1. An electrode device for forming an electrode of a substrate for electrically connecting a bump formed on a corresponding pad of a surface mount electronic component by pressure bonding, the organic insulating material forming the substrate. A plurality of conductive layers formed inside the organic insulating film, which are sequentially arranged in the thickness direction of the organic insulating film so as to be spaced apart from each other, and connecting means for electrically connecting the conductive layers, respectively. Of the insulating film, an opening formed so that a part of the conductive layer is exposed at a portion facing the conductive layer of the uppermost layer, of the uppermost layer exposed through the opening of the organic insulating film. An electrode device, wherein the bump of the surface-mounted electronic component is electrically connected to a conductive layer.
【請求項2】上記表面実装型電子部品は、フリツプチツ
プでなることを特徴とする請求項1に記載の電極装置。
2. The electrode device according to claim 1, wherein the surface mount type electronic component is a flip chip.
【請求項3】上記接続手段は、上記有機絶縁膜内部に形
成されたバイアホールでなることを特徴とする請求項1
に記載の電極装置。
Wherein said connecting means according to claim 1, characterized in that in via holes formed inside the organic insulating film
The electrode device according to.
JP34051794A 1994-12-28 1994-12-28 Electrode device Expired - Fee Related JP3395926B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34051794A JP3395926B2 (en) 1994-12-28 1994-12-28 Electrode device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34051794A JP3395926B2 (en) 1994-12-28 1994-12-28 Electrode device

Publications (2)

Publication Number Publication Date
JPH08186152A JPH08186152A (en) 1996-07-16
JP3395926B2 true JP3395926B2 (en) 2003-04-14

Family

ID=18337741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34051794A Expired - Fee Related JP3395926B2 (en) 1994-12-28 1994-12-28 Electrode device

Country Status (1)

Country Link
JP (1) JP3395926B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001175829A (en) * 1999-10-08 2001-06-29 Dainippon Printing Co Ltd Noncontact data carrier and ic chip
FR3039329B1 (en) * 2015-07-22 2019-06-07 Valeo Systemes De Controle Moteur ELECTRONIC COMPONENT COMPRISING AT LEAST ONE CONNECTING LEG

Also Published As

Publication number Publication date
JPH08186152A (en) 1996-07-16

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