JPH098274A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a mesa semiconductor device whose breakdown voltage can be increased without making the chip size too large and the depth of a recessed groove for forming the device in a mesa too deep. CONSTITUTION: A semiconductor device in which a semiconductor layer 2 having a second conductivity is separated in a mesa is manufactured by forming a p-n junction 10 by providing the semiconductor layer 2 for forming a semiconductor element on a semiconductor layer 1 having a first conductivity and a recessed groove deeper than the p-n junction in the semiconductor layer 2. In the semiconductor device, a channel stopper 6 which has the same conductivity as that of the semiconductor layer 1 has and contains high concentration impurity is provided on the bottom of the recessed groove.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an improved breakdown voltage such as a diode, a transistor, a thyristor, an insulated gate bipolar transistor (IGBT), a MOSFET and an IC, and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device that can achieve downsizing of an element while improving withstand voltage with a mesa structure, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a method for increasing the breakdown voltage of a transistor, for example, as shown in FIG. 5, a field limiting ring (hereinafter referred to as F
(Referred to as LR) 4 to provide a base region 2 and a collector region 1
A method is used in which the depletion layer formed in the pn junction 10 between them is expanded to the outer peripheral side of the FLR 4.

In this conventional transistor, a collector region 1 consisting of an n ⁺ type semiconductor substrate 1a and an n ⁻ type low impurity concentration semiconductor layer 1b formed by epitaxial growth on the n ⁺ type semiconductor substrate 1a, and diffusion into the collector region 1 etc. A p-type base region 2 and an emitter region 3 formed by an n ⁺ -type impurity in the base region 2 by diffusion or the like. The base region is formed on the outer peripheral side of the pn junction 10 between the base and collector. A p-type F that has the same conductivity type as the base region so as to surround the vertical pn junction between the collectors.
LR4 is provided. Further, 5 is an insulating film made of SiO ₂ or the like provided on the surface of the semiconductor layer 1b, 6 is a channel stopper for terminating the depletion layer, and 7, 8, 9 are collector, base and emitter electrodes, respectively.

As another method of increasing the breakdown voltage, as shown in FIG. 6, a groove 11 deeper than the depth of the pn junction 10 between the base region 2 and the collector region 1 is provided around the base region 2. A method is known in which the semiconductor layer 1b has a mesa shape. With such a mesa shape, the extension of the depletion layer of the pn junction 10 is not bent toward the front surface side of the semiconductor layer 1b, but extends in parallel along the pn junction 10 to form the concave groove 11.
Corresponding to the passivation film 5a. Therefore, the depletion layer does not have a curved portion, and the breakdown voltage is improved even at the interface with the passivation film 5a (generally, when the curved portion is formed in the middle of the depletion layer, the breakdown voltage at the interface with the insulating film on the surface also decreases, It is known that the same breakdown voltage cannot be obtained unless the depletion layer is widened as compared with the case where no curved portion is formed). Further, the passivation film 5 in the groove 11 part
Since a is provided at a position different from the operation region, it can be made a film having a high withstand voltage by adjusting the charges in the passivation film 5a, and a higher withstand voltage can be obtained by using the mesa structure. In FIG. 6, the same parts as those in FIG. 5 are designated by the same reference numerals.

In order to further increase the breakdown voltage of this mesa-shaped semiconductor device, it is possible to reduce the impurity concentration of the n ^-- type semiconductor layer 1b near the pn junction 10 and widen the depletion layer to achieve a high breakdown voltage. However, the depletion layer spreads under the mesa-shaped concave groove 11. Therefore, if the groove 11 is scribed to form a chip, the wide portion of the depletion layer is exposed at the cut portion of the semiconductor substrate, and if the depletion layer portion is directly exposed, it becomes rather unstable and the breakdown voltage decreases. Therefore, in order to obtain a higher withstand voltage with the mesa shape, as shown in FIG. 6, the channel stopper 6 is provided outside the concave groove 11 for forming the mesa shape so that the depletion layer terminates at the channel stopper 6. Then, the extension of the depletion layer is moved away from the base region 2 via the lower portion of the concave groove and terminated at the channel stopper 6 by scribing at the channel stopper 6 portion. By doing so, the end portion of the depletion layer is not directly exposed to the cut portion of the chip, and a high breakdown voltage is achieved.

In the above-mentioned two methods for achieving a high breakdown voltage, when the mesa shape is used, the deeper the groove is, the wider the groove needs to be to form it by etching. FLR if the distance between the edge and the end of the chip (channel stopper 6) is 200 μm or less
, And if it is wider than that, the mesa shape is often used.

[0007]

When the breakdown voltage is increased due to the shape of the mesa, if the depletion layer is expanded to obtain a higher breakdown voltage as described above, the depletion layer reaches the lower side of the groove and the outside of the groove. However, there is a problem that the chip becomes large and the end portion between the concave groove and the scribe portion is cracked or liable to chip, which lowers the yield.

On the other hand, in order to prevent the expanded depletion layer from reaching the lower side of the groove, the groove may be formed deep.
If the groove is too deep, there is a problem that the semiconductor wafer runs along or cracks easily occur, resulting in a decrease in reliability.

The present invention solves such a problem, and in a mesa-shaped semiconductor device, the chip size is not increased even if higher withstand voltage is obtained, and the depth of the concave groove for forming the mesa shape is obtained. An object of the present invention is to provide a semiconductor device capable of obtaining a high breakdown voltage without making the depth too deep.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A pn junction is formed by providing a second conductivity type semiconductor layer for forming a semiconductor element on the first conductivity type semiconductor layer, and a groove deeper than the depth of the pn junction is formed in the second conductivity type semiconductor layer. In this way, the second conductive type semiconductor layer is separated into a mesa shape, and a channel stopper having the same conductive type as the first conductive type semiconductor layer and a high impurity concentration is provided at the bottom of the groove. Has been.

The first conductive type semiconductor layer is a collector region, the second conductive type semiconductor layer is a base region, and the groove is provided on the outer periphery of the base region, and the first conductive type semiconductor layer is formed in the base region. By providing the emitter region, a high withstand voltage transistor having a mesa shape can be obtained.

The method of manufacturing a semiconductor device of the present invention comprises (a) first
A channel stopper, which is a high-concentration region of the first conductivity type, is formed around the element formation region of the conductivity type semiconductor layer,
(B) A second conductivity type semiconductor layer is formed on the surface side of the first conductivity type semiconductor layer, and (c) a portion of the second conductivity type semiconductor layer located above the channel stopper is etched to form the channel. It is characterized in that a concave groove reaching the stopper is formed, (d) a passivation film is formed in the concave groove, and (e) it is cut into chips by the channel stopper portion.

Before forming the second conductivity type semiconductor layer in the step (b), the first conductivity type semiconductor layer having a low impurity concentration is further epitaxially grown to increase the distance between the pn junction surface and the bottom of the groove. Even if the withstand voltage is high and the expansion of the depletion layer is large, the depletion layer is likely to terminate on the mesa-shaped wall surface, and the high withstand voltage is easily obtained.

A transistor structure can be formed by forming a first conductivity type semiconductor region in the second conductivity type semiconductor layer.

[0015]

According to the present invention, since the channel stopper is formed in the semiconductor layer below the mesa-shaped concave groove with the same conductivity type as the semiconductor layer and with a high impurity concentration, the depletion layer of the pn junction is high. Even if it spreads by the voltage, it enters the channel stopper without passing under the concave groove, and the depletion layer terminates at the channel stopper. As a result, a stable high breakdown voltage can be obtained without exposing the end of the depletion layer that has spread to the cut surface even if the chip is formed by scribing in the groove.

Further, since the depletion layer expanded by the channel stopper can be terminated, it is not necessary to form the concave groove for forming the mesa deep enough to completely cover the range of the depletion layer, and the chip end portion can be formed. It is possible to obtain a highly reliable semiconductor device which suppresses the occurrence of chipping and cracking.

According to the method of manufacturing a semiconductor device of the present invention, a channel stopper is formed in advance at a cutting portion for chip formation, and a second conductivity type semiconductor layer is formed thereon, and the second conductivity type semiconductor is formed. Since the upper portion of the channel stopper of the layer is etched to form the mesa-shaped concave groove, the channel stopper can be easily formed below the concave groove. As a result, it is possible to easily obtain a small-sized and high-breakdown-voltage semiconductor device by scribing in the groove portion to form a chip.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device of the present invention and a manufacturing method thereof will be described with reference to the drawings.

FIG. 1 is a cross-sectional explanatory view of a transistor of one embodiment of a semiconductor device of the present invention, FIG. 2 is a diagram showing each step of the manufacturing method, and FIG. 3 is a part of the manufacturing step of another embodiment of the manufacturing method. FIG. 4 is a diagram showing the yield distribution of the semiconductor device having the structure of FIG. 1 in comparison with that of the conventional structure.

In FIG. 1, a collector region (first conductivity type semiconductor layer) of the first conductivity type, for example, an n ⁺ type semiconductor substrate 1a on which an n ⁻ type semiconductor layer 1b having a low impurity concentration is formed
1 is formed with a base region (second conductivity type semiconductor layer) 2 having a second conductivity type, for example, a p-type semiconductor layer by diffusion or epitaxial growth, and a pn junction 10 is formed between the base region 2 and the collector region 1. Are formed. In the base region 2, a first conductivity type, for example, n ⁺ type emitter region 3 is further formed by diffusion or ion implantation, and an insulating film 5 made of silicon oxide, silicon nitride or the like is formed on the surface thereof. Has been done. A side portion of the base region 2 is etched deeper than the pn junction 10 to have a mesa shape (mesa portion), and a passivation film 5a made of lead glass or glass containing aluminum oxide is formed on the surface thereof. An n ⁺ type channel stopper 6 having the same conductivity type as that of the semiconductor layer 1b and a high impurity concentration is formed in the n ⁻ type semiconductor layer 1b at the bottom of the mesa portion. A collector electrode 7 made of gold or titanium or the like is provided on the back surface of the semiconductor substrate 1a, and a base electrode 8 and an emitter electrode 9 made of aluminum or the like are provided on the front surface side so as to make ohmic contact with the base region 2 and the emitter region 3, respectively. There is.

The transistor of this embodiment has a pn junction 10
In order to improve the breakdown voltage of the n ^- type semiconductor, a groove (mesa portion) deeper than the pn junction 10 is formed to form a mesa structure, and an n ⁻ -type semiconductor is formed in contact with the bottom of the groove (mesa portion) forming the mesa structure. The layer 1b is characterized in that an n ⁺ type channel stopper 6 is provided, and the groove (mesa portion) and the channel stopper 6 portion are scribed to form a chip. Since the transistor of this embodiment has such a structure, the depletion layer 12 spreads on both sides of the pn junction 10 even if a high reverse bias voltage is applied between the base region 2 and the collector region 1, and Even if the depletion layer 12 extends to the lower side of the mesa portion, it terminates in the channel stopper 6. As a result, even when scribing at the mesa portion for chip formation, the end portion of the depletion layer does not directly appear in the scribed cross section, and a stable high breakdown voltage can be obtained. It should be noted that in order to obtain a high breakdown voltage, p
By lowering the impurity concentration of the n ⁻ type semiconductor layer 1b in the n junction 10 part, the depletion layer 12 becomes wider and the breakdown voltage becomes higher.
According to the present invention, since the channel stopper 6 is provided, the high breakdown voltage can be realized without exposing the end portion of the depletion layer 12 to the portion directly cut by the scribe.

Further, according to the semiconductor device of the present invention, the channel stopper 6 is formed below the mesa portion, and the depletion layer 1 is formed.
Since the end of 2 is terminated by the channel stopper 6, it is not necessary to form the concave groove for forming the mesa structure more than necessary, and there is no problem such as cracking or damage of the semiconductor wafer, and the yield is significantly increased. improves. In addition, since the groove is scribed during chip formation, no protrusion can be formed between the groove and the cut portion, and there is no chipping or damage during handling.
Yield is greatly improved. FIG. 4 shows the yield distribution of the transistor according to the present embodiment as compared with the conventional case of scribing outside the groove (conventional example). Regarding the breakdown voltage, a breakdown voltage similar to the conventional one was obtained, and the yield was significantly increased from about 50% to about 80%, as is clear from FIG.

Next, an embodiment of the method for manufacturing the semiconductor device of the present invention will be described with reference to FIG. This embodiment is one embodiment of a method of manufacturing the transistor shown in FIG.

First, as shown in FIG. 2A, when the impurity concentration is about 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3, it is 130
The impurity concentration is 5 × 10 ¹³ / on one surface of the n ⁺ type semiconductor substrate 1a having a thickness of about μm by epitaxial growth or the like.
The collector region 1 is formed by forming the n ⁻ type semiconductor layer 1b having a thickness of about cm ³ to a thickness of about 100 μm, or by forming the n ⁺ type semiconductor layer 1a on one surface of the n ⁻ type semiconductor substrate 1b by impurity diffusion or the like. And a mask 1 made of silicon oxide or silicon nitride on the n ⁻ type semiconductor layer 1b.
3 is formed by thermal oxidation or a CVD method.

Next, as shown in FIG. 2B, an opening 13a is formed in the mask 13 at a position corresponding to the periphery of the semiconductor element forming region, and an n-type impurity such as phosphorus or arsenic is ion-implanted or formed. Introduced by diffusion etc. n ⁺
The channel stopper 6 is formed as a mold.

Next, as shown in FIG. 2C, in order to form the base region 2, for example, a p-type second conductivity type semiconductor layer 2a is epitaxially grown to a thickness of about 20 μm.

After that, n-type impurities such as phosphorus and arsenic are diffused in the base region 2 to form an emitter region 3 of 7 to 10 μm.
The insulating film 5 is formed to a thickness of about m, and the surface mask is re-formed to open only the upper part of the channel stopper 6.
Then, the groove 11 is formed by wet etching or dry etching using a hydrofluoric acid solution so as to reach the channel stopper 6 (see FIG. 2D).

After that, as shown in FIG.
1 is provided with a passivation film 5a made of lead glass, glass containing aluminum oxide, or the like on the surface of 1.
A base electrode 8 and an emitter electrode 9 are formed by coating aluminum or the like by a sputtering method or a vacuum deposition method,
Further, a metal film such as gold or titanium is similarly coated on the back surface side of the semiconductor substrate 1a to form a collector electrode 7, and the semiconductor substrate 1 is scribed at the central portions of the groove 11 and the channel stopper 6, so that the semiconductor substrate 1 shown in FIG. A transistor chip as shown in Fig. 3 is obtained.

FIG. 3 is a diagram showing a manufacturing process of another embodiment of the method for manufacturing a semiconductor device of the present invention.

In this embodiment, as shown in FIG. 3E, before the p-type second conductivity type semiconductor layer 2a is formed in the step (c) of the embodiment shown in FIG. An n ⁻ type or n ⁻ type first conductivity type semiconductor layer 14 is formed, and then, as shown in FIG. 3 (f), the surface side thereof is used as a p type second conductivity type semiconductor layer 2a. 3 and the other steps, that is, the steps of FIGS. 2A to 2B, and FIG.
Subsequent steps such as (g) forming the emitter region 3 and performing etching to reach the channel stopper 6 for forming the mesa shape are the same as those in the above embodiment.

The formation of the second conductivity type semiconductor layer 2a is as follows.
As shown in FIGS. 3 (e) and 3 (f), the first conductive type (n type) semiconductor layer 14 may be formed to have a thickness of about 20 to 80 μm and the surface side thereof may be made to be p type by impurity diffusion or the like. In FIG. 3E, the n ⁻ -type or n ⁻ -type first conductive type semiconductor layer 14 is thinly formed to a thickness of about 10 to 50 μm, and then the dopant is changed to p type and the second conductive type semiconductor layer 2 a is formed to 10 μm.
You may epitaxially grow so that it may become about 30 micrometers in thickness.

According to this embodiment, after the channel stopper 6 is formed, the n ^-- type or n ^-- type first conductive type semiconductor layer 14 is formed, and then the second conductive type semiconductor layer 2a is formed. Therefore, even if a wide depletion layer is formed by applying a high reverse bias to the pn junction 10, the pn junction 10 is formed at a position higher than the bottom surface of the groove 11, and the end portion of the depletion layer has the groove 1
By hitting the side wall of No. 1, it is possible to achieve a higher breakdown voltage.

Although each of the above embodiments has been described by taking the example of the npn-type transistor, it goes without saying for the pnp-type transistor, and also has a pn junction other than the transistor and requires a high breakdown voltage against reverse bias. Semiconductor devices such as diodes, thyristors, triacs, insulated gate bipolar transistors (IGBT), MOSFE
The present invention can be similarly applied to T, IC and the like.

[0034]

According to the present invention, since the channel stopper is formed in the semiconductor layer at the bottom of the concave groove which is formed into a mesa shape of a semiconductor device having a mesa shape and high withstand voltage, a high reverse bias voltage is applied. Even if the depletion layer spreads, the end of the depletion layer terminates at the channel stopper. Therefore, even if the groove is scribed, the end portion of the depletion layer is not exposed at the cut portion, and a stable high breakdown voltage semiconductor device can be obtained.
As a result, it is not necessary to scribe outside the groove, and a high breakdown voltage semiconductor device can be obtained with a small chip.

Further, since the groove can be scribed,
No protrusion is formed between the groove and the scribe surface, so that the occurrence of chips and cracks can be suppressed, the yield is greatly improved, and the cost is greatly reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional explanatory view of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing an example of a method of manufacturing the semiconductor device of FIG.

FIG. 3 is a diagram showing another embodiment of the method for manufacturing the semiconductor device of FIG.

FIG. 4 is a diagram showing a yield of the semiconductor device of FIG. 1 in comparison with a conventional one.

FIG. 5 is a cross-sectional explanatory view of a conventional semiconductor device having a high breakdown voltage.

FIG. 6 is a cross-sectional explanatory view of a conventional semiconductor device having a high breakdown voltage.

[Explanation of symbols]

 1 collector region (first conductivity type semiconductor layer) 2 base region (second conductivity type semiconductor layer) 3 emitter region 6 channel stopper 10 pn junction 11 recessed groove

Claims (5)

[Claims] 1. A pn formed by providing a second conductivity type semiconductor layer for forming a semiconductor element on the first conductivity type semiconductor layer.
A semiconductor device in which a junction is formed and a groove deeper than the depth of the pn junction is formed in the second conductivity type semiconductor layer to separate the second conductivity type semiconductor layer into a mesa shape. A semiconductor device in which a channel stopper having the same conductivity type as the first conductivity type semiconductor layer and a high impurity concentration is provided at the bottom of the groove. 2. The first conductive type semiconductor layer is a collector region, the second conductive type semiconductor layer is a base region, and the groove is provided on an outer periphery of the base region, and the first conductive type semiconductor layer is provided in the base region. The semiconductor device according to claim 1, further comprising a mold emitter region. 3. A channel stopper, which is a first-conductivity-type high-impurity-concentration region, is formed around an element forming region of the first-conductivity-type semiconductor layer, and (b) a surface of the first-conductivity-type semiconductor layer. A second conductivity type semiconductor layer is formed on the side, and (c) a portion of the second conductivity type semiconductor layer located above the channel stopper is etched to form a concave groove reaching the channel stopper. A method of manufacturing a semiconductor device, comprising forming a passivation film in the groove, and (e) cutting into a chip by the channel stopper portion. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first conductivity type semiconductor layer having a low impurity concentration is further epitaxially grown before forming the second conductivity type semiconductor layer in the step (b). 5. The method of manufacturing a semiconductor device according to claim 3, wherein a transistor structure is formed by forming a first conductivity type semiconductor region in the second conductivity type semiconductor layer.