JPH098161A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device which reduces the number of production processes and whose product yield is enhanced by reducing a process which removes a gate insulating film in a region in which a base electrode or an emitter electrode is to be formed. CONSTITUTION: First, a gate insulating film 1 and a poly-Si film (not indicated in the figure) as a conductive film are formed on a substrate 10 in this order. In succession, by means of lithography and etching, a poly-Si film is formed, a pattern for the gate electrode 16 of a MOS transistor is formed, and, at the same time, the emitter electrode pattern 2a of a bipolar transistor is formed. Then, ions are passed through the emitter electrode pattern 2a and the gate insulating film 1 so as to be implanted into the substrate 10. Thereby, an interatomic bond in the gate insulating film 1 between the emitter electrode pattern 2a and the substrate 10 is cut.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a MOS transistor and a bipolar transistor are formed on the same substrate.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor device of this type, N
Bipolar CMOS (Complementary Metal Oxide Semicond) including a CMOS including a MOS transistor (hereinafter referred to as NMOSFET) and a PMOS transistor (hereinafter referred to as PMOSFET) and a bipolar transistor (hereinafter referred to as Bip transistor)
uctor: BiCMOS). Conventionally, this BiC
In the manufacturing process of MOS, a device has been devised to minimize the number of manufacturing steps. This is because an increase in the number of manufacturing steps directly means an increase in manufacturing cost and also causes a decrease in product yield.

As the above-mentioned device for minimizing the number of manufacturing steps of BiCMOS, it is general to form the constituent elements of the Bip transistor and the constituent elements of the CMOS in the same material and in the same step. There is. In Figure 2, CM
An example of BiCMOS in which the gate electrode of the OS and the emitter electrode of the Bip transistor are formed of the same polysilicon (Poly-Si) in the same step is shown. Further, FIG. 3 shows a process of forming such a gate electrode and an emitter electrode of BiCMOS. 2 and 3, the CMOS PMOSFET formation region and the npnBip transistor formation region are shown, and the CMOS NMOSFET formation region is omitted.

That is, in the BiCMOS shown in FIG.
A substrate 10 is composed of a p-type silicon substrate 11 and an n-type epitaxial layer 13 formed on the surface of the p ⁺ type silicon substrate 11 with an n ⁺ type buried diffusion layer 12 interposed therebetween. PM on the surface of the substrate 10
An element isolation film 17 made of silicon oxide (SiO ₂ ) is formed so as to surround the formation region of the OSFET 14 and the formation region of the Bip transistor 22.
The gate electrode 16 is formed on the substrate 10 in the formation region of 14 through the gate insulating film 15 made of SiO ₂ . An insulating film 18 of CVD-SiO ₂ is formed on the substrate 10 so as to cover the gate electrode 16, and p ^{+ of} the substrate 10 is further formed on the insulating film 18.
A source electrode 20 and a drain electrode 21 made of aluminum (Al) that are respectively connected to the mold source and drain layers 19 are formed.

On the other hand, in the formation region 22 of the npnBip transistor, the emitter electrode 26 is formed immediately above the n ⁺ type emitter layer 25 formed on the base body 10, and the emitter electrode 26 is covered. An insulating film 18 is formed on the substrate 10. Then, on the insulating film 18, the p-type base layer 2 formed on the base body 10 is formed.
Al base electrode 27 connected to 4 and emitter electrode 2
Al emitter extraction electrode 28 connected to 6 and the substrate 10
Collector layer 23 through n ⁺ type plug 29 formed in
And an Al collector electrode 30 connected to each of the electrodes. The PMOSFET 14 in the substrate 10
A p ⁺ -type channel stop region 31 is formed between the formation region of ^N , the formation region of NMOSFET, and the formation region of Bip transistor 22.

In such a BiCMOS, in order to form the gate electrode 16 and the emitter electrode 26, first, as shown in FIG. 3A, the surface of the substrate 10 is oxidized and each element surrounded by the element isolation film 17 is formed. Areas to be formed 141, 2
A gate insulating film 15 made of SiO ₂ and having a film thickness of about 5 nm is formed on 21. Next, as shown in FIG. 3B, a p-type impurity is ion-implanted (Ion Implantation) into the base formation planned region 222 of the substrate 10 to form a base impurity introduction layer 24a. Next, as shown in FIG. 3C, the gate insulating film 15 in the emitter formation region 223 is removed by etching.

Then, the surface of the substrate 10 is subjected to a Po by a CVD method.
A ly-Si film (not shown) is formed, and necessary impurities are doped into the gate formation planned region 142 and the emitter formation planned region 223 of the Poly-Si film. For example, in the area 142 where the gate is to be formed, Poly-
Doping phosphorus with high concentration to reduce the resistance of Si,
The emitter layer 2 is formed in the emitter formation region 223 later.
Dope arsenic to form 5. After that, the poly-Si film in the unnecessary region is removed by photolithography and etching, and the gate electrode 16 and the emitter electrode 26 are formed as shown in FIG. 3D.

Then, the base 10 is heat-treated to diffuse and activate the impurities in the base impurity introduction layer 24a to form the base layer 24 as shown in FIG. Arsenic present is thermally diffused into the substrate 10 to form the emitter layer 25 on the substrate 10 immediately below the emitter electrode 26. Note that the steps before and after the above steps are not directly related to the present invention and may be any manufacturing method that can be easily inferred from the known manufacturing steps of BiCMOS, and therefore the description thereof is omitted here.

[0009]

However, the MOSFE
In the above-described method for manufacturing a semiconductor device, in which the gate electrode of T and the emitter electrode of the Bip transistor are formed of Poly-Si in the same step, the gate insulation of the region where the emitter is to be formed is performed before the Poly-Si film is formed. The film must be removed by etching, and in order to remove the gate insulating film, a photolithographic patterning process using a resist, an etching process for removing the gate insulating film, a removing process of the resist patterned on the surface of the substrate, etc. However, there is a complaint that several steps are required.

The present invention has been made to solve the above problems, and it is possible to reduce the step of removing the gate insulating film in the region where the base electrode or the emitter electrode is to be formed, thereby reducing the number of manufacturing steps and the product. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can improve the yield.

[0011]

SUMMARY OF THE INVENTION The present invention provides an MO on a substrate.
This is done in a method of manufacturing a semiconductor device in which an S transistor and a bipolar transistor are formed. That is, first, in a first step, an insulating film and a conductive film are laminated in this order on a substrate, and then the conductive film is formed into a pattern of a gate electrode of a MOS transistor by lithography and etching, and at the same time, a bipolar transistor is formed. It is formed in the pattern of the base electrode or the emitter electrode. Then, in a second step, bonds between atoms in the insulating film between the base electrode pattern or the emitter electrode pattern and the substrate are cut off.

[0012]

In the method of manufacturing a semiconductor device according to the present invention, the insulating film between the base electrode or emitter electrode pattern and the substrate is made of, for example, silicon oxide, and silicon oxide of silicon oxide is formed by allowing ions to pass through this insulating film. When the bond between the atom and the oxygen atom is broken, the structure of the insulating film becomes coarse. As a result, the insulating property of the insulating film is lowered,
The pattern of the base electrode or the emitter electrode and the base body are electrically connected. Further, for example, when ions are passed through the insulating film and then the substrate is heat-treated, oxygen atoms whose bonds with silicon atoms in the insulating film are broken are aggregated on the pattern side of the base electrode or the emitter electrode, and the insulating property of the insulating film is improved. It is surely lost, and electric conduction between the pattern of the base electrode or the emitter electrode and the substrate is surely secured.

[0013]

Embodiments of the present invention will be described below. FIG. 1 is a diagram for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention. Particularly, the semiconductor device shown in FIG.
CMOS composed of FET and PMOSFET, and np
FIG. 6 is a diagram showing a process of forming a gate electrode of a MOSFET and an emitter electrode of a Bip transistor, which is a feature of the present invention, in a BiCMOS including an nBip transistor. In FIG. 1, the CMOS PMOSF is used.
The ET forming region and the npnBip transistor forming region are shown, and the CMOS NMOSFET forming region is omitted. Further, in the drawing, the same forming elements as those of the conventional example are denoted by the same reference numerals.

In this embodiment, in order to form the gate electrode of the MOSFET and the emitter electrode of the Bip transistor, first, as shown in FIG. 1A, a substrate 10 having an element isolation film 17 formed on its surface in advance is prepared. Then, the base 10
The surface is oxidized to form the gate insulating film 1 made of SiO ₂ and having a thickness of about 5 nm in each of the device formation planned regions 141 and 221 formed by the device isolation film 17. The process before the formation of the element isolation film 17 is the same as the conventional process.

Next, polysilicon (Poly-Si) is deposited on the surface of the substrate 10 by the CVD method, and Poly-S is formed in the gate formation region 142 of this Poly-Si film (not shown).
Phosphorus is doped at a high concentration to reduce the resistance of i, and the region 223 where the emitter is to be formed is doped with arsenic for forming an emitter layer later. After that, by photolithography and etching, as shown in FIG. 1B, the gate electrode 16 made of Poly-Si and the Poly-Si are formed.
An emitter electrode pattern 2a made of is formed.

Next, as shown in FIG. 1C, boron, which is a p-type impurity, is ion-implanted into the base formation region 222 of the substrate 10 through the emitter electrode pattern 2a and the gate insulating film 1. Then, the physical damage of forming the impurity introduction layer 3a of the base and breaking the bond between silicon (Si) atoms and oxygen (O) atoms in the gate insulating film 1 to make the structure of the gate insulating film 1 coarse and dense. give.

In this ion implantation, the gate insulating film 1 is effectively physically damaged. Therefore, the ion implantation conditions are set so that the peak (r _p ) of the ion concentration comes to the surface of the substrate 10 immediately below the emitter electrode pattern 2a. To set. For example, when the thickness of the Poly-Si film forming the gate electrode 16 and the emitter electrode pattern 2a is 200 nm and the ion species is boron, if the implantation energy of boron is 65 KeV, the peak position of the boron concentration is The position is such that it passes through the emitter electrode pattern 2a and the gate insulating film 1. The current gain h of the npnBip transistor to be formed depends on the dose amount at the time of ion implantation.
_{The FE} is determined, but a dose amount of the order of 10 ¹³ cm ^-2 is optimal.

In this ion implantation step, boron of the order of 10 ¹³ cm ⁻² passes through the gate insulating film 1 in the region 222 where the base is to be formed, and the gate insulating film 1 is damaged as described above. The insulating property of the film 1 is lowered to such an extent that the emitter electrode pattern 2a and the substrate 10 immediately below the emitter electrode pattern 2a are electrically connected to each other.

After the ion implantation is performed, the substrate 30 is heat-treated at, for example, 1100 ° C. for about 10 seconds so that the O atoms in the gate insulating film 1 whose bonds with Si atoms have been cut by the ion implantation are used as emitter electrodes. The insulating property of the gate insulating film 1 is completely lost by aggregating on the pattern 2a side. That is, the gate insulating film 1 is completely destroyed. As a result, as shown in FIG. 1D, the emitter electrode 2 is formed, which is surely electrically connected to the base body 30 via the gate insulating film 1 whose insulating property is lost. By this heat treatment, the impurities introduced into the base impurity introduction layer 3a are diffused and activated to form the base layer 3, and
Arsenic introduced from the emitter electrode pattern 2a is thermally diffused into the substrate 10 to form the emitter layer 4 on the substrate 10 immediately below the emitter electrode 2.

In this heat treatment, RT such as lamp annealing is performed.
By using A (Rapid Thermal Anneal), the gate insulating film 1 is effectively destroyed. Further, in the region 222 where the base is to be formed, in the region where the emitter electrode pattern 2a does not exist immediately above, the heat treatment recovers the damage due to the ion implantation to some extent.

Through the above steps, the gate electrode 16 of the MOSFET and the emitter electrode 4 of the Bip transistor are formed. After that, as shown in FIG. 2, the source / drain layer 19, plug 29, and
By forming the insulating film 18, the source electrode 20, the drain electrode 21, the base electrode 27, the emitter extraction electrode 28, the collector electrode 30, and the like, the PMOSFET 14 and N
Bi consisting of MOSFET and Bip transistor 22
CMOS is manufactured.

In the above-mentioned embodiment, the impurity ion implantation layer 3a of the base can be formed by the same ion implantation, and the insulating property of the gate insulating film 1 between the emitter electrode pattern 2a and the substrate 10 is lost. You can That is, the emitter electrode 2 that is electrically connected to the base 10 can be formed without performing the conventional gate insulating film removing step, so that the number of steps required for the gate insulating film removing step can be reduced. It is possible to reduce the total number of manufacturing steps. Therefore, it is possible to manufacture the BiCMOS at lower cost and with higher yield than the conventional one.

In the above embodiment, the case where the gate electrode of the MOSFET and the emitter electrode of the Bip transistor are formed of the same conductive film (Poly-Si) has been described.
The base electrode pattern of the Bip transistor and the gate electrode of the MOSFET are formed of the same material such as Poly-Si, and the insulating film existing between the base electrode pattern and the substrate is ion-implanted and destroyed by heat treatment to destroy the gate electrode. And the base electrode can also be formed.

In the above embodiment, the case where the heat treatment is performed after the ion implantation is described. However, as described above, the insulation property of the insulating film between the emitter electrode or the base electrode and the substrate can be obtained by only the ion implantation. , It can be reduced to such an extent that the electrical conduction between the emitter electrode or the base electrode and the substrate immediately below it is hardly affected. However, by utilizing the heat treatment that also serves as diffusion and activation of the base impurity introduction layer as in the above embodiment, the insulating property of the insulating film can be more surely lost without increasing the number of steps.

Further, in the ion implantation step of the above embodiment,
Boron ions are used as ions to be ion-implanted in order to also form the impurity introduction layer of the base, but other ions such as argon (Ar) ions are used to form ions for forming the impurity introduction layer of the base. It is also possible to continuously perform the implantation and the ion implantation for lowering the insulating property of the insulating film. In the above embodiment, the case where the present invention is applied to the manufacture of BiCMOS has been described, but the present invention is applied to the Bip transistor and one MOSFET.
Needless to say, it can be applied to the manufacture of a semiconductor device including

[0026]

As described above, in the method of manufacturing a semiconductor device of the present invention, the bond between atoms in the insulating film between the base electrode or emitter electrode pattern and the substrate is
For example, since ions are cut by passing through the insulating film to make the structure of the insulating film coarse and dense, the insulating property of the insulating film can be almost lost. Therefore, it is possible to form the base electrode or the emitter electrode that is electrically connected to the substrate without performing the step of removing the insulating film, and thus it is possible to reduce the number of steps required for the step of removing the insulating film. it can. If the heat treatment is performed after the ions have passed through the insulating film, the insulating property of the insulating film can be more surely lost. Therefore, according to the present invention, since a semiconductor device can be manufactured with a small number of steps, manufacturing cost can be reduced and product yield can be improved.

[Brief description of drawings]

FIG. 1 is a side sectional view of an essential part for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 2 is a side sectional view of an essential part showing an example of a BiCMOS in which a gate electrode and an emitter electrode are formed of the same conductive material and in the same step.

FIG. 3 is a side sectional view of an essential part for explaining an example of a conventional method for manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 gate insulating film 2 emitter electrode 2a emitter electrode pattern 10 substrate 16 gate electrode

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a MOS transistor and a bipolar transistor formed on a substrate, wherein an insulating film and a conductive film are laminated in this order on the surface of the substrate, followed by lithography and etching. Forming the conductive film in the pattern of the gate electrode of the MOS transistor and simultaneously forming the conductive film in the pattern of the base electrode or the emitter electrode of the bipolar transistor, and the pattern of the base electrode or the pattern of the emitter electrode, and A second step of breaking bonds between atoms in the insulating film between the substrate and the substrate, and a method of manufacturing a semiconductor device. 2. The cutting in the second step is performed by implanting ions into the substrate through the pattern of the base electrode or the pattern of the emitter electrode and the insulating film. A method for manufacturing a semiconductor device as described above. 3. The cutting in the second step is performed by implanting ions into the substrate through the pattern of the base electrode or the pattern of the emitter electrode and the insulating film, and then heat treating the substrate. The method for manufacturing a semiconductor device according to claim 1, wherein