JPH0974344A - Drive circuit for insulated gate semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate switching speed while suppressing transient voltage or current oscillation to be frequently generated when turning on or off a semiconductor element. SOLUTION: A drive circuit uses a voltage detecting means 10 for comparing a gate voltage Vg of a semiconductor element 1 with a reference value and generating a voltage detect signal Sd to change a logical state corresponding to that result, potential divider circuits 21 and 22 for ON and OFF operations for dividing a gate drive power supply voltage Vd, tristate circuits 31 and 32 for which those respective potential dividing points are commonly connected with output points, and control means 40 for controlling the ON/OFF of a pair of those respective transistors corresponding to the logical states of an input signal Si and the voltage detect signal Sd. During delay time τp or τn from a change in the logical state of the input signal Si to a change in the logical state of the voltage detect signal Sd, the output points of the tristate circuits 31 and 32 are alternately controlled into a floating state, and voltages divided by the potential divider circuits 21 and 22 are outputted as intermediate values Vip and Vin of output signals Sop and Son. An output signal So is derived from the mutual node of drive transistors 50p and 50n for receiving those voltages, and the gate of the semiconductor element 1 is driven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit suitable for preventing a transient overvoltage or overcurrent from occurring when an insulated gate semiconductor element for electric power such as an insulated gate bipolar transistor (hereinafter referred to as an IGBT) is turned on / off or switched. Regarding

[0002]

2. Description of the Prior Art Insulated gate semiconductor devices such as the above-mentioned IGBTs have a high input inductance of the gate as compared with bipolar devices, and therefore have the advantage that they can be driven with a small amount of power and the load can be switched at a high frequency. Widely used for controlling equipment. However, when switching at high speed, overvoltage and overcurrent are likely to occur, so
It is customary to turn a semiconductor element on and off by a simple drive circuit with a resistance connected to its insulated gate. FIG. 3 shows the waveforms of main signals related to such a conventional example.

The semiconductor element 1 shown on the right side of FIG.
BT is used in a state where the emitter side is grounded and the collector side is connected to the load 2 receiving the power supply voltage V. The load 2 is inductive in the illustrated example, and a diode 3 that prevents the generation of an overvoltage when the semiconductor element 1 is turned off is connected in antiparallel. The drive circuit 4 receives an input signal Si of about 5V which is a logic signal designating the on / off state of the semiconductor element 1, and issues an output signal So of 15V which is the same as the power supply voltage Vd in the same logic state in the example of the figure. .

The gate of the semiconductor device 1 which receives the output signal So through the resistor Rg has electrostatic capacitances Cge and Cgc between its emitter and collector, respectively, and these capacitances are several hundreds to several thousand pF, respectively. Since it is a fairly large capacitance,
The drive circuit 4 is provided with sufficient drive capability for charging / discharging the gate capacitance Cg of the semiconductor element 1 that combines them in a desired short time. 3 (b) and 3 (c) show the waveforms of the input signal Si and the output signal So of the drive circuit 4, respectively.

[0005]

However, the above-mentioned FIG.
In the drive circuit 4 as shown in (a), if the drive capability is increased to increase the switching speed of the semiconductor element 1 or the turn-on time and turn-off time are shortened by decreasing the resistance value of the gate resistance Rg, the semiconductor element is turned on and off. There is a problem that transient vibration is likely to occur in the voltage applied to 1 and the current flowing through it. Below, this state is shown in FIG.
It will be explained with reference to (f).

FIG. 3D shows the waveform of the gate voltage Vg when the semiconductor device 1 receives the output signal So having the waveform shown in FIG. 3C from the drive circuit 4. Gate-emitter capacitance Cge and gate-collector capacitance Cgc related to the aforementioned gate capacitance Cg
Semiconductor device 1 during turn-on operation or turn-off operation
The waveform of the gate voltage Vg is considerably different from the simple charge / discharge waveform as shown in the figure, because it changes depending on the voltage value and current value received by.

3 (e) and 3 (f), a collector-emitter voltage Vce applied to the semiconductor element 1 and a current I flowing therethrough are shown.
Respectively are shown. As shown in FIG. 3 (e), there is no vibration in the waveform of the voltage Vce at the time of turn-on, but a large vibration appears in the waveform at the time of turn-off and a sharp peak voltage is generated. As shown in FIG. 3 (f), the waveform of the current I shows some vibration at turn-off, but large vibration appears at turn-on, and a very sharp peak current is generated.

As can be seen from the above, when the semiconductor device 1 is turned on, its current I is applied, and when it is turned off, the voltage Vce is applied.
Transient vibrations are particularly likely to occur, and the vibration amplitude tends to increase rapidly as the driving force of the drive circuit 4 increases, the resistance value of the gate resistance Rg decreases, and the load 2 inductively increases its inductance value. There is. As described above, in the actual situation, in order to increase the switching speed of the semiconductor element 1, the transient vibration that accompanies the on / off operation is a bottleneck.

In view of the above situation, an object of the present invention is to provide a drive circuit capable of increasing the switching speed as compared with the conventional one while suppressing the transient vibrations which are likely to occur at the time of turning on and off the insulated gate semiconductor device.

[0010]

According to the present invention, the above object is to provide a voltage detection signal which receives a voltage applied to a gate of a semiconductor element and switches a logic state according to a comparison result of reference values of the voltage values. A voltage detecting means for generating a voltage, a voltage dividing circuit for dividing the gate drive power supply voltage to a predetermined ratio, and a pair of transistors connected in series to the drive power supply voltage, and the logical state of the two interconnected points is an output point. The tri-state circuit is controlled in three states including the float state, and the output signal for driving the gate of the semiconductor element is derived from this output point that is commonly connected to the voltage dividing point of the voltage dividing circuit and the on / off of the semiconductor element. The logic state of the input signal is switched by using the control means that receives the designated input signal and the voltage detection signal and controls the on / off state of the transistor of the tri-state circuit according to the logic state of both signals. The time until the switching logic state of the voltage detection signal after divided is achieved by taking the partial pressure value by controlling the tristate circuit to float voltage divider circuit as an output signal by the control means.

The voltage detecting means referred to in the above configuration may be provided with operational hysteresis characteristics such that the reference value to be compared with the gate voltage value of the semiconductor element is different when the gate voltage rises and when it falls. it can. In the voltage dividing circuit, a transistor is connected in series to each of the pair of voltage dividing elements, and when the transistor in the tri-state circuit is turned on, the transistor that enters in series with that of the voltage dividing circuit is controlled to the off state. Advantageously controls the transistors that enter it in parallel to the on state. The simplest way is to configure the control means as a logic gate or a combination circuit thereof.

The voltage dividing circuit may be a single voltage dividing circuit in some cases, but it is most rational to provide it separately for the ON operation and the OFF operation of the semiconductor element so that the voltage dividing ratios thereof can be set independently. Is. Even in this case, a single tri-state circuit can be used, but a tri-state circuit can be attached to each voltage divider circuit to change the logic state of the input signal from one to the other and from the other to the one. It is advantageous to alternately control the float state by the control means in accordance with the above.

Further, in this case, a drive transistor for receiving an output signal from each of the voltage dividing circuit and the corresponding tri-state circuit is provided, and the drive transistors for ON operation and OFF operation are connected in series with the drive power supply voltage. It is advantageous to take the output signal from the interconnection point of both drive transistors for gate drive to the semiconductor element.

[0014]

In the drive circuit for the insulated gate semiconductor device according to the present invention, (1) the transient oscillation of the current or voltage due to the on / off operation of the semiconductor device is caused by the abrupt change of the gate voltage of the semiconductor device at the very early stage of the turn-on time or turn-off time. Paying attention to the point of being induced by such changes, the voltage divider circuit in the configuration of the previous section changes the gate voltage by allowing charge / discharge of the gate immediately after the start of on / off operation to proceed to the divided voltage value set by it. Suppress the speed to the extent that transient vibration is not induced, and (2) pay attention to the fact that it takes some time to charge and discharge at that time. It is set from the time when the gate voltage changes to a predetermined reference value, the control means keeps the tri-state circuit in a floating state within this time, and (3) this time elapses. After that, the control means releases the tri-state circuit from the floating state, causes the tri-state circuit to drive the gate of the semiconductor element, completes charging and discharging of the semiconductor element within a short time, and puts the semiconductor element into a regular on / off state. It has succeeded in achieving the intended purpose of.

[0015]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of the embodiment showing a drive circuit according to the present invention together with a semiconductor element and a waveform diagram of relevant main signals, and FIG. 2 is an operation characteristic diagram in the case where a voltage detecting means has an operation history. is there. In the embodiments described below, voltage dividing circuits are separately provided for turning on and off the semiconductor element, and each voltage dividing circuit has a transistor connected in series to each of the pair of voltage dividing elements. It is assumed that the tri-state circuit is provided corresponding to each voltage dividing circuit, but the present invention is not limited to this embodiment and can be implemented in various modified modes within the scope of the above-mentioned gist. .

An insulated gate semiconductor device 1 which is an IGBT, a load 2 and a diode 3 in parallel with the load 3 are shown on the right side of FIG. 1 (a).
Is the same as the case of the conventional example of FIG. 3 described above. The drive circuit according to the present invention receives an input signal Si having a waveform shown in FIG. 1 (b), and outputs an output signal So having a waveform shown in FIG. 1 (h) in the same logic state as the input signal Si in the illustrated example. The gate of the device 1 is driven without passing through the gate resistance Rg as shown in FIG.

The voltage detecting means 10, which is simply shown by a block in the center of FIG. 1A, receives the gate voltage Vg of the semiconductor element 1 which is the result of charging and discharging the gate by this output signal So,
The voltage value is compared with a predetermined reference value, and a voltage detection signal Sd whose logic state changes according to the result is generated in the waveform shown in FIG. 1 (c). When the logic state of the input signal Si in FIG. 1 (b) is switched, the output signal So or the gate voltage Vg in FIG. 1 (h) immediately starts rising or falling accordingly, but the gate of the semiconductor device 1 Since there is an electrostatic capacity and it takes some time to charge and discharge, the change in the logic state of the voltage detection signal Sd is delayed from the input signal Si by a short time shown by τp and τn in the figure as shown in Fig. 1 (c). come.

A voltage divider circuit surrounded by a chain line in FIG. 1 (a)
Reference numerals 21 and 22 are for receiving the driving power supply voltage Vd for the gate of the semiconductor element 1 and dividing it into a predetermined ratio. In some cases, it is possible to use only one, but in this embodiment, the semiconductor element 1 A voltage dividing circuit 21 for on-operation and a voltage dividing circuit 22 for off-operation are provided so that the voltage division ratios thereof can be set independently of each other. These voltage dividing circuits 21 and 22 each include a pair of voltage dividing resistors 21r and 22r as usual, but in this embodiment, p-type and n-type transistors are respectively provided for the voltage dividing resistors 21r and 22r. 21p and 21n, and 22p and 22
n are connected in series as shown.

Similarly, the tri-state circuits 31 and 32 surrounded by the one-dot chain line in FIG. 1 (a) operate not only as an inverter circuit in which the logic state of the output point switches to two states of high and low but also in the float state. This is a controlled three-state circuit. In this embodiment, a tri-state 31 for on-operation and a tri-state circuit 32 for off-operation of the semiconductor element 1 are provided corresponding to the voltage dividing circuits 21 and 22 described above. Of the voltage dividing circuits 21 and 22 are commonly connected to the corresponding voltage dividing points. Further, the output signal Sop for on operation is derived from the output point of the tri-state circuit 31, and the output signal Son for off operation is derived from the output point of the tri-state circuit 32.

The tri-state circuits 31 and 32 are p-type transistors for the driving power supply voltage Vd as shown in the figure.
31p, 32p and n-type transistors 31n, 32n are respectively connected in series, and the interconnection point of each pair of these transistors is used as an output point commonly connected to the voltage dividing points of the voltage dividing circuits 21 and 22. The control means 40, which will be described below, alternately controls the floating state for the delay times τp and τn in accordance with the change of the logic state of the input signal Si from one to the other and vice versa. It

The control means 40 of this embodiment comprises voltage dividing circuits 21 and 22.
It controls the on / off state of the transistors of the tri-state circuits 31 and 32.
It is preferable to configure the logic gate that receives Si and the voltage detection signal Sd or a combination circuit thereof, and in this embodiment, it is configured by an AND gate 41 for ON operation and an OR gate 42 for OFF operation, and a control signal that is an output thereof. S41
And S42, the input signal Si is output as it is.
The waveforms of control signals S41 and S42 are shown in FIGS. 1 (d) and 1 (e), respectively.

Now, assuming that the input signal Si in FIG. 1B changes from low to high, the voltage detection signal Sd in FIG. 1C is in a low state immediately after that, so that the AND gate of the control means 40 is operated.
The control signal S41 of FIG. 1 (d) by 41 is low, and therefore the p-type transistor 31p receiving the high of the input signal Si of the tri-state circuit 31 for ON operation and the n-type transistor receiving the low of the control signal Sd. Both 31n are turned off, and the tri-state circuit 31 enters a floating state. On the other hand, since both the p-type transistor 21p that receives the low control signal S41 and the n-type transistor 21n that receives the high input signal Si in the voltage dividing circuit 21 turn on, the on-operation shown in FIG. The output signal Sop is driven by the voltage dividing circuit 21 to drive the power supply voltage Vd.
Is the intermediate voltage Vip.

On the other hand, on the off operation side, the NOR gate
The control signal S42 of FIG. 1 (e) due to 42 becomes high at the same time as the rising of the input signal Si, and the p-type transistor 32p in the tri-state circuit 32 that receives it turns off and the input signal Si
Since the n-type transistor 32n receiving the high level is turned on, the output signal Son for the off operation shown in FIG. 1 (g), which is derived from the output point, is in the low state. The delay time τp described above
When the control signal S41 on the on-operation side becomes high after the passage of, the n-type transistor 31n of the tri-state circuit 31 is turned on, so that the output signal Sop for on-operation is switched to low.

Next, when the input signal Si changes from high to low, the control signal S41 immediately changes to low, and the tri-state circuit
Since the p-type transistor 31p in 31 is turned on when the input signal Si is high and the n-type transistor 31n is turned off when the control signal S41 is low, the output signal Sop for on-operation changes to a high state. On the other hand, the control signal S42 is still high during the delay time τn of the voltage detection signal Sd, and the tri-state circuit 32 receives the high p-type transistor 32p and the low of the input signal Si n-type. Both of the transistors 32n are turned off, so that a floating state occurs. However, the voltage divider circuit 22 is a p-type transistor that receives the high level of the input signal Si.
N-type transistor 22 receiving 22p and control signal S42 high
Since both n are turned on, the output signal Son for the off operation becomes the intermediate voltage Vin obtained by dividing the driving power supply voltage Vd. When the control signal S42 changes to low after the elapse of the delay time τn, the p-type transistor 32p of the tri-state circuit 32 turns on at that low, and the n-type transistor 32n turns off at the low of the control signal Si. The signal Son rises from the intermediate voltage Vin to the high voltage Vd.

As described above, the control means 40 floats the tri-state circuits 31 and 32 during the delay time τp or τn until the logic state of the voltage detection signal Sd is switched after the logic state of the input signal Si is switched. In this embodiment, the state is alternately controlled to output the divided voltage values of the drive power supply voltage Vd by the voltage dividing circuits 21 and 22 as the intermediate voltages Vip and Vin of the output signals Sop and Son.

When the tristate circuits 31 and 32 are made to operate in an inverter other than the floating state, the control means 40 in this embodiment turns on the transistors thereof with respect to the drive power supply voltage Vd in the voltage dividing circuits 21 and 22. Be sure to control the transistors that are connected in series to the off state and the transistors that are connected in parallel to the on state. For example, when the p-type transistor 31p of the tri-state circuit 31 is turned on by the low level of the input signal Si, the n-type transistor 21 that enters in series with the drive power supply voltage Vd of the voltage dividing circuit 21
n is turned off by the same low input signal Si, and its p-type transistor 21p is turned on by the high control signal S41. The voltage dividing circuit 21 outputs the output signal Sop generated by the tri-state 31 when the transistor 21n is turned off.
Can be set to the same high logic state as the drive power supply voltage Vd without being affected by, and it can be made even more reliable by turning on the transistor 21p.

In the circuit example of FIG. 1A, the output signal Sop for the ON operation and the output signal So for the OFF operation generated in the above-described manner in order to enhance the driving capability for the semiconductor element 1.
FIG. 1 (h) in which n is received by a p-type drive transistor 50p and an n-type drive transistor 50n which are connected in series to the drive power supply voltage Vd, and the gate of the semiconductor device 1 is driven from the interconnection point between them. ) Is configured to take out the output signal So having a waveform. p-type drive transistor 50
p is for charging the capacitance Cg of the gate of the semiconductor device 1,
The n-type drive transistor 50n is for its discharge, and of course is alternately turned on / off by both output signals Sop and Son.

This output signal So is also the gate voltage Vg applied to the semiconductor element 1, and the output signal Sop for ON operation and the output signal Son for OFF operation are respectively the aforementioned delay times τp and τn when the state of the input signal Si changes. Intermediate voltage Vip and Vin
And the gate capacitance of the semiconductor device 1
Since it takes some time to charge and discharge Cg, the waveform changes gently as compared with the output signals Sop and Son as shown in FIG. 1 (h).

The waveform of the gate voltage Vg in FIG. 1 (h) shows a reference value with which the voltage value is compared by the voltage detecting means 10. In this embodiment, the voltage detecting means 10 is shown in FIG. With such a history of operation, the reference voltage V _H when the gate voltage Vg rises and the reference voltage V _L when the gate voltage Vg fall are configured to be different. In the voltage detecting means 10, the gate voltage Vg is set to the reference voltage V _{H as} the logic state of the voltage detecting signal Sd as shown in FIG.
It is sufficient to have a normal counterclockwise history characteristic shown by an arrow in the figure so as to be changed respectively when it becomes V _L or V _L , but it is also possible to give it a clockwise history characteristic if necessary. Is. This hysteresis characteristic is, for example, a reference value V above and below 7.5V, which is half the driving power supply voltage Vd of 15V.
_It is preferable to set the difference dV between _H and V _L to be 2 to several V.

Immediately after the logic state of the input signal Si changes, the intermediate voltage Vip or Vin of the output signal Sop or Son is received by the gate and the drive transistor 50p or 50n is turned on, they operate in the saturation region and the semiconductor element 1 is operated. Since the gate capacitance Cg is charged or discharged with a substantially constant current, the gate voltage Vg rises or falls with a substantially constant slope as shown in FIG. 1 (h). This gate voltage Vg is the voltage detection circuit 10
The time until the reference voltage V _H rises is the above-mentioned delay time τp during the ON operation, and the time until the reference voltage V _L falls is the delay time τn during the OFF operation.

The procedure for setting the delay times τp and τn will be specifically described as follows. Now, let kp be the constant determined by the mobility of the channel and the capacitance of the gate oxide film of the p-type transistor 50p, the ratio of the channel width to the channel length be Wp / Lp, and its gate threshold be Vtp.
Then, the constant charging current Ip with respect to the gate capacitance Cg of the semiconductor element 1 of the drive transistor 50p when the gate receives the intermediate voltage Vip is, as is well known, Ip = (kp / 2) (Wp / Lp)
(Vip-Vtp) ² and therefore the delay time τ during ON operation
p can be set by τp = V _H Cg / Ip using the value of this charging current Ip. Similarly, the discharge current In with respect to the gate capacitance Cg by the n-type transistor 50n is a constant determined by the channel mobility and the capacitance of the gate oxide film, kn, the ratio of the channel width and the channel length is Wn / Ln, and the gate threshold value. Is Vtn, In = (kn / 2) (Wn / Ln) (Vin-Vtn) ² and the delay time during the OFF operation can be set by τn = V _L Cg / In.

In this embodiment having the above-described structure, the collector and
The waveform of the voltage Vce across the emitter is shown in FIG. 1 (i), and the waveform of the current I flowing through it is shown in FIG. 1 (j). As can be seen by comparing with the waveforms of FIG. 3 (e) and FIG. 3 (f) in the above-mentioned conventional example, in the circuit of the present invention, the waveform of the current I during the on-operation of the semiconductor element 1 and the voltage Vce at both ends during the off-operation of the semiconductor element 1 Although there is a small peak at, there is no large overcurrent or overvoltage due to transient vibration as in the past.

Further, in the circuit of the present invention, as shown in FIG.
It is not necessary to use the gate resistance Rg shown in (a), and the charging and discharging of the gate of the semiconductor element 1 can be completed within a very short time especially after the delay times τp and τn have passed. The delay time τp and τn are, of course, 0.1 depending on the case.
It is preferable to set it within the range of .about.0.5 .mu.S, whereby the turn-on time and turn-on time of the semiconductor device 1 which has conventionally required 1-2 .mu.S can be reduced to about 0.5 to 1 .mu.S.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various modes. For example, in the embodiment, all the drive circuits are configured as CMOS circuits, but they may be configured as bipolar circuits, for example. The setting of the delay time can be adjusted by the voltage dividing ratio of the voltage dividing circuit, even if the voltage detecting means does not have the history characteristic of the operation as in the embodiment. It is also possible to simplify the circuit configuration as a whole by omitting the transistor in series with the voltage dividing resistor of the voltage dividing circuit.

In the embodiment, the voltage dividing circuit for ON operation and the voltage dividing circuit for OFF operation are used. However, in order to simplify the circuit configuration, a single voltage dividing circuit is commonly provided for both operations. The corresponding tri-state circuit may be controlled by the control means to be floated during the delay time between the on-operation and the off-operation. Of course, the control means in such an embodiment can easily be configured to control the transistors in the tri-state circuit on and off in accordance with the operation required for it. Further, as can be seen from the operation waveforms of the combination of the voltage divider circuit and the tri-state circuit on the ON operation side and the OFF operation side in the embodiment, the output signal is only intermediate between the delay times of the ON operation and the OFF operation. It is also possible to implement the invention so that it is at a voltage.

[0036]

As described above, in the semiconductor element drive circuit according to the present invention, the voltage detection signal is generated and divided by the voltage detection means in accordance with the result of comparing the gate voltage of the semiconductor element with the reference voltage. The voltage supply circuit divides the drive power supply voltage for the gate of the semiconductor element to a predetermined ratio, and the tristate circuit outputs the output voltage that is commonly connected to the voltage dividing point of the voltage dividing circuit. The output signal that is controlled to the state is generated, and the on / off of the transistor in the tri-state circuit is controlled according to the logic state of the input signal that specifies the on / off of the semiconductor element and the voltage detection signal by the control means. Within the delay time after the logic state of the signal changes until the logic state of the voltage detection signal changes, the control means changes the logic state of the output point of the tri-state circuit. It may be mentioned the following effects by taking the partial pressure value of the control to the voltage divider circuit to over preparative state as an intermediate voltage value of the output signal.

(A) By placing the output signal for driving the gate of the semiconductor element at an intermediate voltage obtained by dividing the driving power supply voltage by the voltage dividing circuit within the delay time of the change of the voltage detection signal with respect to the change of the input signal, It is possible to suppress the change rate of the gate voltage so as not to induce the transient oscillation by partially advancing the charging / discharging to the intermediate voltage. (b) Use the point that it takes time to charge and discharge the electrostatic capacity of the gate of the semiconductor device, and use the voltage detection means to set the delay time to suppress the rate of change of the gate voltage until the voltage value reaches a predetermined reference value. It can be set easily and accurately from the changing time and rationally according to the capacitance value of the gate.

(C) It is not necessary to use a gate resistance as in the conventional case, and especially after a lapse of delay time, the tri-state circuit is released from the floating state and the gate is directly driven strongly to charge / discharge its capacitance. By completing the process within a short time, the turn-on time and turn-off time of the semiconductor device can be reduced to about half of the conventional one. As described above, the present invention solves the problem of the contradiction or trade-off between the suppression of the transient vibration of the voltage and the current and the increase in the switching speed which the conventional driving method using the gate resistance has.
While safely protecting semiconductor elements from overvoltage and overcurrent due to transient vibration, it is possible to expand the frequency at which the switching operation can be performed to the high-frequency region side compared to the past.

The embodiment of the present invention in which the voltage detecting means has a history characteristic in operation so that the reference voltage to be compared with the gate voltage of the semiconductor element is different when the gate voltage increases and decreases When the transient characteristics of the load are different between the ON operation and the OFF operation, there is an advantage that the changing speed of the gate voltage can be accurately set so as to surely suppress the occurrence of the transient vibration. Also, when a transistor is connected in series to each voltage dividing element of the voltage dividing circuit to turn on the transistor in the tri-state circuit, a mode of controlling the transistor which enters in series with that of the voltage dividing circuit to the off state, The mode in which the transistors in parallel are controlled to be in the ON state has the effect of increasing the gate driving force and increasing the switching speed of the semiconductor element. A mode in which the control means is configured by a logic gate or a combination thereof is
It has the advantage that the operations of the tri-state circuit and the voltage dividing circuit can be accurately controlled with a simple circuit configuration.

The mode in which the voltage dividing circuit is separately provided for the ON operation and the OFF operation to independently set the voltage dividing ratio, and the mode in which the tristate circuit is provided for each voltage dividing circuit surely prevents the transient vibration. As described above, there is an effect that the changing speed of the gate voltage during the on-operation and the off-operation of the semiconductor element can be independently set according to the characteristics. A driving transistor is provided for each combination of a voltage dividing circuit for ON operation and an OFF operation and a tri-state circuit, and an output signal is derived from an interconnection point of both driving transistors to drive a gate of a semiconductor element. This has the effects of charging / discharging the gate to an intermediate voltage value with a constant saturation current of the transistor to accurately set the delay time and increasing the driving force for the gate to increase the switching speed of the semiconductor device.

[Brief description of drawings]

FIG. 1 shows waveforms of main signals related to an embodiment circuit of a semiconductor element drive circuit according to the present invention. FIG. 1 (a) is a circuit diagram showing the drive circuit together with a semiconductor element, and FIG. Input signal waveform diagram, Figure (c) shows voltage detection signal waveform diagram.
(d) is a waveform diagram of the control signal for ON operation, (e) is a waveform diagram of the control signal for OFF operation, (f) is a waveform diagram of the output signal for ON operation, and (g) is the same. ) Is a waveform diagram of the output signal for OFF operation, (h) is a waveform diagram of the output signal for driving the semiconductor element,
Figure (i) is a waveform diagram of the voltage across the semiconductor element.
(j) is a waveform diagram of the current flowing through the semiconductor element.

FIG. 2 is an operation characteristic diagram of a voltage detection unit having an operation history.

3A and 3B show main signal waveforms related to an example of a conventional drive circuit, FIG. 3A is a circuit diagram showing a drive circuit together with a semiconductor element, and FIG. 3B is a waveform diagram of an input signal. Figure (c) is the waveform diagram of the output signal, (d) is the waveform diagram of the gate voltage of the semiconductor element, (e) is the waveform diagram of the voltage across the semiconductor element, and (f) is the semiconductor element. It is a wave form diagram of the electric current which flows into.

[Explanation of symbols]

1 Insulated gate semiconductor element or IGBT 2 Load of semiconductor element 10 Voltage detection means 21 Voltage dividing circuit for ON operation 21r Voltage dividing resistor 21p, 21n Transistor in series with voltage dividing resistor 22 Voltage dividing circuit for OFF operation 22r Voltage dividing resistor 22p, 22n Transistor in series with voltage dividing resistor 31 Tri-state circuit for ON operation 31p, 31n Tri-state circuit transistor 32 Off-state tri-state circuit 32p, 32n Tri-state circuit transistor 40 Control means 41 Control means AND gate 42 OR gate for control means 50p, 50n Drive transistor Cg Capacitance of gate of semiconductor element I Current flowing in semiconductor element Sd Voltage detection signal Si input signal So Output signal for driving semiconductor element Son Output signal for off operation Sop output signal for ON operation S41 control signal for ON operation S42 control signal for OFF operation τn voltage detection signal during OFF operation Signal delay time τp Delay time of voltage detection signal during ON operation V Power supply voltage for load Vce Voltage across semiconductor device Vd Drive power supply voltage for semiconductor device gate Vg Gate voltage for semiconductor device Vin Output signal for OFF operation Intermediate voltage Vip Intermediate voltage of output signal for ON operation V _H Reference voltage when gate voltage of voltage detecting means is rising _VL Reference voltage when gate voltage of voltage detecting means is falling

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Claims (7)

[Claims] 1. A voltage detection means for receiving a voltage applied to a gate of a semiconductor element and issuing a voltage detection signal whose logic state is switched according to a result of comparison with a reference value, and a driving power supply voltage for the gate are predetermined. A voltage divider circuit that divides the voltage into a ratio and a pair of transistors connected in series to the drive power supply voltage.
An output signal for gate drive of the semiconductor device is derived from the output point which is commonly connected to the voltage dividing point of the voltage dividing circuit and whose logical state is controlled to three states including the float state by using the mutual connecting point of the both as an output point. And a control unit that receives an input signal designating on / off of the semiconductor element and a voltage detection signal and controls the on / off state of the transistor of the tristate circuit according to the logical states of both signals. During the time until the logic state of the voltage detection signal changes after the logic state of the signal is switched, the tri-state circuit is controlled to the floating state by the control means so that the divided voltage of the voltage divider circuit is taken out as the output signal. A drive circuit for an insulated gate semiconductor device characterized by the above. 2. A drive circuit for an insulated gate semiconductor device according to claim 1, wherein the control means is configured as a logic gate or a combination circuit thereof. 3. The circuit according to claim 1, wherein a transistor is connected in series to each of the pair of voltage dividing elements of the voltage dividing circuit, and the voltage dividing circuit is turned on when the transistor in the tristate circuit is turned on. A drive circuit for an insulated gate semiconductor device, characterized in that a transistor connected in series with the control circuit is controlled to an off state. 4. The circuit according to claim 1, wherein a voltage dividing circuit is provided separately for the ON operation and the OFF operation of the semiconductor element, and the voltage dividing ratios thereof can be set independently. And a drive circuit for an insulated gate semiconductor device. 5. A circuit according to claim 4, wherein a tri-state circuit is provided for each voltage dividing circuit, and control is performed in response to a change in the logical state of the input signal from one side to the other side and a change from the other side to the one side. A driving circuit for an insulated gate semiconductor device, characterized in that the driving circuit alternately controls the floating state by means. 6. The circuit according to claim 5, wherein a drive transistor for receiving an output signal from both voltage dividing circuits and a corresponding tri-state circuit is provided for each of the ON operation and the OFF operation. A drive circuit for an insulated gate semiconductor device, wherein a drive transistor is connected in series to a drive power supply voltage, and an output signal for driving a gate of the semiconductor device is derived from an interconnection point of both drive transistors. 7. The circuit according to claim 1, wherein the reference voltage for comparing the gate voltage values of the semiconductor elements of the voltage detecting means is different when the gate voltage is increasing and when the gate voltage is decreasing. A drive circuit for an insulated gate semiconductor device, characterized in that the drive circuit is provided.