JP2001223571A - Gate driving device for voltage driving-type semiconductor element - Google Patents
Gate driving device for voltage driving-type semiconductor elementInfo
- Publication number
- JP2001223571A JP2001223571A JP2000033721A JP2000033721A JP2001223571A JP 2001223571 A JP2001223571 A JP 2001223571A JP 2000033721 A JP2000033721 A JP 2000033721A JP 2000033721 A JP2000033721 A JP 2000033721A JP 2001223571 A JP2001223571 A JP 2001223571A
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- Japan
- Prior art keywords
- voltage
- gate
- switching means
- output
- driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Power Conversion In General (AREA)
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、モータ制御、エア
コン等のインバータあるいはNC制御などに使用される
電力変換装置を構成するIGBT,MOSFET等の電
圧駆動型半導体素子のゲート駆動装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive device for a voltage-driven semiconductor device such as an IGBT or MOSFET which constitutes a power conversion device used for inverter control or NC control of a motor control, an air conditioner or the like.
【0002】[0002]
【従来の技術】半導体素子を用いた電力変換装置におい
ては、近年、種々の法的規制から該電力変換装置を構成
する前記電圧駆動型半導体素子のスイッチング動作に伴
って発生するノイズを低減させることが求められてい
る。図4はこの種の電力変換装置の従来例を示す回路構
成図である。図4において、1はこの電力変換装置の電
圧駆動型半導体素子としてのIGBT、2はモータ等の
誘導性負荷を示し、主回路電源VMからIGBT1のオ
ン・オフに基づいて誘導性負荷2に電力が供給される。
実際のインバータ回路では、このIGBT1が2個直列
接続された直列回路を3個並列接続にし、かつ各直列回
路の中点を出力としてモータ等の誘導性負荷に接続され
る。このIGBT1をオン・オフさせる駆動回路には、
駆動回路電源VDDと基準電位点(IGBT1のエミッ
タ電位あるいは接地電位)との間に直列接続されるPチ
ャネルのMOSFET11及びNチャネルのMOSFE
T12と、駆動信号に基づいてMOSFET11,12
を制御する反転素子21a〜21eからなる制御回路と
を備えている。3はゲート抵抗である。PチャネルのM
OSFET11側とNチャネルのMOSFET12側と
の反転素子の段数が異なるのは同時にMOSFET1
1,12がオン状態となり短絡するのを防ぐための時間
的なずれを持たせたためである。この回路では、MOS
FET11,12を低オン抵抗の素子を選定して用い、
IGBT1の駆動能力を高く設定し、ゲート抵抗3の値
を調整して前記駆動能力より低く使用できるようにして
いる。かかる回路において、回路構成は簡単であるが、
IGBT1のスイッチング動作を早くすると、ターンオ
ン・ターンオフ時のIGBT1のコレクタ電流Ic及び
コレクタ−エミッタ電圧VCEの変化が急峻となり、コ
レクタ電流Icに振動現象が生じノイズが発生すること
となる。なお、本発明は電圧駆動型半導体素子のゲート
駆動装置に特徴を有するものであるので、以後主スイッ
チング素子であるIGBT1を1つだけ記載して説明を
行っている。前記図4におけるノイズの低減手段として
図5の回路を提供した。図5は異なる従来例を示す回路
構成図であり、類似した回路を出願し公開(特開平9―
47015号、特開平10―32976号、特開平11
―97994号)した。図5において、M1はオン抵抗
が低いPチャネルMOSFETであり、M2はオン抵抗
が高いNチャネルMOSFETであり、M3はオン抵抗
が低いNチャネルMOSFETであり、M4はオン抵抗
が高いPチャネルMOSFETであり、M5はM3より
更にオン抵抗の低いNチャネルMOSFETである。そ
して、MOSFETM1,M2が並列接続され、MOS
FETM3,M4,M5が並列接続され、更にこれらの
並列接続されたMOSFETM1,M2の一端とMOSFET
M3,M4,M5の一端とが直列に接続される。MOS
FETM1,M2の他端は駆動回路電源VDDに接続さ
れ、MOSFETM3,M4,M5の他端は基準電位点(IG
BT1のエミッタ電位あるいは接地電位)に接続され
る。この直列接続された中点がIGBT1のゲートに接
続される。各MOSFETM1〜M5のゲートはプリド
ライバを介して駆動信号により個々に制御される。コレ
クタ電流ICが50AのIGBT1を駆動する場合に各
MOSFETのオン抵抗は、MOSFETM3が17
Ω、M4が220Ω、M5が2Ω、M1,M2が両者オ
ンした状態で34Ωに設定される。2. Description of the Related Art In recent years, in a power conversion device using a semiconductor device, it has been required to reduce noise generated due to a switching operation of the voltage-driven semiconductor device constituting the power conversion device due to various legal regulations. Is required. FIG. 4 is a circuit configuration diagram showing a conventional example of this type of power converter. In FIG. 4, reference numeral 1 denotes an IGBT as a voltage-driven semiconductor element of the power converter, and 2 denotes an inductive load such as a motor, and power is supplied from the main circuit power supply VM to the inductive load 2 based on ON / OFF of the IGBT 1. Is supplied.
In an actual inverter circuit, three series circuits in which two IGBTs 1 are connected in series are connected in parallel, and the midpoint of each series circuit is connected to an inductive load such as a motor as an output. The driving circuit for turning on / off the IGBT 1 includes:
P-channel MOSFET 11 and N-channel MOSFET connected in series between drive circuit power supply VDD and a reference potential point (emitter potential or ground potential of IGBT 1)
T12 and MOSFETs 11, 12 based on the drive signal.
And a control circuit including inverting elements 21a to 21e for controlling 3 is a gate resistance. M for P channel
The number of inverting elements on the OSFET 11 side and the N-channel MOSFET 12 side is different at the same time
This is because there is a time lag for preventing the short circuits 1 and 12 from being turned on. In this circuit, MOS
FETs 11 and 12 are used by selecting low on-resistance elements,
The driving capability of the IGBT 1 is set high, and the value of the gate resistor 3 is adjusted so that the IGBT 1 can be used at a lower driving capability. In such a circuit, the circuit configuration is simple,
When the switching operation of the IGBT 1 is accelerated, the change of the collector current Ic and the collector-emitter voltage VCE of the IGBT 1 at the time of turn-on and turn-off becomes steep, so that the collector current Ic causes an oscillation phenomenon to generate noise. It should be noted that the present invention is characterized by a gate drive device for a voltage-driven semiconductor device, and therefore, the following description is given by describing only one IGBT 1 as a main switching device. The circuit of FIG. 5 is provided as a means for reducing the noise in FIG. FIG. 5 is a circuit configuration diagram showing a different conventional example.
No. 47015, JP-A-10-32976, JP-A-11
No. 97994). In FIG. 5, M1 is a P-channel MOSFET having a low on-resistance, M2 is an N-channel MOSFET having a high on-resistance, M3 is an N-channel MOSFET having a low on-resistance, and M4 is a P-channel MOSFET having a high on-resistance. M5 is an N-channel MOSFET having a lower on-resistance than M3. Then, the MOSFETs M1 and M2 are connected in parallel,
FETs M3, M4, and M5 are connected in parallel, and one end of these parallel-connected MOSFETs M1 and M2 is
One end of M3, M4, M5 is connected in series. MOS
The other ends of the FETs M1 and M2 are connected to the drive circuit power supply VDD, and the other ends of the MOSFETs M3, M4 and M5 are connected to a reference potential point (IG
BT1 (emitter potential or ground potential). This series connected midpoint is connected to the gate of IGBT1. The gates of the MOSFETs M1 to M5 are individually controlled by drive signals via a pre-driver. When the collector current IC drives the IGBT 1 of 50 A, the ON resistance of each MOSFET is 17
Ω, M4 is set to 220 Ω, M5 is set to 2 Ω, and M1 and M2 are set to 34 Ω with both turned on.
【0003】[0003]
【発明が解決しようとする課題】前記図5の駆動回路で
は、駆動信号に応じてプリドライバから出力される信号
により、各MOSFETのオンするタイミング(詳細は
後述する)を変化させて過渡的にオン抵抗を変化させて
駆動能力を変え(駆動能力高いと低損失と低スイッチン
グロス、駆動能力が低いと低ノイズ)低損失と低ノイズ
を達成している。しかしながら、この駆動回路では、各
MOSFETのオン抵抗によって駆動対象であるIGB
T1に対する駆動能力が決められるので、IGBT1の
機種毎にあわせて各MOSFETのオン抵抗を設定せね
ばならなかった。また、この図5の駆動回路において、
図4の如くゲート抵抗3を用いて駆動能力を変更しよう
とした場合に、MOSFETM1とM2の各オン抵抗が
例えば100Ωと1KΩというようにかなり異なるた
め、ゲート抵抗3が入ることで、オン抵抗の比がくるっ
てしまうので単純にゲート抵抗3を付けることはできな
い。図6は図5の駆動能力を変えるための回路構成図で
ある。図6において、図5と異なる点はMOSFETM
1〜M5の一端を連結せずにそれぞれ引き出し、異なる
抵抗値のゲート抵抗3a〜3eを介してIGBT1に接
続した点である。この回路構成ではゲート抵抗の値を個
々に設定することにより駆動能力を任意に設定できる。
しかし、通常この駆動回路はICとして形成されるが、
個々のゲート抵抗に接続するためにICのピン数が増え
ることとゲート抵抗も端子分必要となりコストアップと
なる。In the drive circuit shown in FIG. 5, the timing at which each MOSFET is turned on (details will be described later) is changed by a signal output from the pre-driver in response to the drive signal, and the drive circuit is transiently driven. The drive capability is changed by changing the on-resistance (high drive capability results in low loss and low switching loss, and low drive capability results in low noise) to achieve low loss and low noise. However, in this drive circuit, the IGB to be driven is controlled by the ON resistance of each MOSFET.
Since the driving capability for T1 is determined, the on-resistance of each MOSFET must be set according to the type of IGBT1. In the drive circuit of FIG.
When it is attempted to change the driving capability using the gate resistor 3 as shown in FIG. 4, the on-resistances of the MOSFETs M1 and M2 are considerably different, for example, 100Ω and 1KΩ. Since the ratio is increased, it is not possible to simply add the gate resistor 3. FIG. 6 is a circuit configuration diagram for changing the driving capability of FIG. FIG. 6 is different from FIG.
1 to M5 are connected to the IGBT 1 via gate resistors 3a to 3e having different resistance values, respectively. In this circuit configuration, the driving capability can be arbitrarily set by individually setting the values of the gate resistors.
However, although this drive circuit is usually formed as an IC,
The number of pins of the IC is increased to connect to each gate resistor, and the gate resistor is required for the terminals, resulting in an increase in cost.
【0004】本発明の目的は、主回路の電圧駆動型素子
を低損失で低ノイズな駆動が可能な駆動回路を安価に提
供することである。An object of the present invention is to provide a low-cost drive circuit capable of driving a voltage-driven element of a main circuit with low loss and low noise.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、駆動信号のオン指令に基づいて電圧駆
動型半導体素子(IGBT1)のゲートへオン用電圧を
オン用の第1スイッチング手段(M1,M2)を介して
印加し、オフ指令に基づいてオフ用の第2スイッチング
手段(M3,M4)を介してゲートの電圧を引き抜くゲ
ート駆動装置において、前記オン用の第1スイッチング
手段とオフ用の第2スイッチング手段からなる出力段ユ
ニットが複数(出力段1〜3、1a〜3a)あり、該複
数の出力段ユニットの入力側端子(A〜E)が並列に接
続され、出力側端子(出力信号)が独立して設けられ1
つの電圧駆動型半導体素子(IGBT1)に対して該出
力側端子が任意に接続されることが有効である。また、
オン用の第1スイッチング手段がPチャネルMOSFE
T(M1)とNチャネルMOSFET(M2)との並列
接続回路であり、オフ用の第2スイッチング手段がPチ
ャネルMOSFET(M4)とNチャネルMOSFET
(M3)との並列接続回路であることが有効である。P
チャネルMOSFET(M1、M4)はオン抵抗が高
く、NチャネルMOSFET(M2、M3)はオン抵抗
が低くする。また、ゲート駆動装置がICであり、オフ
用の第2スイッチング手段のNチャネルMOSFETよ
りも低いオン抵抗のNチャネルMOSFET(M5)を
前記IGBT1のゲートと基準電位との間に設けること
が有効である。複数の出力段ユニットの出力端子の出力
値は異なっている。In order to achieve the above object, the present invention provides a first method for turning on an on-state voltage to a gate of a voltage-driven semiconductor device (IGBT1) based on an on-command of a drive signal. In the gate drive device, which is applied through the switching means (M1, M2) and pulls out the gate voltage via the second switching means for turning off (M3, M4) based on the off command, the first switching for turning on is performed. There are a plurality of output stage units (output stages 1 to 3 and 1a to 3a) each of which comprises a switch and a second switching unit for turning off, and the input terminals (A to E) of the plurality of output stage units are connected in parallel, The output side terminal (output signal) is provided independently.
It is effective that the output side terminal is arbitrarily connected to one voltage-driven semiconductor element (IGBT1). Also,
The first switching means for turning on is a P-channel MOSFET.
T (M1) is a parallel connection circuit of an N-channel MOSFET (M2), and the second switching means for turning off is a P-channel MOSFET (M4) and an N-channel MOSFET
It is effective that the circuit is connected in parallel with (M3). P
The channel MOSFETs (M1, M4) have a high on-resistance, and the N-channel MOSFETs (M2, M3) have a low on-resistance. Further, it is effective to provide an N-channel MOSFET (M5) having an on-resistance lower than the N-channel MOSFET of the second switching means for turning off between the gate of the IGBT1 and the reference potential. is there. The output values of the output terminals of the plurality of output stage units are different.
【0006】本発明によれば、出力段ユニットの出力端
子が引き出されたICの端子を任意に接続することによ
り、低損失、低ノイズを損なうことなくICによる駆動
能力が簡単に変えることができる。According to the present invention, by arbitrarily connecting the terminal of the IC from which the output terminal of the output stage unit is drawn out, the driving capability of the IC can be easily changed without impairing low loss and low noise. .
【0007】[0007]
【発明の実施の形態】図1は、本発明の第1の実施例を
示す電力変換装置の回路構成図であり(a)は駆動回路
図であり(b)は(a)の出力段1の部分拡大図であ
り、図5に示した従来例回路と同一機能を有するものに
は同一符号を付している。すなわち図1において、出力
段1〜3からなるユニットがIC内において並列に接続
されている。これら出力段1〜3の回路構成は(b)に
示すようになっており、図5のMOSFETM1〜M5
と同じ回路構成となっている。但し、出力段1〜3での
各MOSFETM1〜M5のオン抵抗は異なるものを採
用しており、出力段1〜3の出力信号が異なる駆動能力
となっている。まず、図1(b)の部分拡大図の動作を
図2に示す動作波形図を参照しつつ、以下に説明する。
なお、図2の動作波形を具現するためのMOSFETM
1〜M5の選定条件は、図5におけるオン抵抗の選定条
件と同じとしている。まず、プリドライバを介して駆動
信号(図2(f)参照)が図示の如くオフからオン(T
1時点)に変化してIGBT1にオン指令が発せられる
と、M1の端子Aの信号はハイからロー(図2(a)参
照)へ変わり、M2の端子Bの信号はローからハイ(図
2(b)参照)に変わりM1,M2はオフ状態からオン
状態となる。このオン状態の時にM3〜M5はオフ状態
とされる(図2(c)〜(e)参照)。その結果IGB
T1は駆動回路電源VGGからM1,M2を介してのゲ
ート電圧でオン状態となり、IGBT1のゲート電圧V
Gは急速に立ち上がり、IGBT1の閾値VG1を越え
て平坦期間(IGBT1のミラー容量充電期間)に入り
つつ、IGBT1がターンオン動作を開始する。このミ
ラー容量充電期間は、M2をT2時点でオフさせること
でT1〜T2時点の間のゲート容量充電にM1,M2が
寄与してこの時間の短縮が図られる。その後、IGBT
1のゲート電圧(図2(g)参照)がVG1に近づくに
つれてM2のゲート・ソース電圧はM2の閾値に近づき
オフするため、IGBT1のゲート電圧がVG1以上の
領域ではM1のみがオン状態になり、その結果、図示の
如くIGBT1のゲート電圧VGのdV/dtが小さく
なり、IGBT1のコレクタ電流Ic(図示せず)及び
コレクタ・エミッタ電圧VCE(図2(h)参照)の変
化が緩やかになる。次に、駆動信号がオンからオフに変
化(T3時点)してIGBT1にオフ指令が発せられる
と、M3〜M5はオフ状態からオン状態となる。このオ
ン状態の時にM1,M2はオフ状態とされる。その結
果、IGBT1のゲート電圧VGEは急速に立ち下が
り、平坦期間(IGBT1のミラー容量放電期間)を若
干残しつつ、IGBT1がターンオフ動作を開始する。
このミラー容量放電期間は、M5をT4時点でオフさせ
ることにより短縮することができ、一旦M3、M4のみ
がオン状態となり、その結果、図示の如くIGBT1の
ゲート電圧VGのdV/dtが小さくなり、IGBT1
のコレクタ電流Ic及びコレクタ・エミッタ電圧VCE
の変化が緩やかになる。なお、T5時点でゲート電圧が
VG2(約5V)まで下降すると再びM5をオンさせて
M3〜M5をオン状態としてゲート電圧VGの下降を速
め、IGBT1のターンオフ時間を短縮してオフ保持さ
せる。再び図1にもどり、出力段1〜3は、各MOSF
ETのオン抵抗を変えるだけでよいので、IC内で容易
に実現が可能である。この出力段1〜3の出力信号を出
力すべく出力端子はこの例では3つとなり、ICのピン
数が2つ増えるが、例えば、この出力端子をコレクタ電
流Icが25A,50A,75AとすればIGBT1へ
の接続ピンを組み合わせることで7種類の駆動能力を実
現できる。そして、出力段ユニットを4個とすれば15
種類の駆動能力が実現できる。これらにおいて、外付け
のゲート抵抗を図6のように個々に設ける必要がないの
で部品数を増やすこともない。図3は異なる実施例であ
り、(a)は駆動回路図であり、(b)は(a)の出力
段1aの部分拡大図である。図3において図1と異なる
点は、出力段1〜3のそれぞれに設けられていたMOS
FETM5を取出して独立してM5を設けた点である。
このM5はシンカーと呼ばれ、駆動対象であるIGBT
1をオフに保持するためのオン抵抗が低抵抗のトランジ
スタである。この場合、IGBT1のゲートが低抵抗で
基準電位(接地)に落ちていればよいので、駆動対象毎
に駆動能力を変えなくてもよい。従って、各出力段のM
5を統合して1つの出力端子としている。この出力端子
はゲートの電圧を検出するための端子としてもよい。以
上のように本発明では、各MOSFETのオン抵抗を変
える手段にて説明したが、各MOSFETに拡散抵抗あ
るいはポリシリコンの抵抗を直列に介挿して抵抗値を設
定してもよい。FIG. 1 is a circuit diagram of a power converter showing a first embodiment of the present invention. FIG. 1 (a) is a drive circuit diagram, and FIG. 1 (b) is an output stage 1 of FIG. 5 is a partially enlarged view, and the same reference numerals are given to those having the same functions as those of the conventional circuit shown in FIG. That is, in FIG. 1, units including output stages 1 to 3 are connected in parallel in the IC. The circuit configuration of these output stages 1 to 3 is as shown in FIG.
It has the same circuit configuration as that of FIG. However, the ON resistances of the MOSFETs M1 to M5 in the output stages 1 to 3 are different, and the output signals of the output stages 1 to 3 have different driving capabilities. First, the operation of the partially enlarged view of FIG. 1B will be described below with reference to the operation waveform diagram shown in FIG.
A MOSFET M for realizing the operation waveform of FIG.
The selection conditions of 1 to M5 are the same as the selection conditions of the on-resistance in FIG. First, a drive signal (see FIG. 2 (f)) is turned on from off to on (T
When the ON command is issued to the IGBT 1 at one point in time, the signal at the terminal A of M1 changes from high to low (see FIG. 2A), and the signal at the terminal B of M2 changes from low to high (see FIG. 2). (See (b)), and M1 and M2 change from the off state to the on state. During this on state, M3 to M5 are turned off (see FIGS. 2C to 2E). As a result IGB
T1 is turned on by the gate voltage from the driving circuit power supply VGG via M1 and M2, and the gate voltage V of the IGBT1 is
G rises rapidly, and the IGBT 1 starts a turn-on operation while exceeding a threshold VG 1 of the IGBT 1 and entering a flat period (a mirror capacitor charging period of the IGBT 1). In this Miller capacitance charging period, M1 is turned off at the time T2, and M1 and M2 contribute to the gate capacitance charging between the times T1 and T2, so that the time is shortened. Then, IGBT
As the gate voltage of 1 (see FIG. 2 (g)) approaches VG1, the gate-source voltage of M2 approaches the threshold value of M2 and turns off. Therefore, in the region where the gate voltage of IGBT1 is equal to or higher than VG1, only M1 turns on. As a result, as shown in the figure, dV / dt of the gate voltage VG of the IGBT 1 decreases, and the changes in the collector current Ic (not shown) and the collector-emitter voltage VCE (see FIG. 2 (h)) of the IGBT 1 become gentle. . Next, when the drive signal changes from on to off (at time T3) and an off command is issued to the IGBT 1, M3 to M5 change from off to on. During this ON state, M1 and M2 are turned OFF. As a result, the gate voltage VGE of the IGBT 1 rapidly falls, and the IGBT 1 starts a turn-off operation while slightly leaving a flat period (a mirror capacitance discharging period of the IGBT 1).
This Miller capacitance discharge period can be shortened by turning off M5 at the time of T4, and only M3 and M4 are once turned on. As a result, dV / dt of the gate voltage VG of the IGBT1 decreases as shown in the figure. , IGBT1
Collector current Ic and collector-emitter voltage VCE
Changes slowly. When the gate voltage drops to VG2 (about 5 V) at time T5, M5 is turned on again, M3 to M5 are turned on, the drop of the gate voltage VG is accelerated, and the turn-off time of the IGBT1 is shortened and held off. Returning to FIG. 1 again, the output stages 1 to 3
Since it is only necessary to change the on-resistance of the ET, it can be easily realized in the IC. In this example, three output terminals are provided to output the output signals of the output stages 1 to 3, and the number of pins of the IC is increased by two. For example, when the collector current Ic is 25 A, 50 A, and 75 A, the output terminals are changed. For example, seven types of driving capabilities can be realized by combining the connection pins to the IGBT1. And if there are four output stage units, 15
Different driving capabilities can be realized. In these, it is not necessary to provide external gate resistors individually as shown in FIG. 6, so that the number of components is not increased. 3A and 3B show different embodiments, in which FIG. 3A is a drive circuit diagram, and FIG. 3B is a partially enlarged view of the output stage 1a of FIG. 3 is different from FIG. 1 in that the MOSs provided in each of output stages 1 to 3 are provided.
The point is that FET M5 is taken out and M5 is provided independently.
This M5 is called a sinker and is an IGBT to be driven.
1 is a transistor having a low on-resistance for holding 1 off. In this case, since the gate of the IGBT 1 only needs to have a low resistance and fall to the reference potential (ground), the driving capability does not have to be changed for each driving target. Therefore, M of each output stage
5 are integrated into one output terminal. This output terminal may be a terminal for detecting the voltage of the gate. As described above, in the present invention, the means for changing the ON resistance of each MOSFET has been described. However, a resistance value may be set by inserting a diffusion resistance or a polysilicon resistance in each MOSFET in series.
【0008】[0008]
【発明の効果】本発明によれば、主回路の電圧駆動型素
子を低損失で低ノイズな駆動が可能でしかも駆動能力が
任意に変えられる駆動回路を安価に提供することができ
る。According to the present invention, it is possible to provide an inexpensive drive circuit capable of driving the voltage drive type element of the main circuit with low loss and low noise and capable of arbitrarily changing the drive capability.
【図1】本発明の実施例を示す回路構成図であり、
(a)は駆動回路図、(b)は(a)の部分拡大図FIG. 1 is a circuit diagram showing an embodiment of the present invention;
(A) is a drive circuit diagram, (b) is a partially enlarged view of (a).
【図2】図1の動作を説明する波形図FIG. 2 is a waveform chart illustrating the operation of FIG.
【図3】本発明の他の実施例を示す回路構成図であり、
(a)は駆動回路図、(b)は(a)の部分拡大図FIG. 3 is a circuit diagram showing another embodiment of the present invention;
(A) is a drive circuit diagram, (b) is a partially enlarged view of (a).
【図4】従来例を示す回路構成図FIG. 4 is a circuit configuration diagram showing a conventional example.
【図5】他の従来例を示す回路構成図FIG. 5 is a circuit diagram showing another conventional example.
【図6】参考例を示す回路構成図FIG. 6 is a circuit diagram showing a reference example.
1 IGBT 2 誘導性負荷 11、 12、M1〜M5 MOSFET 21a〜21e 反転素子 3、3a〜3e ゲート抵抗 DESCRIPTION OF SYMBOLS 1 IGBT 2 Inductive load 11, 12, M1-M5 MOSFET 21a-21e Inverting element 3, 3a-3e Gate resistance
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5H740 BA11 BA12 BB10 HH05 KK01 5J055 AX08 AX12 AX25 AX44 AX65 BX16 BX18 CX07 CX13 CX20 DX09 DX13 DX14 DX22 DX55 DX56 DX73 DX83 GX01 GX02 GX04 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H740 BA11 BA12 BB10 HH05 KK01 5J055 AX08 AX12 AX25 AX44 AX65 BX16 BX18 CX07 CX13 CX20 DX09 DX13 DX14 DX22 DX55 DX56 DX73 DX83 GX01 GX02 GX04
Claims (6)
半導体素子のゲートへオン用電圧をオン用の第1スイッ
チング手段を介して印加し、オフ指令に基づいてオフ用
の第2スイッチング手段を介してゲートの電圧を引き抜
くゲート駆動装置において、前記オン用の第1スイッチ
ング手段とオフ用の第2スイッチング手段からなる出力
段ユニットが複数あり、該複数の出力段ユニットの入力
側端子が並列に接続され、出力側端子が独立して設けら
れ1つの電圧駆動型半導体素子に対して該出力側端子が
任意に接続されることを特徴とする電圧駆動型半導体素
子のゲート駆動装置。An on-state voltage is applied to a gate of a voltage-driven semiconductor device via a first on-state switching means based on an on-command of a drive signal, and a second off-state switching means is provided based on an off instruction. In the gate driving device for extracting the voltage of the gate through the gate driver, there are a plurality of output stage units including the first switching means for turning on and the second switching means for turning off, and the input terminals of the plurality of output stage units are connected in parallel. Wherein the output side terminal is provided independently and the output side terminal is arbitrarily connected to one voltage driven type semiconductor element.
ルMOSFETとNチャネルMOSFETとの並列接続
回路であり、オフ用の第2スイッチング手段がPチャネ
ルMOSFETとNチャネルMOSFETとの並列接続
回路である請求項1記載の電圧駆動型半導体素子のゲー
ト駆動装置。2. The first switching means for turning on is a parallel connection circuit of a P-channel MOSFET and an N-channel MOSFET, and the second switching means for turning off is a parallel connection circuit of a P-channel MOSFET and an N-channel MOSFET. A gate driving device for a voltage-driven semiconductor device according to claim 1.
く、NチャネルMOSFETはオン抵抗が低い請求項2
記載の電圧駆動型半導体素子のゲート駆動装置。3. The P-channel MOSFET has a high on-resistance and the N-channel MOSFET has a low on-resistance.
A gate drive device for a voltage-driven semiconductor device according to claim 1.
の電圧駆動型半導体素子のゲート駆動装置。4. The gate drive device for a voltage-driven semiconductor device according to claim 2, wherein the gate drive device is an IC.
ルMOSFETよりも低いオン抵抗のNチャネルMOS
FETを前記ゲートと基準電位との間に設けた請求項2
記載の電圧駆動型半導体素子のゲート駆動装置。5. An N-channel MOS having an on-resistance lower than that of an N-channel MOSFET of a second switching means for turning off.
3. An FET provided between the gate and a reference potential.
A gate drive device for a voltage-driven semiconductor device according to claim 1.
が異なる請求項1記載の電圧駆動型半導体素子のゲート
駆動装置。6. The gate drive device for a voltage-driven semiconductor device according to claim 1, wherein output values of output terminals of the plurality of output stage units are different.
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JP2000033721A JP2001223571A (en) | 2000-02-10 | 2000-02-10 | Gate driving device for voltage driving-type semiconductor element |
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