JPH0970053A - Signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the signal processing unit in which an image inversion function is realized at a low cost without the need for addition of a comparatively large scale circuit such as a line memory. SOLUTION: In the case of reading image data in the unit of 8 samples from frame memories 33a, 33b of a RAM 33 in the image inversion mode, the address is controlled in reverse direction to that in the normal reproduction state as to a horizontal line direction. Furthermore, as to a Y signal component in the unit of 8 samples read from the RAM 33, an image inversion circuit 34 applies rearrangement processing to the component so as to reverse the arrangement of the data by 8 samples and the result is fed to a de-blocking/de- shuffling circuit 29. Moreover, as to Cr(R-B) and Cb(B-Y) signal components in the unit of 8 samples read from the RAM 33, write addresses in a buffer circuit 29a are reverse to that in the usual reproduction to reverse the arrangement of data in the unit of 8 samples.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for processing image signal data, for example,
The present invention relates to a signal processing device suitable for mounting on a digital video tape recorder or the like.

[0002]

2. Description of the Related Art In recent years, video tape recorders (hereinafter referred to as VT) have been developed.
(Abbreviated as R), the captured image signal is converted into a digital signal and recorded / recorded on a recording medium such as a magnetic tape.
A digital VTR designed for reproduction is considered. In such a digital VTR, in general, when a color video signal is directly converted to a digital signal and recording / reproducing is performed, the amount of data to be handled becomes enormous, so that an image converted into a digital signal is generated. It has been considered to encode the signal data to compress the transmission data amount.

Further, in such a digital VTR, various special reproductions can be realized relatively easily because the image signal is treated as digital data. For example, as one of such special reproductions. A display function of a left-right reversed image in which the left-right of the original image is reversed can be considered. Then, as one method of realizing such a horizontal inversion function of an image, it is conceivable to provide a line memory for one line (scanning line), for example. Then, the decoded image data signal is once written in this line memory, and address control is performed so that the read operation is the reverse of the write operation. As a result, the right and left of the image are reversed for each line, and it is possible to display an image in a state where the original image is viewed through a mirror, for example.

[0004]

However, since the line memory as described above has a relatively large scale as a circuit, there is a problem in that the circuit scale of the entire device also increases accordingly. In addition, it also causes an increase in cost, which is disadvantageous especially for consumer equipment and the like for which cost reduction is required.

[0005]

In order to solve the above-mentioned problems, the present invention provides a memory for writing and reading sample data of pixels of a video signal in units of n samples, and a memory in this memory. An address control unit that can set a write or read address of data corresponding to the horizontal line direction of an image in a specified order opposite to that in normal reproduction, and n samples for writing or reading to or from a memory The signal processing device is configured to include a data rearrangement unit capable of rearranging the unit data arrangement order so as to reverse the order of normal reproduction. The data rearrangement section outputs n pieces of shift register sections to which the luminance signal component data read out from the memory in units of n samples is input for each sample, and the n pieces of shift register sections output. It is configured to include a selection unit that sequentially selects and outputs the generated data in the reverse order of the original arrangement of n samples. Further, the data rearrangement unit is a buffer for writing and reading the color difference signal data read from the memory in units of n samples in units of one sample, and the color difference signal component in units of n samples in the buffer. The address when writing
It is configured to be provided with an address control unit capable of making the address designation order reverse to that in normal reproduction.

According to the above configuration, a RAM and a buffer circuit, which are provided in a signal processing device such as a digital VTR and used for executing a required process, are used, and a relatively simple data rearranging circuit is used. It becomes possible to realize the image left-right inversion function by adding. In addition, even when the RAM is configured to write and read data in units of a predetermined n samples based on the data format, the data arrangement for reversing the data arrangement of n samples is reversed. By providing the replacement circuit, the image left-right inversion function is realized.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram schematically showing the structure of a digital VTR which is provided with a signal processing device according to an embodiment of the present invention. The digital VTR according to the present embodiment processes a video signal as a digital signal as shown in FIG.
Recording circuit system 1 for recording on a video tape, and a video tape 13
A reproduction circuit system 21 for reproducing the image information recorded in
It consists of. The digital VTR of this embodiment is, for example, 525 lines / 60 Hz of the NTSC system or the like.
Will be described as being compatible with the video signal of.

First, the recording circuit system 1 will be described. For this recording circuit system 1, Y (luminance) signal data and component signal data by color difference signal data Cb (BY) and Cr (RY) are input terminals 2,
Input via 3 and 4. These signal data are supplied to the blocking / shuffling circuit 5. In the blocking / shuffling circuit 5, first, as shown in FIG.
As shown in, the input Y signal data is 8 × 8
Each pixel block (Y block) is divided into units, and each color difference signal data Cr, Cb is also 8 × 8.
It is divided into pixel blocks (Cr block, Cb block). Then, a macro block is formed by four Y blocks and a total of six blocks each including one Cr block and one Cb block existing in the same spatial position as each of these Y blocks. Then, in the blocking / shuffling circuit 5, writing is sequentially executed to the RAM 23 which is a frame memory for each macro block. As a result, macroblocks corresponding to one frame are accumulated in the RAM 23. It should be noted that the RAM 23 is actually configured to handle sample data for every 8 pixels as one unit, and control writing and reading of data.

For example, in the case of the present embodiment, the input image signal data is 5 according to the NTSC system or the like.
The video signal of 25 lines / 60 Hz is supposed to correspond, but the blocking / shuffling circuit 5 uses the RAM 23.
When a macro block for one frame is written in, the storage area of the RAM 23 is vertically divided into five areas 1 to 5 as shown in FIG.
Divide into 0 blocks. A unit of a block obtained by dividing an area for one frame in this way is hereinafter referred to as a super block. This super block is formed of, for example, 27 macro blocks as shown in the figure.

Next, as shown in FIG. 3, the blocking / shuffling circuit 5 includes the first macroblock MB ₅₁ of the fifth superblock of the fifth region and the first superblock of the first region. , The first macroblock MB ₁₁ of the fourth region, the first macroblock MB ₄₁ of the ninth superblock of the fourth region, the first macroblock MB ₂₁ of the seventh superblock of the second region, and the first macroblock MB ₂₁ of the third region. The first macroblock MB _{31 of} the 3 superblocks,
In this order, one macro block is read from each area from one frame of macro block data written in the RAM 23 in accordance with a predetermined shuffling rule. As a result, the shuffling process is performed on the video data of one frame. Then, one fixed-length data (segment data) is formed by a total of five macroblocks read out as described above, and this is supplied to the discrete cosine (DCT) conversion circuit 6.

The DCT circuit 6 converts the Y signal data, Cr signal data and Cb signal data of each macroblock on the frequency axis for each fixed length data shown in FIG. 3 to obtain DCT coefficient data and quantize it. Supply to the circuit 7. The quantization circuit 7 quantizes the DCT coefficient data input from the DCT circuit 6 to perform compression processing, and outputs the quantized DCT coefficient data to the framing circuit 8.

In the framing circuit 8, the data supplied from the quantizing circuit 7 is converted into a frame structure based on the recording format. Here, the frame-structured data is input to the deshuffling circuit 9. The deshuffling circuit 9 performs a deshuffling process on the video data for one frame according to the reverse deshuffling rule for the shuffling performed by the blocking / shuffling circuit 5, and supplies it to the recording encoding circuit 10.

In the recording encoding circuit 10, the deshuffling-processed video data is subjected to a predetermined encoding process suitable for the recording format and output to the recording amplifier 11. The recording data amplified by the recording amplifier 11 is supplied to the recording head 12, and the recording head 12 magnetically records the video tape 13. For example, the recording head 12 is a rotary head provided on a rotary drum together with a reproducing head 22 described later, and the video tape 13
Recording and reproduction are performed by obliquely performing a helical scan with respect to.

The video data recorded on the video tape 13 as described above is reproduced by the reproduction circuit system 21. The data recorded on the video tape 13 is read by the reproducing head 22 and supplied to the reproducing / decoding circuit 24 via the reproducing amplifier 23. Playback decoding circuit 24
The data input to is decoded here, and then shuffled in the shuffling circuit 25 according to the same shuffling rule as in the blocking / shuffling circuit 5.

The deframing circuit 26 performs a deframing process for each fixed length data as a reverse process to the data which is frame-structured and recorded in the framing circuit 8 at the time of recording, and then the fixed length data after the compression process (see FIG. 3). Reference) is formed and supplied to the inverse quantization circuit 27.

The dequantization circuit 27 dequantizes the input data with the dequantization coefficient corresponding to the quantization coefficient used in the data quantization process in the quantization circuit 7 during recording. And decompress the compressed data. This decompressed data is sent to the inverse DCT (IDCT) circuit 2
The inverse DCT is applied to each data of the macroblocks that are supplied to the macroblock forming the fixed length data. As a result, the video data before compression processing at the time of recording can be obtained.

The data output from the IDCT circuit 18 is supplied to the deblocking / deshuffling circuit 29. The deblocking / deshuffling circuit 29 performs deshuffling processing on the input data, which is the reverse of the shuffling processing performed by the blocking / shuffling circuit 5. In this deshuffling process as well, as in the shuffling process in the blocking / shuffling circuit 5, the RAM 23 is used so that image data in macroblock units can be obtained as described in FIG. Become. In this case, the writing and reading of data to and from the RAM 23 are also performed in units of 8 samples as in the case of the reproducing circuit system 1. Then, the deblocking / deshuffling circuit 29 performs deblocking processing on the data in macroblock units obtained in this way, and Y
The signal data, the Cb signal data, and the Cr signal data are obtained, and these respective signal data are output terminals 30, 31, 32.
Respectively output via.

An image inverting circuit 34 is provided in this embodiment. The image inversion circuit 34
For example, as shown in the figure, it is provided for the read data line of the RAM 33 in the reproduction circuit system 21. And
When the "image inversion mode" is set as described later, the read data of the RAM 33 is rearranged so that an image in which the left and right sides of the original image are reversed can be obtained. ing.

FIG. 4 is a diagram for conceptually explaining the operation for horizontally reversing the image in the present embodiment. For example, in a normal reproduction operation, when reading data from the RAM 33 and performing deshuffling, 1
The read address is controlled so that the line image data is in the order corresponding to the actual image. That is, in this case, as shown in FIG. 4A, the data corresponding to an image signal of one line and the data A _{1 to} A ₄₄ are read in this order. In addition, as described above, writing / reading data to / from the RAM 33
Since it is performed in units of 8 samples (8 pixels), each of these data A _{1 to} A ₄₄ is formed of sample data P _{1 to} P ₈ for 8 pixels as shown in the figure,
The sample data P _{1 to} P ₈ have a structure according to the arrangement order of the pixels of the horizontal line of the actual image. In this figure, the read data corresponding to the image signal of one line is ₄₄ data A _{1 to} A _{44 because} the number of pixels for one horizontal line of the original video signal is 352 (that is, 44).
This corresponds to × 8 (sample) = 352).

In the case of the image inversion mode, for example, the data writing to the RAM 33 is performed by the same write address control as in the normal state, but at the time of reading, as shown in FIG. In order that the data corresponding to the image signal is opposite to that in the case of FIG. 4A,
That is, the read addresses are controlled so that the data A _{44 to} A ₁ are arranged in order from the left. However, at this point, the pixel sample data P _{1 to} P ₈ correspond to the arrangement order of the original pixels in the horizontal line direction.
As shown in (c), a process of rearranging the structure of the pixel sample data for each of the data A _{44 to} A ₁ in “P _{8 to} P ₁ ”, which is the reverse of “P _{1 to} P ₈ ”, is performed. To By rearranging the data in this way, as the finally obtained image data, the arrangement order of the pixels of each horizontal line is reversed with respect to the original image, and as a result, It is possible to obtain an image with left and right reversed.

FIG. 5 shows the deblocking / deshuffling circuit 29, the RAM 33 and the image inverting circuit 34 shown in FIG.
Is a block diagram extracted and shown, and the horizontal inversion processing of the image in the present embodiment is realized by the operation of these functional circuit units. As shown in this figure, the RAM 33
Is provided with, for example, two frame memories 33a and 33b. The deblocking / deshuffling circuit 29 writes data to the frame memories 33a and 33b in units of 8 samples while controlling the write timing and write address by the write control signal S _WR (write data is D _WR. At the same time, the data read timing and the address control are performed by the read signal S _RD , and the data is similarly read every 8 sample units (the read data is D
₍ Shown as _RD ). As a result, during the normal reproduction operation, deshuffling is performed in macroblock units as described with reference to FIG. Further, the data corresponding to the horizontal line obtained as a result corresponds to the data described in FIG.
Further, the image inversion circuit 34 uses the RA as described in FIG.
It is provided so as to be connected to the line of the read data D _RD from M33. This image inverting circuit 34 is shown in FIG.
Although the sample data is rearranged in units of 8 pixels described in (b) and FIG. 4 (c), actually, read data D read from the RAM 33 as described later.
Of _RD , rearrangement is performed on the sample data of the Y signal component in units of 8 pixels. Then, the read data D _RD
Among these, the data of the color difference signal composed of the Cr signal component and the Cb signal component is the deblocking / deshuffling circuit 29.
The buffer circuit 29a provided therein is used. In the present embodiment, the buffer circuit 29
a is originally a RAM in the format described below.
The color difference signal component (Cr and Cb signal data) data read in units of 8 samples from 33 is rearranged according to a required rule even during normal reproduction, and is output from the deblocking / deshuffling circuit 29, for example. Is provided for converting into a data array corresponding to the format of the color difference signal. Then, in the present embodiment, for example, every time the color difference signal data is written to the buffer circuit 29a in units of 8 samples, the writing is performed in the address order opposite to that in the normal reproduction, and the reading is performed in the normal operation. By performing the same address control, the data can be rearranged in 8-sample units as shown in FIG. 4 (b) → FIG. 4 (c), which will be described later.

An example of the data rearranging operation of the Y signal component data in units of 8 samples by the image inverting circuit 34 will be described with reference to FIGS. 6 and 7. 6 is a circuit diagram showing a configuration example of the image inverting circuit 34, and FIG. 7 is a timing chart showing the operation of the image inverting circuit 34 shown in FIG. The image inverting circuit 34 shown in FIG. 6 includes eight shift registers 40 to 47, selection circuits 50 to 57, switches SW ₁ and SW ₂ . R
As the read data D _RD from the AM 33, the data of the Y signal component in units of 8 samples is input via the input terminal T _IN . The input terminal T _IN is branched and connected to the respective data input terminals of the shift registers 40 to 47. The input terminal T _IN is directly supplied to the terminal T _B of the switch SW ₁ . The shift registers 40 to 47 are
When the enable input is supplied, the data supplied to the data input terminal is input and shifted, and the data output Q ₀ ~
The output is made as Q ₇ . The data outputs Q _{0 to} Q ₇ of the shift registers 40 to 47 are connected to the switch SW.
_{In FIG. 2} , terminals 0 to 7 denoted by “0” to “7” are respectively connected. In the switch SW _2, and terminal 0 terminal 7 are alternatively selected as described later, and supplies the data output of the shift register 40 to 47 to the terminal T _A of the switch SW _1. Switch SW ₁
Selects a terminal T _B in the normal reproduction mode and a terminal T _A in the image inversion mode by a switching signal corresponding to the normal reproduction mode and the image inversion mode, and outputs the data to the deblocking / shuffling circuit 29 as output data. Supply. The selection circuits 50 to 57 have 0 to 7 in advance, respectively.
Select number data is set as a gate circuit, select number data is branched and input, and its output is connected to each enable terminal of the shift registers 40 to 47. This select number data is a 3-bit data signal indicating any of 0 to 7, and the selection circuits 50 to 5
7 outputs an enable signal when the select number data that matches the set select number is input. The select number data is also supplied to the switch SW ₂ as a terminal switching control signal. In the switch SW ₂ , any one of the terminals 0 to 7 numbered according to the select number indicated by the select number data is supplied. To be selected.

The operation of the image inverting circuit 34 having such a configuration is as follows. First, since the switch SW ₁ is switched to the terminal T _B in the normal reproduction mode, the read data D of the RAM 33 supplied to the input terminal T _IN is read.
_RD (Y signal component) is input to the deblocking / shuffling circuit 29 via the switch SW ₁ . That is, in this case, the read data D _{RD of the} RAM 33 is not directly rearranged by the image inverting circuit 34 in units of 8 samples, and the deblocking / shuffling circuit 2 is directly connected.
9 can be regarded as being supplied.

Next, in the image inversion mode, the input terminal T
_As the read data D _RD of the RAM 33 supplied to the _IN , as described above with reference to FIG. 4B, the data corresponding to the image signal for each horizontal line has the reverse arrangement of that in the normal reproduction. The read address is controlled as described above, and the data is sequentially read. Note that the read data at this stage is in units of 8 samples as described in FIG. 4B, and the arrangement order of each sample data in this 8 sample unit corresponds to the arrangement order of the original image data. There is.

RAM 3 read in the image inversion mode
The read data from No. 3 is shown in FIG. 7A in the timing chart of FIG. In FIG. 7A, read data D ₁ , D ₂ , and D ₃ are shown for each set of 8 sample data read from the RAM 33. Further, 1 _A to 8 _A , 1 _B to 8 are respectively included in the respective sample data in the respective read data D ₁ , D ₂ and D ₃ .
The symbols _B , 1 _C to 8 _C are attached. The select number data is supplied to each of the selection circuits 50 to 57 and SW ₂ as shown in FIG. 7B. That is,
Each data block D ₁ , D ₂ , D _3, ... Of FIG.
The select number data is “0 → 1 → 2 → 3 → 4 → 5 → 6 → corresponding to the transfer period of the data for one sample for each
7 "→" 7 → 6 → 5 → 4 → 3 → 2 → 1 → 0 "pattern is repeated. Based on this select number data, the selection of the shift register (40 to 47) capable of inputting data as described above and the terminal (0 to 0 of the switch SW ₂
7) is selected, for example, during the period in which the select number data is "0", the shift register 40 is operated by the input terminal T _IN.
The state in which the data supplied from (1) can be input, and the terminal 0 is selected in the switch SW ₂ .

By providing the select number data shown in FIG. 7B as described above, the outputs Q _{0 to} Q ₇ of the shift registers 40 to 47 are first shown in FIGS. 7C to 7J, respectively. As shown in. For example, as the operation of the shift register 40, the select number data is "0".
During the period t _{0 to} t ₁ , the first sample data 1 _A in the RAM read data D ₁ is input, and the sample data is output as Q ₀ until the time point t ₅ when the select number data becomes “0”. Outputs 1 _A. Then, in a period in which the select number data period t ₄ ~t ₅ is then "0", enter the last sample data 8 _B of RAM read data D _2, the output in the next period t ₅ ~t ₆ Q ₀ becomes the sample data 8 _B. In this period t ₅ ~t ₆ is folded select number data from becoming a "0", the first sample data 1 _C in the RAM read data D ₃ input to this time, the output at time t ₆ after It is output as Q ₀ . By such an operation, the output Q ₀ is
The state shown in FIG. 7C is obtained. Then, the other shift registers 41 to 47 also perform the operations according to the shift register 40 based on the select numbers set in the selection circuits 51 to 57 connected to the enable terminals, respectively, so that the shift registers 40 to 47 shown in FIG. Output Q as shown in (j)
_{1 to} Q ₇ will be obtained.

Then, while the outputs Q _{0 to} Q ₇ of the shift registers 40 to 47 are obtained as described above, the terminal switching of the switch SW ₂ is performed by selecting the select number of the select number data shown in FIG. 7B. Is controlled so that the select number data changes according to the pattern of “7 → 6 → 5 → 4 → 3 → 2 → 1 → 0” in the period t _{2 to} t ₅ , for example. In the switch SW ₂ , the shift register 47 (output Q ₇ ) → 46 (output Q
₆ ) → 45 (output Q ₅ ) → 44 (output Q ₄ ) → 43 (output Q ₃ ) → 42 (output Q ₂ ) → 41 (output Q ₁ ) → 40
The output data is selected in the order of (output Q ₀ ). As a result, in the period t _{2 to} t ₅ , the RAM read data D _{1A in} the order of the sample data 8 _A to 1 _A is obtained as shown in FIG. 7 (k). The RAM read data D _1A is the RAM read data D input from the input terminal T _IN in the previous period t _{0 to} t ₂ .
Time axis sequence order of the sample data 1 _A to 8 _A is to that reversed in _1.

In the subsequent period t _{5 to} t ₇ , the select number data is "0 → 1 → 2 → 3 → 4 → 5 →
6 → 7 "and changed, by being selected in the order of terminal 0-7 accordingly also the terminal of the switch SW _2, the sample data 8 as shown in the period t ₅ ~t ₇ in FIG. 7 (k) Data in which the RAM read data D _{2A in} the order of _B to 1 _B is obtained, and the arrangement order of the sample data 1 _B to 8 _B of the RAM read data D ₂ previously input in the periods t ₂ to t ₅ is reversed. Will be obtained.

By the operation of the image inversion circuit 34 in this manner, the processing for rearranging the arrangement order of the pixel sample data shown in FIG. 4B as described in FIG. 4C. It is possible to do. And
As described above, the image inversion circuit 34 handles the data of the Y signal component, which allows the deblocking / deshuffling circuit 29 of the reproducing circuit system shown in FIG.
As the video data of the Y signal output from the output terminal 30 from, a signal corresponding to an image in which the left and right of the image are inverted is obtained.

Next, the rearrangement processing of the color difference signal data (Cr signal and Cb signal data) in the image inversion mode will be described with reference to FIGS. by the way,
The data format of the color difference signal of the original video signal in the present embodiment is, for example, in principle, as shown in FIG. 9A. In this case, first, as shown in section a, Cr corresponding to one pixel (one sample)
The signal data Cr ₀ and Cb signal data Cb ₀ are arranged,
In the next section b, the same data Cr ₀ and data C as those in the section a
b ₀ is arranged. Then, a section A _{1 which} is a combination of the section a and the section b is formed as a color difference signal data unit for the one sample. Thereafter, as shown in the Cr signal data Cr ₁ ～Cr ₇ and Cb signal data Cb ₁ to CB _7, the section A ₂ ~ section A _8, the same data arrangement form, the color difference of the remaining 7 samples The signal data is arranged, and the data arrangement of the color difference signal in units of 8 samples as shown in the section A to the section B is repeated.

For example, at the time of recording, when the shuffling process is executed by the blocking / shuffling circuit 5 using the RAM 33, the color difference signal data is as shown in FIG.
The format shown in FIG. 9A is converted into the format shown in FIG. 9B, and writing to the RAM 33 is executed. The RAM writing format of the color difference signal data shown in FIG.
_As shown in ₁ , first, the Cr signal data C for 8 samples
r _{0 to} Cr ₇ are arranged, and in the next section B ₂ , 8 samples of Cb signal data Cb _{0 to} Cb ₇ are arranged. Then, the writing of data to the RAM 33 is performed for each set of 8 samples in each of the sections B ₁ and B ₂ . After this, a period B ₃ in which data other than the color difference signals for 16 samples is arranged is provided. And
After that, as shown in sections B ₄ and B ₅ , the array pattern of the color difference signal data in units of 8 samples is repeated as described above. That is, by adopting the data format as shown in FIG. 9B, an array of data suitable for the 8-bit data processing in the RAM 33 can be obtained. Then, the reading of the color difference signal data from the RAM 33 is also performed in units of 8 samples based on the format shown in FIG. 9B, and the shuffling process by the blocking / shuffling circuit 5 is executed.

Therefore, during the normal reproduction, when the deblocking / deshuffling circuit 29 performs the deblocking / deshuffling processing on the color difference signal components, the format is as shown in FIG. 9B. The read data from the RAM 33 is rearranged into the format shown in FIG. 9A and finally outputted as the Cr signal data and the Cb signal data from the output terminals 31 and 32.

As shown in FIG. 1, the deblocking / shuffling circuit 29 includes a buffer circuit 29a.
Is provided, the buffer circuit 29a is supposed to perform the processing of converting the data format shown in FIG. 9B to that shown in FIG. 9A during normal reproduction, for example. Further, in the present embodiment, the rearrangement process of the color difference signal data read from the RAM 33 in units of 8 samples in the image inversion mode is performed by using the buffer circuit 29a as described below. To be

The block diagram of FIG. 8 shows the buffer circuit 2 described above.
The configuration of 9a is schematically shown, and in this case, as shown in the figure, two buffer RAMs 29b and 29c are provided. Color difference signal component data (Cr signal and C signal) of the RAM read data D _RD read from the RAM 33 is written to the buffer RAMs 29b and 29c.
b signal data) is supplied in units of 8 samples. In this way, the data input in units of 28 samples is stored in the buffer R for each sample for a required address at a predetermined timing by the write control signal S _WR1.
Written to AM 29b, 29c. The data written in the buffer RAMs 29b and 29c is read out based on the read timing and address control by the read control signal S _RD1 and supplied to the terminals T _C and T _D of the bank changeover switch SW ₃ . The bank changeover switch SW ₃ executes the changeover operation for the terminals T _C and T _D at a predetermined timing based on the bank changeover signal S _B , and the buffer RAM 29 via the terminals T _C and T _D.
Bank switching is performed for the read data of b and 29c. As a result of providing the buffer circuit 29a having such a configuration, during normal reproduction, the color difference signal data read from the RAM 33 in units of 8 samples in the format shown in FIG. 9B is shown in FIG. It can be converted to the format shown in.

When the image inversion mode is set during reproduction, the color difference signal data (Cr signal data and Cb signal data) are processed as follows. in this case,
As the color difference signal data read from the RAM 33, as described above with reference to FIG. 4B, the reading process is executed in units of 8 samples from the address opposite to that at the time of writing for each horizontal line. However, as the color difference signal data in units of 8 samples read from the RAM 33 at this time,
The format is based on the format shown in FIG.
That is, the Cr signal data of 8 samples is read at once in the order of Cr ₀ to Cr ₇ by designating the read address once (section B ₁ ), and the Cb signal data of 8 samples is designated Cb ₀ by the designation of the next read address. The data will be read in the order of Cb ₇ .

The color difference signal data in units of 8 samples read from the RAM 33 as described above is stored in the buffer circuit 29 in the deblocking / shuffling circuit 29.
a. When writing the data in units of 8 samples to the buffer RAMs 29b and 29c of the buffer circuit 29a, the write control signal S _WR1 (see FIG. 8) is used to specify the write address in the reverse order of the normal reproduction. Address control is performed so that

Accordingly, it can be considered that the color difference signal data in the format as shown in FIG. 10A is written in the buffer circuit 29a in the image inversion mode, for example. That is, in the case of the data format of FIG. 9B corresponding to the normal reproduction, the array of the Cr signal data of 8 samples in the section B ₁ is Cr ₀ to Cr.
_In contrast, in the case of FIG. 10A corresponding to the image inversion mode, the arrangement of the Cr signal data of 8 samples in the section B _R1 is reversed to Cr ₇ to Cr _0. Has been done. And also in the next section B _R2 ,
Similarly, the array of Cb signal data of 8 samples is Cb _{7 to} C.
b ₀ , which is an array pattern opposite to the section B ₂ in FIG. 9B. Further, the arrangement order of the Cr signal data or Cb signal data for each likewise 8 samples even in the section B ₄ and section B ₅ followed by section B ₃ is in the contrary to the case of FIG. 9 (b).

Then, with respect to the buffer RAMs 29b and 29c in which the color difference signal data having such contents are written, when the data is read, the read control by the same timing and address designation as in the normal reproduction, and the bank switching control are performed. By executing this, it is possible to obtain color difference signal data in a format as shown in FIG.
In FIG. 10B, the Cr signal data and the Cb signal data corresponding to 8 samples are represented by the sections A _{R1 to} A in the figure.
_As shown in _R8 , [Cr ₇ , Cb ₇ , Cr ₇ , Cb ₇ ]
~ [Cr ₀ , Cb ₀ , Cr ₀ , Cb ₀ ] are arranged in this order. This data arrangement can be regarded as the arrangement in which the sections A _{1 to} A ₈ in the color difference signal data format of FIG. 9A corresponding to the normal reproduction are arranged in reverse so as to be the sections A _{8 to} A ₁ . As a result, for the color difference signal data in units of 8 samples read from the RAM 33,
This corresponds to the processing of rearranging the pixel sample data array order in the horizontal line direction as shown in FIGS. 4B to 4C. Then, the deblocking / deshuffling circuit 29 performs the required processing on the color difference signal data in the format as shown in FIG.
To output as Cr signal data and Cb signal data, respectively.

As described above, the Y signal data, the Cr signal data and the Cb signal data which are color difference signals are rearranged, and finally the deblocking / deshuffling circuit 29 outputs the Y signal, the Cr signal, and the Cb signal. By outputting as component signal data by a signal, it is possible to display an image in which the left and right are inverted.

In the present embodiment, for example, R
It is possible to easily obtain a mosaic image by controlling the write and read addresses for the AM 33 during the normal reproduction and only rearranging the data within the unit of 8 samples. Further, depending on the address control for the RAM 33 and the buffer circuit 29a,
For example, it is possible to obtain a special effect image in which the left half of the video image displays the normal image and the right half displays the symmetrical image by performing the reverse image processing.

Further, the present invention is not limited to the one shown in the above-mentioned embodiment, and for example, the video signal processing provided with the memory in which the writing and reading control is performed in the unit of the number of samples other than the unit of 8 samples. It can also be applied to circuits and the like. Further, in the above embodiment, the description has been made assuming that it corresponds to the 525 lines / 60 Hz video signal of the NTSC system or the like, but it may be configured to correspond to the 625 lines / 50 Hz video signal of the PAL system, for example. Needless to say.

[0042]

As described above, the signal processing device of the present invention is capable of performing a simple shift register and address control at the time of writing or reading to the memory without adding a relatively large-scale circuit such as a line memory. Since the left and right reversed image display can be performed, for example, when the present invention is applied to a consumer video camera device or the like,
It has an effect that an image reversal function can be added at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video camera device including a signal processing device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a structure of a macro block.

FIG. 3 is an explanatory diagram showing shuffling processing in the present embodiment.

FIG. 4 is an explanatory diagram conceptually showing a data rearrangement process in the image inversion mode in the present embodiment.

FIG. 5 is a block diagram showing a deblocking / deshuffling circuit and a RAM extracted from the present embodiment.

FIG. 6 is a block diagram illustrating a configuration example of an image inversion circuit.

FIG. 7 is a timing chart showing the operation of the image inversion circuit.

FIG. 8 is a block diagram showing a configuration of a buffer circuit.

FIG. 9 is a diagram showing a format of color difference signal data.

FIG. 10 is a diagram showing a format of color difference signal data.

[Explanation of symbols]

 29 Deblocking / Deshuffling Circuit 29a Buffer Circuit 29b, 29c Buffer RAM 33 RAM 33a, 33b Frame Memory 34 Image Inversion Circuit

Claims (3)

[Claims] 1. A storage unit configured to write and read sample data of pixels of a video signal in units of n samples, and a write or read address of data corresponding to a horizontal line direction of an image in the storage unit. The address control means which can be set in a specified order opposite to that in the normal reproduction, and the arrangement order of the data of n samples which is written to or read from the storage means are reverse to those in the normal reproduction. A signal processing device comprising: a data rearranging unit capable of rearranging so that 2. The data rearranging means is adapted to input the luminance signal component data read from the storage means in units of n samples for each sample.
Number of shift register means and the data output from the n number of shift register means are reversed from the original arrangement order of n sample units,
The signal processing apparatus according to claim 1, further comprising: a selection unit that sequentially selects and outputs. 3. The data rearranging means is a buffer in which the color difference signal data read from the storage means in units of n samples is written and read for each sample, and the buffer is arranged in units of n samples. 2. The signal processing according to claim 1, further comprising address control means capable of setting an address when writing the color difference signal component of <1> to an address designation order opposite to that in the normal reproduction. apparatus.