JPH0898142A - Picture reproduction device - Google Patents

Abstract

PURPOSE: To easily realize high speed reproduction higher than standard reproduction speed. CONSTITUTION: Constitution from the decoding circuit 202 of a variable length code, which decodes encoding picture information in accordance with an encoding processing, to an adder 206, and a control sequencer 300 stopping the decoding of one or plural pieces of encoding picture information in a B-picture by controlling a decoding processing at the time of variable speed reproduction faster than one-fold speed are provided. Namely, the control sequencer 300 does not execute decoding in the decoding circuit 202 of the B-picture at the time of variable speed reproduction faster than one-fold speed by controlling the decoding circuit 202 of the variable length code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory such as a CD-ROM or CD-I (for example, a so-called compact disc on which image information compressed and coded by utilizing inter-frame correlation is recorded. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reproducing device that reproduces and decodes compressed and encoded image information from an information recording medium such as CD-Interactive.

[0002]

2. Description of the Related Art Conventionally, various methods for compressing and coding an image signal have been proposed. As a specific example thereof, for example, there is a so-called MPEG (International Standardization Working Group for color moving picture coding system). Moving Picture Exp
ert Group). That is, the encoding method defined by the MPEG is a so-called high-efficiency encoding method for image signals for digital storage media, and the redundancy in the time axis direction is reduced by taking the difference between images, and then the so-called discrete The cosine transform (DCT) process and the variable length code are used to reduce the redundancy in the spatial axis direction.

In this MPEG encoding method, a frame image is an I picture (Intra-coded picture), a P picture (forward predictive-coded picture) or a B picture, which will be described later. (Bidirectionally-coded image: Bidirectionally-code
The picture signal is compressed and coded as one of the three types of pictures (d picture).

Among the I, P and B pictures,
In the I picture, the image signal for one frame is encoded and transmitted as it is. On the other hand, in the P picture, basically, the difference from the image signal of the I picture or P picture that precedes it in time is encoded and transmitted. In the B picture, basically, the difference from the average value of both the frame preceding and the frame following the time is calculated, and the difference is encoded and transmitted.

As shown in FIG. 2, the structure of data handled by the above-mentioned MPEG encoding system is, in order from the bottom, a block layer, a macroblock layer, a slice layer, a picture layer, and a group of pictures. (GOP: Gr
Oup of Picture) layer, and the video sequence layer has a hierarchical structure. Hereinafter, a brief description will be given in order from the lower layer in FIG.

First, the unit block of the block layer is
It is composed of 8 × 8 pixels (pixels of 8 lines × 8 pixels) adjacent to each other in luminance or color difference. DCT (Discrete Cosine Transform) is applied to each unit block.

Next, the macroblocks of the macroblock layer are four luminance blocks (luminance unit blocks) Y0, Y1, Y2, and Y3 that are adjacent to each other in the left, right, top, and bottom, and at the same position as the luminance block on the image. The color difference block (color difference unit block) Cr and Cb corresponds to 6 blocks in total. The order of transmission of these blocks is Y0, Y1, Y2, Y3, Cr, Cb.

The slice layer is composed of one or a plurality of macroblocks which are continuous in the scanning order of the image. At the slice head (header), the motion vector and D in the image
The difference of the C (direct current) component is reset, and the first macroblock has data indicating its position in the image, so that it can be restored even if an error occurs.

In the picture layer, each picture, that is, each picture is composed of at least one or a plurality of slices. Each of the I picture, P picture, B picture, and DC intra-coded image (DC coded (D) pictur) is encoded according to the encoding method.
It is classified into four types of images of e).

Here, in the above-mentioned I picture, only the information closed in one image at the time of encoding is used. In other words, the image can be reconstructed only by the information of the I picture itself when decoding. Actually, the DCT processing is performed as it is and the encoding is performed without taking the difference.

In the P picture, an I picture or a P picture which is located in a temporally previous position at the input and has already been decoded is used as a prediction image (image serving as a reference for obtaining a difference).

[0012] In the B picture, an I picture or P picture that is temporally positioned earlier and has already been decoded, and an I picture or P picture that is temporally posterior and has already been decoded, and their Three types of interpolated images made from both are used.

The DC intra-coded image (D picture) is an intra-coded image composed of only DCT DC coefficients and cannot exist in the same sequence as the other three types of images.

The group of pictures (GOP) layer includes one or a plurality of I pictures and 0 or a plurality of non-I pictures.
And a picture. Here, the interval of the I picture and the interval of the I picture or the B picture are free. Further, the interval between the I picture and the P picture may be changed inside the group of picture layers.

The video sequence layer includes an image size,
It is composed of one or more group of picture layers having the same image rate and the like.

A typical example of decoding and displaying encoded data according to the above method will be described with reference to FIG. In FIG. 3, I0 and the like in the drawing are I pictures, B1 and B2 and the like in the drawing are B pictures, and P3 and P6 and the like in the drawing are P pictures.
The pictures are shown, and the number in each picture indicates the display order. The group of these pictures is
Decoding is performed in the following order (1) to (15).

(1) The picture of I0 is decoded only from the compressed data corresponding to the I0 (intra-frame correlation).

(2) The picture of B1 is decoded from the decoded picture of I0 and the compressed data corresponding to B1. If there is a GOP (previous GOP) before the current GOP currently being decoded, then the previous GOP
The picture of B1 is decoded from the decoded P picture of OP (picture of P15 ', for example), the decoded picture of I0 of the current GOP, and the compressed data corresponding to B1.

(3) The picture of B2 is decoded from the decoded picture of I0 and the compressed data corresponding to B2. When the previous GOP exists, the decoded P picture (picture of P15 ′) of the previous GOP, the decoded I0 picture of the current GOP, and the compressed data corresponding to B2 are used to calculate the B2 picture. To decode.

(4) The picture of P3 is decoded from the decoded picture of I0 and the compressed data corresponding to P3.

(5) The picture of B4 is decoded from the decoded picture of I0 and the decoded picture of P3 and the compressed data corresponding to B4.

(6) The picture of B5 is decoded from the decoded picture of I0 and the decoded picture of P3 and the compressed data corresponding to B5.

(7) The picture of P6 is decoded from the decoded picture of P3 and the compressed data corresponding to P6.

(8) The picture of B7 is decoded from the decoded picture of P3 and the decoded picture of P6 and the compressed data corresponding to B7.

(9) The picture of B8 is decoded from the decoded picture of P3 and the decoded picture of P6 and the compressed data corresponding to B8.

(10) The picture of P9 is decoded from the decoded picture of P6 and the compressed data corresponding to P9.

(11) The picture of B10 is decoded from the decoded picture of P6 and the decoded picture of P9 and the compressed data corresponding to B10.

(12) The picture of B11 is decoded from the decoded picture of P6 and the decoded picture of P9 and the compressed data corresponding to B11.

(13) From the decoded P9 picture and the compressed data corresponding to P12,
Decode the picture.

(14) The picture of B13 is decoded from the decoded picture of P9 and the decoded picture of P12 and the compressed data corresponding to B13.

(15) The picture of B14 is decoded from the decoded picture of P9 and the decoded picture of P12 and the compressed data corresponding to B14. And so on.

Therefore, in order to perform the above-described decoding, the order of the compressed data supplied to the decoder is I
0 → B1 → B2 → P3 → B4 → B5 → P6 → B7 → B8
→ P9 → B10 → B11 → P12 → ...

As described above, in the MPEG compression compression encoding, the frame is constructed by utilizing the inter-frame correlation, and at the time of decoding, a new picture is constructed by utilizing the previously decoded picture. It is created and the created picture is used again for the construction of the next picture. Also, M
The data compressed and encoded by the PEG method does not include the data for recombining the previous picture from the already decoded picture, and the data in only one direction is recorded and transmitted.

[0034]

By the way, the above-mentioned M
Various methods have been proposed for performing variable speed reproduction at a standard reproduction speed (1 × speed) or higher in a video signal compression technique using inter-frame correlation such as the PEG method, but it is simpler and requires less processing. An easy method is desired.

Therefore, the present invention has been proposed in view of the above-mentioned circumstances, and in the video signal compression technique utilizing the inter-frame correlation, it is possible to easily and easily perform the variable speed reproduction above the standard reproduction speed. It is an object of the present invention to provide an image reproducing device capable of performing the above.

[0036]

DISCLOSURE OF THE INVENTION The present invention has been proposed in order to achieve the above-mentioned object, and there is at least one code image information used for inter-image correlation that is not used for inter-image correlation. In a picture reproducing apparatus for obtaining a decoded reproduced image from the coded image information of a predetermined sequence in which the coded image information is arranged, a decoding means for decoding the coded image information according to a coding process. , Output means for outputting the image information subjected to the decoding processing, and not used for inter-image correlation by controlling the decoding processing by the decoding means or the output of the output means during variable speed reproduction at a speed higher than 1 × speed. And a control means for stopping decoding or output of one or more pieces of encoded image information out of the encoded image information.

Here, the coded image information used for the inter-picture correlation is an intra-picture coded picture and a forward predictive coded picture, and the coded picture information not used for the inter-picture correlation is a bidirectional predictive coded picture. Is.

[0038]

According to the present invention, even if the coded image information not used for inter-image correlation is not decoded or output, it does not affect the subsequent decoding of the coded image information. Therefore, the control means realizes the variable speed reproduction higher than the 1 × speed by stopping the decoding or the output of one or a plurality of encoded image information of the encoded image information not used for the inter-image correlation. There is.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a schematic structure of the image reproducing apparatus of the present invention.

The image reproducing apparatus of the embodiment of the present invention, as shown in FIG. 1, is an optical disc 3 which is an information recording medium in which a moving picture sequence of MPEG1 format is recorded as a moving picture sequence of GOP unit which is a predetermined unit.
01 is reproduced, the moving picture bit stream in the MPEG1 format is decoded, and the moving picture is restored.

That is, as shown in FIG. 1, the image reproducing apparatus according to the present embodiment allows images to be displayed between encoded image information (I picture or P picture) used for inter-image correlation as in the MPEG1 format. An image reproduction device for obtaining a decoded reproduction image from the encoded image information of a sequence in which one or more pieces of encoded image information (B picture) not used for inter-correlation are arranged, wherein the encoded image information is encoded. A configuration from the variable length code decoding circuit 202 to the adder 206 as a decoding means for performing decoding according to the conversion processing;
A control sequencer 300 as a control means for stopping the decoding of one or more pieces of encoded image information in the B picture by controlling the decoding processing in the decoding means at the time of variable speed reproduction at a speed higher than 1 × speed. It is characterized by having.

That is, the control sequencer 300 controls, for example, the variable-length code decoding circuit 202, which will be described later, so that the B-picture is decoded by the corresponding decoding circuit 202 during variable speed reproduction at a speed higher than 1 × speed. Do not do it. Here, for example, when there are two B pictures between I or P pictures as described above, the control sequencer 300 does not perform decoding of both or one of the two B pictures. By realizing, variable speed reproduction is realized. For example, if only one B picture is not decoded, it is possible to reproduce at or above the standard reproduction speed and twice or less (for example, about 1.5 times).
If the picture is not decoded, the reproduction can be performed at three times the standard reproduction speed. However, in the case of the present embodiment, it is assumed that the disc 301 is rotating at a speed capable of supporting at least the triple speed reproduction.

Further, in the apparatus of this embodiment, the decoding circuit 202 performs the decoding, but if the decoded B picture signal is not displayed, the same variable speed reproduction can be performed. For example, a display control circuit 222 or frame memories FM1 to FM4, which will be described later, serving as output means for outputting a signal after decoding, and a control sequencer 30.
The video signal of the B picture is prevented from being output by the control of the CPU 303 based on information such as the type of the picture stored in each frame memory described later from 0 and the temporal reference number described later. By (not displaying), variable speed reproduction similar to the above is possible.

First, the basic operation of the image reproducing apparatus of this embodiment will be described, and then the reproducing operation at a standard reproduction speed or higher in this apparatus will be described.

In FIG. 1, a so-called CD-RO in which a moving picture sequence in the MPEG1 format is recorded.
A disc that is an M (that is, a so-called video CD) 30
From 1, CD-ROM whose operation is controlled by the CPU 303
The controller 302 reads the recorded moving image sequence and extracts the error-corrected MPEG1 video bit stream.

The MPEG1 video bit stream output from the CD-ROM controller 302 is sent to the configuration of the bit stream buffer 201 and the subsequent stages which decode the MPEG1 bit stream. The bit stream buffer 201 is composed of, for example, a frame memory, and temporarily stores the supplied MPEG1 video bit stream and then reads it and sends it to the variable length code decoding circuit 202.

The variable-length code decoding circuit 202 performs variable-length decoding on the data supplied from the bit stream buffer 201, and dequantizes the DCT coefficient and quantization step information of the decoded image in the inverse quantization circuit 203. Send to.
The inverse quantization circuit 203 performs inverse quantization processing corresponding to the quantization at the time of encoding, and further the next inverse DCT circuit 204
Then, inverse DCT processing corresponding to DCT at the time of encoding is performed. All of these processes are performed in units of the macro blocks described above.

Further, the control sequencer 300 receives the motion vector, picture type information and the like from the variable length code decoding circuit 202 and controls the switching of each of the switches S1 to S6 described later together with the variable length code decoding. The error recovery bit is received from the digitization circuit 202 and error recovery processing is performed. Further, the control sequencer 300, when performing variable speed reproduction at a standard reproduction speed or higher, performs the decoding circuit 20.
2 is also controlled so that the decoding circuit 202 does not decode one or more B pictures as described above. The control sequencer 300
Switches S1 to S6 via terminals 321 to 326.
To the switch control signal.

The output from the inverse DCT circuit 204 is supplied to one switched terminal tA of the changeover switch S5 and also sent to the adder 206. The changeover switch S5
If the supplied data is data of a macroblock of an I picture, it outputs the data as it is, and if it is data of a macroblock of another picture type, the adder 206
Outputs the data supplied from.

The output data of the changeover switch S5 is sent to the common connection terminal of the changeover switch S4. The changeover switch S4 is connected to the data input terminals of the corresponding frame memories FM1 to FM4 at the switched terminals t1 to t4, respectively, and these switched terminals t1 to t4 are sequentially switched.

The data sequentially sent to the frame memories FM1 to FM4 via the changeover switch S4 are sequentially stored in the frame memories FM1 to FM4, and the stored data are subsequently used for image reproduction and display. Like That is, the frame memories FM1 to F
Of the data stored in M4, the I picture data is used as it is for image reproduction, and the other picture data is input to the adder 206 later as image data (P
Or B picture data).
The frame memories FM1 to FM4 are connected to the terminal 311.
Writing and reading are controlled by a writing / reading control signal supplied from the control sequencer 300 via the.

The data read from each of the frame memories FM1 to FM4 is sent to the corresponding switched terminals t1 to t4 of the changeover switches S1 to S3. The changeover switches S1 to S3 are also changed over in the same manner as the switches S4 and S5 according to the type of macroblock to be processed.

The outputs of the changeover switches S1 and S2 are the memory read circuits 215 and 21 as buffers.
7 to the half pixel processing circuits 216 and 218, where half pixel processing for halving the number of pixels is performed and sent to the adder 219 or the changeover switch S.
6 are sent to the corresponding switched terminals tf and tb. The output of the adder 219 is also sent to the corresponding switched terminal tfb of the changeover switch S6. The output from the changeover switch S6 is sent to the adder 206. The output of the adder 206 is sent to the switched terminal tB of the switch S5.

The output of the change-over switch S3 becomes the restored image data and the display control circuit 22.
Sent to 2. The output from the display control circuit 222 is sent from the terminal 223 as an output video signal to a subsequent stage configuration (for example, a monitor device).

Further, from the control sequencer 300, information such as a picture type held in each frame memory and a temporal reference number to be described later is sent to the memory register 312, and the memory register 312 concerned outputs a terminal 313. The above information is sent to the CPU 303 via
To be sent to. Therefore, the CPU 30
3 can easily know the type of picture in each frame memory by reading the content held in the memory register 312. CPU 303
When the reproduction at the standard reproduction speed or higher is executed, the information in the memory register 312 is used to control the writing / reading of each frame memory.

Further, in the image reproducing apparatus of the present embodiment as described above, as the reproduction modes, for example, normal play mode, intra play mode, still play (pause) mode, 1 frame play mode, IP -Play (IP-scan) mode and I
Various reproduction modes such as PB1-play mode, IPB2-play mode, and direct mode can be selected.

The normal play mode is a normal speed forward reproduction mode in which the bit stream written in the disk is sequentially decoded and displayed. The intra play mode is a reproduction mode in which only the I picture in the bit stream is decoded and the other pictures are skipped, for example, used during fast forward. In the still play mode, when the command is written, the decoding operation of the bitstream is stopped and the pause mode is fixed to the currently displayed screen. The 1-frame play mode is a so-called frame advance mode in which, when this command is written in the paused state, the next frame is decoded and the next frame is displayed.
The IP-play (IP scan) mode is a reproduction mode in which only I-pictures and P-pictures are decoded and B-pictures are skipped. For example, the fast-forward reproduction of 1 × speed or more is used. IPB1-Play Mode and I
The PB2-play mode is a mode in which an I picture and a P picture are decoded, and in addition, only one of the two B pictures is decoded. These IP
The B1-play mode and the IPB2-play mode are also used for reproduction at the above-mentioned 1 × speed or higher. The direct mode is a mode in which a picture indicated by a temporal reference number (tempNal_reference number (tmpN)) representing information in a picture layer designated by the host computer (CPU) is decoded and displayed. In this direct mode, until the picture of the temporal reference number is found, I picture, P picture
Decode only the picture.

Next, description will be made on the case where the image reproducing apparatus of the embodiment of the present invention realizes a reproducing speed higher than the standard reproducing speed.

In the following example, the order of the bitstreams supplied to the bitstream buffer 201 is I0 → B1 → B2 → P3 → B4 → B5 → P6 → B7 → B.
In the case of 8 → P9 → B10 → B11 → P12 → B13 → B14, a case of performing reproduction at the standard reproduction speed or higher will be described. The order of display on the display during forward reproduction of the bit stream is B1.
→ B2 → I0 → B4 → B5 → P3 → B7 → B8 → P6 →
It becomes B10->B11->P9->B13->B14-> P12.

In the apparatus of this embodiment, the reproduction using the frame memories (FM1 to FM3) capable of storing three image planes has been described. That is, in this embodiment,
In the configuration of FIG. 1, for example, the frame memories FM1 and FM
2 and FM3 are used, and the frame memory FM4 is not used (or is not provided). In this case, the switches S1 to S4 are connected to the switched terminals t1 to t3.
Only (switched terminal t4 is not used or not provided).

In such an example, when the moving image is reproduced at the normal standard speed in the forward direction, the control sequencer 30 is used.
0 performs switching control to each switched terminal of each switch S1 to S6 as shown in Table 1, and the CPU 303 also uses the three frame memories FM1, FM2 and FM3 as shown in Table 1. Table 1 shows each frame memory FM1 to FM3.
Shows the types of pictures held in the display and their order, the types of pictures to be displayed on the display and their order, and the terminals to be switched selected by the switches S1 to S6. The setting of the switched terminals of the switches S5 and S6 changes within the picture, but Table 1 shows a typical setting.

[0063]

[Table 1]

As a first specific example of this table 1,
When the reproduction is performed at a speed higher than the double speed (for example, the reproduction is performed at the triple speed), the following is performed. In the case of this 3 × speed reproduction, the control sequencer 300 controls the decoding circuit 202 not to decode the B picture and the changeover switch S.
1 to S6 are switched and controlled as shown in Table 2, and the CPU 30
3 also controls writing / reading of the frame memories FM1 to FM3 as shown in Table 2.

[0065]

[Table 2]

That is, in Table 2, the B picture is skipped (for example, not decoded) and reproduced. According to this, the picture to be displayed on the display (monitor) is I0 → P3 → P6 → P9 → P.
12 → ..., which makes it possible to reproduce three times as much as in the case of Table 1.

Next, with respect to Table 1 above, as a second specific example, for example, in the case of performing reproduction at a standard reproduction speed or higher and a double speed or lower (for example, reproduction at about 1.5 times), control The sequencer 300 controls not to decode one of the B pictures, and also the changeover switches S1 to S
6, and the CPU 303 also controls writing / reading of the frame memories FM1 to FM3 as shown in Table 3.

[0068]

[Table 3]

That is, in Table 3, I or P
One of the two B pictures between pictures is skipped (for example, not decoded) and reproduced. According to this
The picture displayed on the display is, for example, B2 →
I0 → B5 → P3 → B8 → P6 → B11 → P9 → B14
→ P12 → ..., which is about 1.
5 times reproduction is possible. In the case of the example in Table 3,
Which of the above two B pictures should be skipped?
It can be set by the control sequencer 300 and the CPU 303 knowing the information such as the picture type and the temporal reference number from the decoding circuit 202.

In the above-described embodiment, the case where two B pictures are present between I or P pictures is taken as an example. However, one or three or more B pictures are present between the I or P pictures. When there are B pictures, the number of B pictures to be skipped and reproduced is changed by changing the number of B pictures to be skipped and reproduced. It is possible to perform variable speed reproduction at an arbitrary speed according to the number.

When a plurality of B pictures are present between I or P pictures, the number of B pictures to be skipped and reproduced is arbitrarily changed between I or P pictures (I or P). It is also possible to change the number of B pictures between pictures).

Further, in the above description of Tables 1 to 3,
Although an example in which three frame memories FM1 to FM3 are used has been described, high speed reproduction is similarly possible even when four frame memories FM1 to FM4 are used.

[0073]

As described above, in the present invention, even if the coded image information that is not used for the inter-image correlation is not decoded or output, it does not affect the subsequent decoding of the coded image information. Therefore, the control means stops decoding or outputting one or more pieces of encoded image information out of the encoded image information not used for inter-image correlation, so that variable speed reproduction at a speed higher than 1 × speed can be easily and easily performed. Is feasible.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of an image reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the structure of data handled by an MPEG encoding system.

FIG. 3 is a diagram for explaining a typical example when decoding and displaying coded data according to the MPEG coding method.

[Explanation of symbols]

 202 Decoding Circuit for Variable Length Coding 203 Inverse Quantization Circuit 204 Inverse DCT Circuit 206 Adder 300 Control Sequencer FM1 to FM4 Frame Memory

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 7/137 Z

Claims (2)

[Claims] 1. Decoding from a predetermined sequence of coded image information used for inter-image correlation, in which one or more coded image information not used for inter-image correlation is arranged In an image reproducing device for obtaining a reproduced image, a decoding means for decoding the coded image information according to a coding process, an output means for outputting the decoded image information, and a shift speed higher than 1 × speed At the time of reproduction, by controlling the decoding processing in the decoding means or the output of the output means, decoding of one or more pieces of encoded image information of the encoded image information not used for inter-image correlation or An image reproducing apparatus comprising: a control unit that stops output. 2. The encoded image information used for the inter-image correlation is an intra-image encoded image and a forward predictive encoded image,
The image reproducing apparatus according to claim 1, wherein the coded image information not used for the inter-image correlation is a bidirectional predictive coded image.