JPH0964856A - Reset synchronization system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a synchronization acquisition time by using a matched filter so as to detect a reception signal and a correlation signal and using the correlation signal so as to generate a clock phase switching timing for demodulating the reception signal. SOLUTION: A control circuit 101 receiving a load timing signal compares a peak signal of a matched filter 109 with an output of a frequency divider circuit 107. When both the signals reach an L level, the control circuit 101 provides a switching signal to throw a switch 108 to the position through which the peak signal of the filter 109 is given to a phase comparator 104. The throwing state of the switch 108 is maintained till the absence of a reception signal is detected by monitoring the peak signal of the filter 109. Furthermore, the comparator 1-4 receiving the peak signal of the filter 109 compares a phase of a leading edge of an output of a frequency divider circuit 102 with a phase of a leading edge of the peak signal of the filter 109 and clock phase locking is conducted from an approximated phase by changing a control voltage of a VCO 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset synchronization system in a spread spectrum communication device.

[0002]

2. Description of the Related Art Conventionally, when performing synchronization acquisition in a spread spectrum communication apparatus using a matched filter,
The correlation peak of the matched filter and the code period clock generation timing signal are compared in phase by a phase comparator, and the voltage controlled oscillator (VC
The clock phase output from O) is shifted to synchronously capture and hold the demodulation data sampling clock.

[0003]

However, in the above-mentioned conventional example, the phase locked loop (PLL) is used.
Due to the relationship between the lockup time and the jitter, it is difficult to significantly reduce the pull-in time, and when performing communication by burst reception, there was a problem that the preamble period for synchronization acquisition increased and the throughput decreased. .

An object of the present invention is to provide a reset synchronization system which can shorten the time required for synchronization acquisition.

[0005]

According to the present invention, in a spread spectrum communication device using a matched filter, a received signal and a correlation signal are detected by the matched filter, and the received signal is demodulated using the correlation signal. For generating a clock phase switching timing for

Specifically, the demodulation clock generating means for demodulating the received signal uses a separate internal clock as the phase comparison signal of the phase comparator when there is no received signal, and a matched filter. Means for generating reset timing / load timing from the correlation peak signal, means for detecting the phase relationship between the correlation peak and the chip rate clock, etc., and controlling the generation timing of the code period clock according to this phase relationship, Means for switching the clock phase generated by the demodulation clock generation means based on the code cycle clock generation timing signal, and phase comparison of the phase comparator in the next cycle after completion of this clock phase switching operation (reset operation) And means for switching the signal from the internal clock to the correlation peak signal. That.

With the above configuration, as soon as a signal is received and a correlation peak is obtained, the clock phase can be pulled in from within one chip, and the speed of synchronization acquisition can be increased.
The effect is that the synchronous preamble time at the start of communication can be shortened and the throughput can be improved, and in addition, when applying to that system, flexible system deployment can be considered. .

Furthermore, when the reception signal detecting means determines that there is no reception signal, the means for adjusting the phase of the internal clock and the sampling clock or the code generation timing is provided, so that the internal operation can be performed at high speed at the reception standby time. It becomes possible to synchronize with the clock, and even if the burst period at the time of receiving burst data can be a short cycle, it is possible to establish synchronization by a high-speed reset operation, which has the effect of shortening the preamble period. By performing the synchronization acquisition for each reception, the effect of expanding the flexibility of system construction can be obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of this embodiment.

In FIG. 1, a control circuit 101 is a circuit that controls the initial value of a counter circuit that divides a clock, controls the switching between the matched filter output and the output of the divider circuit 107, and the like. The (code frequency generation circuit) 102 is a circuit that divides the clock of the voltage controlled oscillator (VCO) 105 into a code period frequency.

The reset circuit 103 is a circuit that generates a load timing based on the clock of the VCO 105 from the correlation output of the matched filter 109 and outputs a signal indicating a load generation timing and a clock phase relationship.

The phase comparator 104 is a phase comparator for performing phase comparison between the code period frequency clock timing and the peak signal or the internal clock and outputting phase difference information. The VCO 105 is for synchronizing the clock phase. It is a voltage controlled oscillator. The output of the phase comparator 104 is V through the loop filter LF.
It is sent to the CO 105.

The TCXO 106 is an oscillator for generating an internal clock, and the frequency dividing circuit 107 is for adjusting the clock of the oscillator 105 to the code period frequency. In the frequency dividing circuit 107, the phase of the comparison signal generated by the internal clock is switched according to the load timing of the code frequency generating circuit 102.

The switch 108 is for switching the peak output of the frequency dividing circuit 107 and the matched filter 109, and the SAW matched filter 109 is a correlator for correlating the received spread signal. The output of the SAW matched filter 109 is output from the control circuit 101, the reset circuit 103, and the switch 1 via the filter Filter, the amplifier Amp, the detector Det, and the peak detector Peak.
08.

In FIG. 2, a signal 201 is a peak signal generated from the output of the matched filter 109 which is the correlation output of the correlator, and the rising edge indicates the peak position of the output of the matched filter. Also, the signals 202-2
Reference numeral 05 is a clock of the VCO 105, and signals 206 to 209.
Is a load timing signal, and signals 210 to 213 are code period frequency clocks after loading.

The specific operation of this embodiment will be described below.

First, when there is no received signal in the receiver, the control circuit 101 instructs the phase comparator 104 to use the switch 1 in order to make the comparison signal an internal clock.
08 is switched. Upon receiving this, the phase comparator 104 compares the phases of the outputs of the frequency dividing circuit 102 and the frequency dividing circuit 107, controls the VCO 105, and outputs the frequency dividing circuit 107.
The output of is synchronized.

Next, when the received signal is detected, the reset circuit 103 detects the peak signal 20 of the matched filter 109.
The rising edge of 1 is latched, and the rising timing of the inverted clock of the VCO 105 is used to generate the load timing of the frequency dividing circuit 102 and the frequency dividing circuit 107.
02, the frequency dividing circuit 107 and the control circuit 101. Also, when generating this signal, the VCO 105
When the falling edge of the clock is detected, the reset circuit 103 outputs an edge detection signal to the control circuit 101 before outputting the load timing signals 206 and 207.

Control circuit 101 receiving the edge detection signal
Sets to the frequency dividing circuit 102 and the frequency dividing circuit 107 a value obtained by adding 2 to the initial value for generating the spread code period frequency. The frequency dividing circuit 102 and the frequency dividing circuit 107 that have received this start counting from the initial value obtained by adding 2 according to the load timing output from the reset circuit 103.

If the reset circuit 103 does not detect the falling edge between the peak signal output 201 of the matched filter 109 and the generation of the load timing, the control circuit 101 instructs the frequency dividing circuits 102 and 107 to operate. Then, a value obtained by adding 1 to the initial value for generating the spread code period frequency is set, and the frequency dividing circuit 101 and the frequency dividing circuit 107 receiving this value start counting by the same operation as described above.

Next, the control circuit 101 which has received the load timing signal compares the peak signal output 201 of the matched filter 109 with the output of the frequency dividing circuit 107 and outputs L to each other.
At the time of reaching the OW level, a switching signal for switching the peak signal output 201 of the matched filter 109 to the one output to the phase comparator 104 is sent to the switch 108, and the peak signal output 201 of the matched filter 109 is monitored and received. The state of the switch 108 is held until it is detected that the signal disappears.

If it is detected that there is no received signal,
The control circuit 101 includes a frequency dividing circuit 102 and a frequency dividing circuit 10.
7, an initial value for generating the spread code period frequency is output, and then a load timing transmission instruction signal is output to the reset circuit 103. After that, the reset circuit 103
After receiving the load timing signal from the control circuit 101, the control circuit 101 maintains the state of the switch 108 until the correlation signal is detected again after switching the switch 108 to the internal clock side.

Further, the phase comparator 104 which receives the peak signal output 201 signal of the matched filter 109
Performs a phase comparison between the rising edge of the output of the frequency divider circuit 102 and the rising edge of the peak signal output 201 of the matched filter, and changes the control voltage of the VCO 105 to perform the clock phase pull-in operation from the approximate phase.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing this second embodiment.

In FIG. 3, a control circuit 301 is a circuit for controlling the initial value of a counter circuit that divides a clock, and switching the output of the matched filter and the output of the divider circuit 307. The code generator 302 generates a spreading code for demodulation by the VCO 305 clock that outputs the chip rate frequency of the spreading code, sends a code generation timing signal for each spreading code period, and switches the spreading code according to the reset timing.

The reset circuit 303 generates the reset timing of the code generator 302 and the load timing of the frequency divider circuit 307 from the correlation output of the matched filter 309 based on the clock of the VCO 305, and the reset generation timing and the clock phase relationship. It is a circuit that outputs the signal shown.

The phase comparator 304 is a phase comparator for performing phase comparison between the code generation timing signal output for each code cycle and the peak signal or the internal clock and outputting phase difference information. The VCO 305 is
A voltage controlled oscillator for clock phase synchronization.

The TCXO 306 is an oscillator for generating an internal clock, and the frequency dividing circuit 307 is a circuit for adjusting the clock of the oscillator 305 to the code period frequency. In the frequency dividing circuit 307, the phase of the comparison signal generated by the internal clock is switched according to the load timing of the code frequency generating circuit 302.

The switch 308 is for switching the peak output of the frequency dividing circuit 307 and the matched filter 309, and the SAW matched filter 309 is a correlator for correlating the received spread signal.

The specific operation of this embodiment will be described below.

First, when there is no received signal in the receiver, the control circuit 301 instructs the phase comparator 304 to use the switch 3 in order to make the comparison signal an internal clock.
08 is switched. Receiving this, the phase comparator 304 compares the phases of the code generation timing signal of the code generator 302 and the output of the frequency dividing circuit 307, and the VCO 30
5 is controlled to synchronize the output of the frequency dividing circuit 307.

Next, when the received signal is detected, the reset circuit 303 detects the peak signal 20 of the matched filter 309.
The rising edge of 1 is latched, the rising edge of the inverted clock of the VCO 305 is used to generate the code generation reset timing signal of the code generator 302 and the load timing of the frequency dividing circuit 307, and the code generator 302, the frequency dividing circuit 307 and the control are performed. Output to the circuit 301.

When this signal is generated, VC is already
When the falling edge of the O305 clock is detected,
Before outputting the reset timing signal and the load timing signal, the reset circuit 303 has the control circuit 301
An edge detection signal is output to.

Control circuit 301 which has received the edge detection signal
Adds 2 to the initial value for generating a control signal for the code generator 302 to generate from the code of the second chip of the spreading code and for the frequency dividing circuit 307 to generate the spreading code period frequency. Set the value.

Upon receipt of this signal, the code generator 302 receives the second signal of the spreading code for demodulation at the timing of the reset signal (however, this is not the only case, and the nth code chip generated by the code start timing signal To 2
It suffices that the code is generated from the chip after the chip), and the frequency dividing circuit 307 is the reset circuit 303.
The counting is started from the initial value obtained by adding 2 according to the load timing output from the.

If the reset circuit 303 detects no falling edge between the peak signal output 201 of the matched filter 309 and the generation of reset timing and load timing, the control circuit 301 determines that
A control signal for causing the code generator 302 to generate from the code of the first chip of the spread code, and the frequency dividing circuit 30.
For 7, the value obtained by adding 1 to the initial value for generating the spread code period frequency (similarly to the above, this is not limited to this, and for the nth code chip generated by the code start timing signal. A value for generating a code from the chip after one chip) is set. Code generator 30 receiving this
2 and the frequency dividing circuit 307 perform the same operation as described above.

Next, the control circuit 301 receiving the load timing signal compares the peak signal output of the matched filter 309 and the output of the frequency dividing circuit 307, and outputs the LO signal to each other.
At the time of reaching the W level, a switching signal for switching the peak signal output 201 of the matched filter 309 to the phase comparator 304 is sent to the switch 308, and the peak signal output of the matched filter 309 is monitored. The state of the switch 308 is maintained until the disappearance is detected.

If it is detected that there is no received signal,
The control circuit 301 outputs, to the code generator 302, an initial value for generating a spread code cycle frequency to the frequency division circuit 307 and a control signal to generate from the head code of the spread code, and then the reset circuit 303. To the load timing transmission instruction signal. Then reset circuit 3
Control circuit 30 which received the load timing signal from
After switching the switch 308 to the internal clock side,
The state of the switch 308 is held until the correlation signal is detected again.

Further, the phase comparator 304 which has received the peak signal output signal of the matched filter 309 compares the phase of the rising edge of the code generation timing signal of the code generator 302 with the rising edge of the peak signal output of the matched filter 309. , VCO 305 is changed to perform the clock phase pull-in operation from the approximate phase.

As described above, according to the embodiment of the present invention,
A stable VCO clock synchronized with an internal clock obtained by dividing the same spread code chip clock frequency in advance is used to generate a reset timing / load timing from the correlation peak and a phase relationship between the correlation peak and the chip rate clock. By detecting and controlling the code cycle clock generation timing according to the phase relationship, and by providing the phase comparator with means for switching from the internal code cycle clock to the correlation peak signal in the next cycle after the reset operation is completed, As soon as the signal is received and the correlation peak is obtained, the clock phase can be pulled in from within one chip, and the effect of speeding up the synchronization acquisition can be obtained.

Further, as a result, the synchronization preamble time at the start of communication can be shortened, and the throughput can be improved, and the system can be expanded flexibly when applied to the system. The effect of being considered is also obtained.

Furthermore, when the received signal detecting means determines that there is no received signal, by providing means for adjusting to the phase of the internal clock and the sampling clock or the code generation timing, the internal clock can be operated at high speed during reception standby. It becomes possible to synchronize with, and even if the burst period at the time of burst data reception can be shortened, it is possible to establish synchronization by a high-speed reset operation, and the preamble period can be shortened. The effect of expanding the flexibility of system construction can also be obtained by performing synchronization acquisition for each time.

In the above embodiment, the correlator is S
Although the AW matched filter is used, a digital matched filter may be used as well.

[0045]

As described above, according to the present invention,
By detecting the reception signal and the correlation signal by the matched filter and generating the clock phase switching timing for demodulating the reception signal by using the correlation signal, it is possible to reduce the time required for synchronization acquisition. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 101, 301 ... Control circuit, 102, 107, 307 ... Dividing circuit, 103, 303 ... Reset circuit, 104, 304 ... Phase comparator, 105, 305 ... VCO, 106, 306 ... TCXO, 108, 308 ... Switch, 109 , 309 ... Matched filter, 302 ... Code generator.

Claims (6)

[Claims] 1. A spread spectrum communication device using a matched filter, wherein a received signal and a correlation signal are detected by the matched filter and a clock phase switching timing for demodulating the reception signal is generated using the correlation signal. A reset synchronization method characterized by: 2. A phase comparator for comparing a phase difference between a code period signal and a correlation peak signal or an independent internal clock; and a demodulation of a received signal based on an output of the phase comparator. Clock generating means for generating a clock for generating a clock, and first control means for using the internal clock as a phase comparison signal of the phase comparator when there is no received signal; the clock phase switching timing and the code Second control means for detecting the phase relation of the periodic signals and controlling the generation timing of the code period signal according to the phase relation; from the internal clock to the correlation peak signal in the next period after the reset operation is completed. Third control means for switching; fourth control means for adjusting the phase of the internal clock to the generation timing of the code period signal when there is no received signal Reset synchronization circuit characterized in that it comprises a. 3. The spread spectrum communication device according to claim 1, wherein a SAW matched filter is used as the matched filter. 4. The spread spectrum communication device according to claim 1, wherein a digital matched filter is used as the matched filter. 5. The spread spectrum communication device according to claim 1 or 2, wherein a voltage controlled oscillator is used as the demodulation clock generation means. 6. The spread spectrum communication device according to claim 1, wherein a crystal oscillator is used as the means for generating the internal clock.