JPH0969801A - Spread spectrum communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep spread code phase deviation within one clock by detecting a time difference by a time difference detecting means while using a clock having the opposite phase of a clock generated from a clock generating means. SOLUTION: When a received signal and a reference signal are inputted to a convolver 111 in the same code phase, a correlation peak appears at the intermediate point between the time point, when the received signal and the reference signal are to be inputted to the convolver 111, and an input time point. In opposition to this, when the received signal and the reference signal are inputted to the convolver 111 in different code phases, the correlation peak appears at the intermediate point of a code top between the received signal and the reference signal. Therefore, the time from the leading CG-START signal of a reference code to the correlation peak is measured and after the elapse of measured time, that point of time becomes the leading position of the received signal. At such a time, as the time from the CG-START signal of the reference code to the correlation peak when the inverted clock of the clock of a VCO 106 is used, the time measurement error becomes within 1/2 of a clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication device, and more particularly, to a synchronization system and a synchronization circuit thereof.

[0002]

2. Description of the Related Art Conventionally, in the case of performing synchronization acquisition in a spread spectrum communication apparatus, a sliding correlation synchronization method is generally used in which the same spread code as a received spread signal is slid to perform synchronization acquisition.

Further, in the case of performing code and clock synchronization using a correlator such as a SAW convolver, for example, Japanese Patent Application No. 63-287099 (JP-A-2-13293).
No. 5), the phase comparison of the correlation peak and the reference spread code generation timing signal is performed by the phase comparator, and the clock phase output from the voltage controlled oscillator (hereinafter referred to as VCO) is determined according to the phase difference information. It is configured to shift and perform synchronous acquisition / holding.

Further, in order to shorten the synchronization acquisition time,
For example, as disclosed in Japanese Patent Application No. 6-332714,
A method of performing synchronization acquisition in the same manner as described above by using a means for generating convolution output and reference spread code generation timing for each 1/2 cycle of the code cycle, and Japanese Patent Application No. 63-28.
No. 7101 (JP-A-2-132937), the time difference between the convolution output and the reference code generation timing is measured, and in the next reception code cycle,
A method of resetting the code generator is also known.

[0005]

However, in the above-mentioned conventional example, the method using sliding correlation has a problem that the synchronization acquisition time is long in the case of a sequence having a long extension code length.

Also in the case of the method using the matched filter, a phase locked loop (hereinafter, P
It is difficult to significantly reduce the pull-in time due to the relationship between the lock-up time (referred to as LL) and the jitter, and particularly in the case of communication by burst reception, the preamble period for acquisition of synchronization becomes large and the throughput is reduced. There was a problem.

Further, when the conventional reset synchronization method for shortening the synchronization acquisition time is used, the method and means for measuring the time difference between the convolution output and the reference code generation timing have not been clarified. . It should be noted that the accuracy of the time difference measurement can be improved by using a high-speed clock, but in that case, a high-speed clock is required in addition to the code generation clock,
There is a problem that the number of parts increases.

It is an object of the present invention to provide a spread spectrum communication device capable of performing efficient synchronization acquisition with a simple structure without impairing the synchronization performance.

[0009]

DISCLOSURE OF THE INVENTION The present invention provides code generation means for generating a spread code sequence used for communication, code generation timing generation means for generating code generation timing in the code cycle of the spread code sequence, and the above code. A clock generating means for generating a clock for driving the generating means, a correlating means for correlating a received signal, a phase comparison between an output of the correlating means and a timing signal having a frequency twice the code period, and synchronously capturing. In a spread spectrum communication device, there is provided a synchronization means for performing, a time difference detection means for detecting a time difference between the output of the correlation means and the timing signal of the code period, and a code reset timing generation means for generating a code reset timing according to the time difference. Therefore, the time difference detection means uses a clock having a phase opposite to that of the clock generated from the clock generation means. And detecting a time difference.

The present invention has a code generation means, a code generation timing generation means, a correlation means (for example, a SAW convolver), a synchronization means, a time difference detection means, and a code reset timing generation means. The time difference between the output and the timing signal of the code cycle is measured by using a clock having a phase opposite to that of the clock for driving the code generating means, so that one time resetting is possible without separately preparing a high-speed clock. Since the input signal and the reference spreading code and the demodulating spreading code generated inside the receiver can be suppressed to have a phase shift within one clock, the number of components can be reduced without impairing the synchronization performance.

In addition, by performing synchronization acquisition for each burst reception when performing data communication in bursts, the effect of expanding the flexibility of system construction can be obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, a control circuit 101 controls the convolution output mask timing, reset timing, etc., and the mask circuit 102
The convolution peak is masked if necessary. The code generation circuit 103 is a circuit for generating a reference spread code and a demodulation spread code, and in the spread code, a code start signal (hereinafter, CG-ST) for notifying a specific timing (for example, the head) of the spread code.
An ART signal is generated, and a timing signal (hereinafter, referred to as a CG-START2 signal) is generated every ½ cycle of the code (for example, the head and the middle of two heads).

The phase comparison circuit 104 is a circuit for detecting the reset timing, and the reset circuit 105.
Is a circuit that measures the time difference between the peak signal and the code generation timing from the comparison output of the phase comparison circuit 104, and generates the reset timing signal according to this time difference.

Voltage controlled oscillator (hereinafter referred to as VCO) 1
Reference numeral 06 is an oscillator for clock phase synchronization.
The oscillator 107 is an oscillator for generating an internal clock, and the frequency divider 108 is for adjusting the clock of the oscillator 107 to the code period.

In the frequency divider 108, the phase of the comparison signal generated by the internal clock is switched according to the reset timing of the code generator 103 and the reset timing generated by the code generation timing.

The switch 109 switches between the output of the frequency divider 108 and the output of the mask circuit 102. The phase comparator 110 compares the code generation timing with the phase of the peak signal or the internal clock to obtain the phase difference information. Is output. The correlator 111 is for correlating with the received spread signal, for example, SAW.
It is a convolver.

2 to 4 are time charts showing the operation of this embodiment.

In FIG. 2, 201 is a convolution output which is a correlation output of the correlator 111, and 202
Is the masked convolution output. FIG.
In the figure, reference numeral 301 denotes a signal masked by the mask circuit 102, and the rising edge indicates the peak position of the convolution output.

Reference numeral 302 is a CG-START2 signal output every 1/2 cycle, and 303 is a CG-START signal output every code cycle. The rising edge of each of these two signals indicates a specific timing of the code. 304 is a reset signal indicating the reset timing of the code generator. The actual operation in this embodiment will be described below.

First, when there is no received signal in the receiver, the control circuit 101 switches the switch 109 to the phase comparator 110 so that the comparison signal becomes an internal clock. Receiving this, the phase comparator 110 receives the CG-START2 signal 302 and the frequency divider 1
08 output phase comparison, controlling VCO 106,
The output of the frequency divider 108 is synchronized.

Next, when the received signal is detected, the control circuit 1
01 is the convolution output 301 and the CG-START signal 30 output from the phase comparison circuit 104.
Wait for the comparison result signal of 3. Then, when the comparison result is equal to or larger than the desired phase difference (for example, one code chip), the operation instruction signal is output to the reset circuit 105.

On the other hand, when the phase comparison result of the phase comparison circuit 104 is within the desired phase difference, the clock synchronization instruction signal is output to the control circuit 101. Receiving this, the control circuit 101 does not output the operation instruction signal to the frequency dividing circuit 108 and the reset circuit 105, and switches the input of the switch 109 to the one in which the correlation peak is output.

Reset circuit 105 which has received the operation instruction signal
Waits until the next CG-START signal 303 arrives, and when the CG-START signal 303 is obtained, the VCO
The count up is started using the inversion clock of the clock 106, and the time until the convolution output 301 comes is measured.

When the convolution output 301 is received, the counter in the reset circuit 105 is down-counted, and after the lapse of the same time, the reset signal 304 is output to the code generator 103 and the frequency divider 108. Upon receiving this reset signal 304, the code generator 103 starts code generation from the reference spread code and the demodulation spread code at the head or from a preset code generation position according to this timing.

Further, the frequency divider receiving the reset signal 304 starts the frequency division again according to this timing, and when an edge appears at the frequency division start position, in order to prevent malfunction of the phase comparator 110, the edge information Is masked and the comparison edge is output from the next cycle.

In the reset circuit 105 which outputs the reset signal 304, depending on the reset timing, the convolution output 301 and the C signal are output within ± 1 code chip clock.
Whether or not the G-START signal 303 is input is detected in the next cycle, and if it is not within ± 1 chip, a series of reset operations are repeated again.

If the signals are input within ± 1 chip, the reset operation completion signal is output to the control circuit 101. Upon receiving this, the control circuit 101 outputs a switching control signal for switching the output of the switch 109 to the convolution output. This causes the phase comparator 110 to output the convolution output 201.
The peak information and the CG-START2 signal are input, and the operation shifts to the clock synchronization acquisition operation. In the clock synchronization acquisition operation, the control voltage of the VCO 106 is controlled by the phase difference information of these two input signals to control the clock phase, as in a normal PLL.

When the phases match and the synchronization acquisition ends, a synchronization acquisition completion signal is output to the demodulation circuit (not shown), and a series of synchronization acquisition operations ends. Further, when the reception burst signal disappears, the control circuit 101 resets the frequency divider 108 in synchronization with the code generation timing, and acquires synchronization with the internal clock in the approximate phase.

The code resetting operation will be described in more detail with reference to FIG. It should be noted that here, in order to simplify the description, the delay in each circuit is ignored. In addition, the integration length of the convolver 111 is 1
The number of cycles. In the figure, the received signal and the reference signal are two signals input to the convolver 111,
Each oval represents one cycle of the code.

The reference signal is a signal emitted from the code generator 103 driven by the clock from the VCO 106 and converted into an appropriate frequency. When the received signal and the reference signal are input to the convolver 111 with exactly the same code phase (symbol synchronization is established), the correlation peak is the time when the received signal and the reference signal are input to the convolver 111 and the input time. Appears at the midpoint of.

On the other hand, the received signal and the reference signal are
When the signals are input to the convolver 111 with different code phases (code synchronization is not established), a correlation peak appears at the midpoint between the code head of the received signal and the reference signal. Therefore, the time from the head CG-START signal of the reference code to the correlation peak CONV is measured, and the time point after which the same time as the measured time has elapsed is the head position of the received signal.

At this time, the inversion clock of the clock of the VCO 106 is used to start the reference code CG-START.
When the time from the signal 303 to the correlation peak CONV301 is measured, the reference CG-START signal 30
Since 3 is driven by the VCO 106 clock,
The time measurement error is within 1/2 clock.

Then, after that, when the reset timing is obtained by the down count, the error is within one clock.

FIG. 5 is a block diagram showing a configuration for sampling and holding the voltage for controlling the VCO 106 in the data receiving period as the second embodiment of the present invention.

In FIG. 5, the sample hold means (S
/ H) 112 is a means for sampling and holding the control voltage information of the VCO 106, and is, for example, a sample hold IC. In addition, as a means for holding this voltage information, a method using an A / D converter D / A converter or a method using a reference voltage source can be used. In the following, differences of the present embodiment from the first embodiment will be described.

In the case of a signal in which burst data is multiplexed, the correlation peak may not be correctly extracted due to the influence of cross-correlation. So, in the preamble period,
After performing the reset operation similar to that of the first embodiment, the control circuit 101 outputs the voltage hold instruction signal to the sample and hold means 112 and the switch 10
A switching signal to the internal clock output from the frequency divider 108 is sent to 9 and the reception signal detection circuit (not shown) waits for a reception completion signal.

Upon receiving the reception completion signal, the control circuit 101 outputs a reset signal generated at the code generation timing to the frequency divider 108 to approximate the code generation timing and the phase of the internal clock. , The hold release signal is output to the sample hold means 112, and the internal clock and the code generation timing (CG-STA
The phase comparison of the RT2 signal 302) is performed by the phase comparator 110, and the next reception signal is awaited.

[0039]

As described above, according to the present invention,
At the time when the received wave is detected, first, when performing the reset operation by detecting the phase difference between the correlation output and the code generation timing,
By measuring the time using the clock of the opposite phase of the clock that drives the code generator, the input signal and the reference diffusion generated inside the receiver can be performed by one reset operation without preparing a high-speed clock separately. Since the code and the spread code for demodulation can be suppressed to have a phase shift within one clock, the number of components can be reduced without impairing the synchronization performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the first embodiment.

FIG. 3 is a time chart showing the operation of the first embodiment.

FIG. 4 is a time chart showing the operation of the first embodiment.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 101 ... Control circuit, 102 ... Mask circuit, 103 ... Code generation circuit, 104 ... Phase comparison circuit, 105 ... Reset circuit, 106 ... Voltage controlled oscillator, 107 ... Oscillator, 108 ... Divider, 109 ... Switch, 110 ... Phase Comparator, 111 ... Correlator.

Claims (5)

[Claims] 1. Code generation means for generating a spread code sequence used for communication; code generation timing generation means for generating code generation timing at a code cycle of the spread code sequence;
Phase comparison is performed between the clock generating means for generating the clock for driving the code generating means, the correlating means for correlating the received signal, and the output of the correlating means and the timing signal having a frequency twice the code period. Spread spectrum communication having synchronization means for performing synchronization acquisition, time difference detection means for detecting a time difference between the output of the correlation means and the timing signal of the code period, and code reset timing generation means for generating a code reset timing according to the time difference. A spread spectrum communication device, wherein the time difference detecting means detects the time difference using a clock having a phase opposite to that of the clock generated from the clock generating means. 2. The non-modulation signal transmitting means for transmitting a data non-modulation spread spectrum signal with a preamble period provided at the start of data transmission, wherein the reference spread code is transmitted without data modulation. By so doing, a spread spectrum communication device characterized by obtaining a correlation output having a frequency twice the spread code period. 3. The spread spectrum communication device according to claim 1, wherein the clock generating means is voltage controlled oscillating means. 4. A spread spectrum communication device according to claim 1, wherein a SAW convolver is used as the correlating means. 5. The time difference detection means and the code reset timing generation means according to claim 1, wherein the time difference detection means and the code reset timing generation means output from the correlation means from a time period until a desired time after the code reset timing is generated. A spread spectrum communication device comprising means for masking a part of the output.