JPH0865204A - Synchronization acquisition system - Google Patents

Abstract

PURPOSE: To eliminate the fluctuation due to a temperature and an elapsed time and the dispersion among products by shifting a phase in the unit of tips so as to retrieve a phase matching point thereby eliminating the fluctuation in a clock signal in the case of transition from the acquisition of synchronization to synchronization tracking and thereby improving the synchronization tracking performance and controlling digitally a phase shift of a PN signal so as to warrant a constant phase shift at all times. CONSTITUTION: A gate control signal pulse is outputted at each time interval sufficient to take the correlation between a reference PN signal and a received signal in the case of a synchronization state of a PN signal synchronization circuit so as to stop tentatively a clock signal of a voltage controlled clock generating circuit 12 thereby stopping the supply of the clock signal to a PN signal generator 14 tentatively resulting in shifting the phase of the reference PN signal. A phase comparator circuit 10 detects a phase matching point by taking the correlation while shifting the phase of the reference PN signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization acquisition system, and more particularly to synchronization acquisition of a synchronization circuit in spread spectrum communication.

[0002]

2. Description of the Related Art In spread spectrum communication, a transmission system spreads an information signal by a pseudo noise signal (hereinafter referred to as a PN signal) in a transmission system and transmits it, and a reception system receives this signal. , PN used in the transmission system
It is a communication method in which information is demodulated by despreading with the same PN signal as the signal. In this communication system, in the receiving system,
In order to despread the received signal and take out the information signal, it is necessary to generate a PN signal that is synchronized with the PN signal contained in the received signal. Therefore, normally, a PN signal synchronizing circuit using feedback control is used.

In a PN signal synchronizing circuit, the PN signal in the received signal is usually referred to by using the correlation between the PN signal generated by the PN signal synchronizing circuit (hereinafter referred to as a reference PN signal) and the received signal. The phase difference from the PN signal is detected. For example, a non-coherent delay locked loop, which is a generally known PN signal synchronization circuit, utilizes the phase comparison characteristic shown in FIG.

However, as can be seen from FIG. 10, the synchronizing circuit utilizing the autocorrelation characteristic of the PN signals can follow the synchronization only in the range where the phase difference between the PN signals is constant. For this reason, when the synchronization is first acquired, or when the synchronization is lost, the P in the received signal is up to the range in which the synchronization can be followed.
It is necessary to narrow the phase difference between the N signal and the reference PN signal.
Therefore, a circuit for acquiring synchronization is added to the normal PN signal synchronization circuit.

FIG. 4 is a diagram showing a conventional example of synchronization acquisition. In the figure, 10 is a phase comparison circuit, which is a circuit for phase comparison between a PN signal in a received signal and a reference PN signal. 11
Is a loop filter (LF), and is a filter for removing the noise component of the phase error signal from the phase comparison circuit 10. Reference numeral 12 denotes a voltage control clock (VCC) generation circuit, which generates a clock signal having a frequency according to the input control signal. Reference numeral 14 denotes a PN signal generation circuit (PNG), which is a circuit for generating a reference PN signal by the clock from the voltage control clock generation circuit 12. Also, 30
Is a signal switching circuit, 40 is a constant voltage generating circuit, and 13 is a control circuit for controlling the switching circuit 30 according to the synchronization / asynchronization of the synchronization circuit.

In the asynchronous state, the switching circuit 30 is closed to the constant voltage generating circuit 40 side, and the voltage control clock generating circuit 1
A control signal having a constant voltage is added to 2 to shift the reference PN signal with respect to the PN signal in the received signal. When the phase difference becomes small, a correlation output is obtained and the synchronization detection signal from the phase comparison circuit 10 is detected. The control circuit 13 closes the switching circuit 30 to the low-pass filter 11 side by the synchronization detection signal and starts the synchronization tracking.

The signal from the voltage control clock generation circuit 12 is switched between a signal divided by N ₁ and a signal divided by N ₂ to switch to PN.
As prior arts that are common to only inputting to a signal generator (claim 3), there are "JP-A-5-199205", "JP-A-5-219012", and "JP-A-5-22712".
1 ”,“ JP-A-5-235897 ”and the like (particularly“ JP-A-5-235897 ”), but these are synchronous spread spectrum communication (Coherent Spread Spectum communicati).
on), a local oscillation signal of an intermediate frequency is switched between a synchronous state and an asynchronous state, and this is used as a clock signal of a PN signal generator.

[0008]

As described above, in the conventional PN signal synchronizing circuit, the phase of the reference PN signal is added by adding an offset voltage to the control signal of the voltage control clock in order to obtain the initial synchronization of the PN signal. Was shifted to search for a phase matching point. However, this system has a problem in that, when the control signal is switched from the offset voltage to the phase error signal from the phase comparison circuit immediately after the synchronization is acquired, the clock frequency of the voltage control clock fluctuates and the synchronization is lost. Further, since the conventional method is composed of an analog circuit, there is a problem that the shift amount at the time of phase search of the PN signal varies with temperature and time, and also varies among products.

[0009]

In order to solve the above problems, the present invention provides (1) a sufficient time for detecting the correlation between a received signal and a reference PN signal when the PN signal synchronizing circuit is in an asynchronous state. At every interval, the clock signal of the voltage control clock generation circuit that drives the reference PN signal generation circuit is temporarily stopped, and the phase of the reference PN signal is shifted with respect to the PN signal in the received signal to obtain a phase matching point. Or (2) voltage control input to the reference PN signal generation circuit at sufficient time intervals to detect the correlation between the received signal and the reference PN signal when the PN signal synchronization circuit is in the asynchronous state. Searching for a phase matching point by temporarily stopping the supply of the clock signal of the clock generation circuit and shifting the phase of the reference PN signal with respect to the PN signal in the received signal; or Is (3) referred to in PN signal synchronizing circuit synchronizing state, N ₁ divided from the voltage controlled clock generator circuit (N ₁ is a natural number) by the clock signal P
Drives the N signal generation circuit performs synchronization maintenance of the reference PN signal, the PN signal synchronization circuit is an asynchronous state, N ₂ divided from the voltage controlled clock generator (N ₂ is a natural number and N ₁ ≠ N ₂₎ The reference PN according to the generated clock signal.
Signal to drive the phase of the reference PN signal to P in the received signal.
The phase matching point is searched for by shifting with respect to the N signal, or (4) when the PN signal synchronizing circuit is in the synchronous state, the reference PN signal is generated by the N ₁ -divided clock signal from the voltage control clock generating circuit. The generation circuit is driven to maintain the synchronization of the reference PN signal, and when the PN signal synchronization circuit is in the asynchronous state, at a sufficient time interval for detecting the correlation between the received signal and the reference PN signal, the aforesaid fixed time is applied. The reference PN signal is driven by the clock signal divided by N ₂ from the voltage control clock generation circuit, and the phase of the reference PN signal is shifted with respect to the PN signal in the received signal to search for a phase matching point. Further, (5) In (1) to (3), the 1Δ type delay lock loop is used in the PN signal synchronizing circuit, To search for a phase matching point by shifting the phase fluctuation amount of the reference PN signal by two chips at sufficient time intervals for detecting the correlation between the reference PN signal and the reference PN signal, or (6) above (1), In (2) or (4), a difference is generated between the chip speed of the reference PN signal and the chip speed of the PN signal in the received signal when asynchronous,
The feature is that the phase matching point is searched.

[0010]

The clock signal at the time of shifting from synchronization acquisition to synchronization tracking by shifting the phase on a chip-by-chip basis and searching for a phase matching point instead of shifting the phase of the reference PN signal by changing the clock frequency. To improve the synchronization tracking characteristic. Also, digitally P
By controlling the amount of phase shift of the N signal, a constant amount of phase shift is always guaranteed, and fluctuations due to temperature and the passage of time, variations between products, etc. are eliminated.

[0011]

【Example】

Embodiment 1 (corresponding to claim 1) FIG. 1 is a diagram for explaining one embodiment of the present invention. In FIG. 1, parts having the same functions as those of the prior art shown in FIG. The same reference numerals are attached as in the case. Thus, in this embodiment, when the PN signal synchronizing circuit is in the asynchronous state, a pulse-shaped gate control signal (see FIG. 7 (c) is generated at every sufficient time interval for correlating the reference PN signal and the received signal. )
(See FIG. 7) to temporarily stop the clock signal (see FIG. 7A) of the voltage control clock generation circuit 12 (see FIG. 7D). As a result, the clock supply to the PN signal generator 14 is stopped for one hour, and the phase of the reference PN signal is shifted. In this way, in the asynchronous state, the phase coincidence point can be detected by performing correlation while shifting the phase of the reference PN signal. Here, the time interval for obtaining the correlation is simple with reference to, for example, one cycle of the PN signal, or a fraction thereof, the data length time of the information signal, the time when the clock of the voltage control clock is counted, or the like. Can be

FIG. 7 shows a timing chart of this embodiment. In this example, the gate control signal (see FIG. 7 (c))
Pulse width of the voltage control clock (see FIG. 7 (a))
The width of the clock is set, and one shift amount of the reference PN signal is one chip (a chip is a unit of one symbol of the PN signal). FIG. 7A shows a clock signal of the voltage control clock, and FIG. 7B shows a synchronization detection signal from the phase comparison circuit. In this example, it is ON when asynchronous and OFF when synchronizing.
(See FIG. 7B). Figure 7
(C) is a gate control signal, which periodically generates a pulse signal when the synchronization detection signal is ON. Figure 7
(D) is a clock signal input to the PN signal generation circuit. The clock signal stops every time the gate control circuit is turned on.

Embodiment 2 (corresponding to claim 2) Further, the voltage control clock generation circuit 12 is stopped by the gate control signal (see FIG. 7C), and the oscillation of the voltage control clock generation circuit 12 is started again. In this case, it may take time for the voltage control clock generation circuit 12 to rise. Example 2 is an improvement of this point.
FIG. 2 shows an example of the circuit. In FIG. 2, reference numeral 20 denotes a switch circuit. In this embodiment, the voltage control clock generation circuit 1 is turned off by turning off the switch circuit 20 with a gate control signal (see FIG. 7C) from the control circuit 13.
The control of the voltage control clock generated in 2 eliminates the fluctuation of the clock signal.

Embodiment 3 (corresponding to claim 3) Next, as another embodiment in which the voltage control clock signal is controlled by the gate control signal to shift the phase of the reference PN signal, the frequency division ratio of the clock signal is gated. A method of controlling with a control signal will be described. FIG. 3 is a diagram showing an embodiment thereof, in which 31 and 32 are frequency dividers, which divide the voltage control clock signal (FIG. 8 (a ')) into N ₁ and N ₂ respectively (see FIG. 8
(D ')) Here, N ₁ and N ₂ are natural numbers, and N ₁ and N ₂ are different frequency division ratios. A switching circuit 30 switches the signals from the frequency divider 31 and the frequency divider 32 to P
Input to the N signal generation circuit.

FIG. 8 shows that N ₁ =
1 is a diagram showing a timing chart of N ₂ = 2. In this case, the switching circuit 30 is operated by a synchronization detection signal (see FIG. 8C ').
Can be directly controlled, and when the synchronization detection signal is ON, a signal obtained by dividing the clock signal by two (see FIG. 8B ') is input to the PN signal generation circuit 14, and when it is OFF, the clock signal remains unchanged. input. Thereby, the phase of the reference PN signal can be shifted. By using this, the pulsed gate control signal (see FIG. 7B) required in the first and second embodiments becomes unnecessary.

Fourth Embodiment (corresponding to claim 4) Further, when the circuit of FIG. 3 is used, the gate control signal is converted into a pulse signal (see FIG. 9 (d ″)) as in the first and second embodiments. By doing so, the voltage control clock generation circuit 12
It is possible to temporarily stop the input signal (see FIG. 9 (e ″)) to the chip and shift the phase of the reference PN signal on a chip-by-chip basis. In this example, the phase is shifted by setting N ₁ = 1 and N ₂ = 2 and delaying the reference PN signal by 1 chip. Conversely, the phase of the reference PN signal is advanced to shift the phase. To do so, N ₁ > N ₂ may be set.

Embodiment 5 (corresponding to claim 5) In the above description, the shift amount of the reference PN signal is shifted by one chip for each synchronization determination, but this shift amount is determined by the PN signal synchronizing circuit. It may be determined according to the phase difference detection range. For example, in the 1Δ type delay locked loop, the phase comparison circuit 10 can output a phase error signal up to a phase difference of ± 3/2 chips as shown in FIG. For this reason,
In the 1Δ type delay locked loop, as shown in FIG. 5, the shift amount may be shifted by two chips.

FIG. 5 is an electric circuit diagram for explaining the operation of this embodiment. In the figure, a portion 1 surrounded by a dotted line square is shown.
Reference numeral 0 denotes a phase comparison circuit, which is a correlator composed of a multiplier 50 and a bandpass filter 52, and a correlator composed of a multiplier 51 and a bandpass filter 53.
The correlation between the y) signal, the late signal and the received signal is obtained, and the difference is subtracted by the subtractor 55 to obtain the signal shown in FIG.
The phase comparison characteristic shown in 0 is realized. In addition, in FIG. 5, the synchronization detection signal is generated by adding the outputs of the two correlators by the adder 54. Furthermore, FIG.
Shows a special case where the frequency division ratio of the third embodiment is N ₁ = 1 and N ₂ = 0, and shows a case where the switch circuit 20 is used instead of the frequency divider. By turning off the switch circuit 20 for 2 clocks by the gate control signal, the shift amount of the PN signal can be shifted by 2 chips.

Embodiment 6 (corresponding to claim 6) In the present invention, as described above, (1) the reference PN signal is shifted, and (2) the phase of the reference PN signal at that time is the PN signal in the received signal. It can be said that this is a method of searching at the phase matching point by repeating the operations (1) and (2) of checking whether or not the synchronization can be followed. Therefore, when the amount of shift of the phase of the reference PN signal once is increased, the phase may be shifted by skipping the phase difference range in which synchronization tracking is possible, and the phase matching point may not be found. In this case, in the asynchronous state, the reference PN signal and the PN signal in the received signal may be given a clock frequency difference to search for the phase matching point. Specifically, as shown in FIG. 6, an offset voltage is added to the phase error signal from the phase comparison circuit 10 to obtain a control signal for the voltage control clock generation circuit 12. As a result, it is possible to check the possibility of synchronization tracking in the phase of the reference PN signal that has not been searched, and it is possible to acquire synchronization.

[0020]

As is apparent from the above description, the present invention has the following effects. According to the present invention, instead of changing the clock frequency to shift the phase of the reference PN signal, the phase is shifted on a chip-by-chip basis to search for a phase matching point. The fluctuation of the clock signal is eliminated when shifting to the synchronous tracking, and the synchronous tracking characteristic can be improved. In addition, since the phase shift amount of the PN signal is digitally controlled, a constant phase shift amount is always guaranteed, and as a result, fluctuations due to temperature or elapsed time, variations between products, etc. are eliminated. [Effect of Claim 2] Since the clock signal input to the PN signal generating circuit is controlled by the switch circuit, fluctuations of the clock signal due to control of the voltage control clock can be eliminated. [Effects of Claim 3] Since the phase of the reference PN signal is shifted by switching between two different divided clock signals, the gate control signal can be generated by a simple circuit. [Effect of Claim 4] Since two different divided clock signals are controlled by the gate control signal and input to the PN signal generating circuit, not only the phase of the reference PN signal is delayed but also the phase is advanced. it can. [Effect of Claim 5] Since the phase shift amount of the reference PN signal is set to 2 chips by using the 1Δ type delay lock loop, the synchronization can be surely performed and the synchronization acquisition time can be shortened. [Effect of Claim 6] Since not only the phase of the reference PN signal is shifted but also the clock frequency is changed to perform the synchronization acquisition, not only the 1Δ type delay lock loop but also a general PN signal synchronization circuit is used. The synchronization acquisition time can be shortened.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram for explaining an embodiment (claim 1) of the present invention.

FIG. 2 is an electric circuit diagram for explaining another embodiment (claim 2) of the present invention.

FIG. 3 is an electric circuit diagram for explaining another embodiment (claims 3 and 4) of the present invention.

FIG. 4 is an electric circuit diagram for explaining an example of a conventional synchronization acquisition method.

FIG. 5 is an electric circuit diagram for explaining another embodiment (claim 5) of the present invention.

FIG. 6 is an electric circuit diagram for explaining another embodiment (claim 6) of the present invention.

FIG. 7 is a timing chart for explaining the operation of the first and second embodiments.

FIG. 8 is a timing chart for explaining the operation of the third embodiment.

FIG. 9 is a timing chart for explaining the operation of the fourth embodiment.

FIG. 10 is a diagram showing a phase comparison characteristic of a delay locked loop.

[Explanation of symbols]

10 ... Phase comparator circuit, 11 ... Low-pass filter, 12 ...
Voltage control clock generation circuit, 13 ... Control circuit, 14 ... Pseudo noise signal generation circuit, 20, 30 ... Switch circuit, 3
1, 32 ... Frequency divider circuit, 40 ... Constant voltage generation circuit, 50, 5
1 ... Multiplier, 52, 53 ... Band pass filter, 54 ...
Adder, 55 ... Subtractor.

Claims (6)

[Claims] 1. A clock of a voltage control clock generation circuit for driving a reference PN signal generation circuit at a sufficient time interval for detecting a correlation between a received signal and a reference PN signal when the PN signal synchronization circuit is in an asynchronous state. A synchronization acquisition method characterized by searching for a phase matching point by temporarily stopping the signal and shifting the phase of the reference PN signal with respect to the PN signal in the received signal. 2. The voltage control clock generation circuit input to the reference PN signal generation circuit at every sufficient time interval for detecting the correlation between the received signal and the reference PN signal when the PN signal synchronization circuit is in the asynchronous state. The supply of the clock signal is temporarily stopped, and the phase of the reference PN signal is set to the PN in the received signal.
A synchronization acquisition method that searches for a phase matching point by shifting the signal. 3. The PN signal synchronizing circuit is in a synchronized state,
N ₁ divided from the voltage controlled clock generator circuit (N ₁ is a natural number) drives the reference PN signal generating circuit by the clock signal, performs synchronization maintenance of the reference PN signal, PN signal synchronization circuit in an asynchronous state, the N ₂ divided from the voltage controlled clock generator (N ₂ is a natural number and N ₁ ≠ N ₂₎ driving the reference PN signal by clock signals,
A synchronization acquisition method characterized in that the phase matching point is searched by shifting the phase of the reference PN signal with respect to the PN signal in the received signal. 4. The PN signal synchronizing circuit in a synchronized state,
The reference PN signal generation circuit is driven by the clock signal divided by N ₁ from the voltage control clock generation circuit, and the reference P
When the PN signal synchronizing circuit maintains the N signal in synchronism and the PN signal synchronizing circuit is in the asynchronous state, the voltage control clock generating circuit outputs the voltage control clock generating circuit from the voltage control clock generating circuit at a time interval sufficient for detecting the correlation between the received signal and the reference PN signal. Synchronization acquisition characterized in that the reference PN signal is driven by a clock signal divided by N ₂ and the phase of the reference PN signal is shifted with respect to the PN signal in the received signal to search for a phase matching point. method. 5. Claim 1 or claim 2 or claim 3.
In the above, by using a 1Δ type delay lock loop in the PN signal synchronizing circuit, by shifting the phase fluctuation amount of the reference PN signal by 2 chips at every sufficient time interval for detecting the correlation between the received signal and the reference PN signal. A synchronization acquisition method characterized by searching for phase matching points. 6. The method according to claim 1, claim 2 or claim 4.
In step 1, a synchronization acquisition method is characterized by generating a difference between the chip speed of the reference PN signal and the chip speed of the PN signal in the received signal at the time of non-synchronization to search for a phase matching point.