JPH0964273A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0964273A
JPH0964273A JP7242324A JP24232495A JPH0964273A JP H0964273 A JPH0964273 A JP H0964273A JP 7242324 A JP7242324 A JP 7242324A JP 24232495 A JP24232495 A JP 24232495A JP H0964273 A JPH0964273 A JP H0964273A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
signal line
external signal
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7242324A
Other languages
Japanese (ja)
Other versions
JP3947239B2 (en
Inventor
Takashi Nakayama
高志 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP24232495A priority Critical patent/JP3947239B2/en
Publication of JPH0964273A publication Critical patent/JPH0964273A/en
Application granted granted Critical
Publication of JP3947239B2 publication Critical patent/JP3947239B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Endoscopes (AREA)

Abstract

PROBLEM TO BE SOLVED: To materialize the downsizing without marring the strength of a board, and perform the incorporation into a microunit with accuracy and good work efficiency by providing the periphery of a board with an incline which reduces the thickness. SOLUTION: In the mirror frame 11 of the tip unit of an electron endoscope, one end of the substrate 21 of a semiconductor device is connected by soldering to one terminal 13 of a package 21 such as a solid-state image pickup element, or the like, and one end of an external signal line 15 is connected by soldering to the chip part of the semiconductor device, and the other hand is connected by soldering to the other terminal 14 of the package 12. At that time, since a chamfered part 22 is made at the substrate 21 constituting the semiconductor device, it can be thinned substantially without marring the strength of the substrate 21, and the degree of the interference with the mirror frame 11 of the external signal line 15 becomes small, and the routing of the external signal line 15, and others can be performed smoothly, and the incorporation into the microunit can be performed accurately and besides with good work efficiency.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、半導体装置に関
し、特に電子内視鏡の先端部等の微小ユニット内に組み
込まれて用いられる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device incorporated and used in a minute unit such as a tip portion of an electronic endoscope.

【0002】[0002]

【従来の技術】従来、電子内視鏡の先端部等の微小ユニ
ット内に組み込まれる半導体装置としては、例えば特開
昭63−308954号公報には、図6に示すような構
成のものが開示されている。すなわち、図6において、
1は基板で、該基板1上にはICチップ2がボンディン
グワイヤ3で接続され、封止樹脂4で封止して搭載され
ており、また基板1には抵抗やコンデンサ等のチップ部
品5が接続されて搭載され、半導体装置6を構成してい
る。
2. Description of the Related Art Conventionally, as a semiconductor device incorporated in a minute unit such as a tip portion of an electronic endoscope, for example, Japanese Patent Laid-Open No. 63-308954 discloses a structure shown in FIG. Has been done. That is, in FIG.
Reference numeral 1 denotes a substrate, on which an IC chip 2 is connected by a bonding wire 3 and mounted by being sealed with a sealing resin 4, and a chip component 5 such as a resistor or a capacitor is mounted on the substrate 1. The semiconductor device 6 is configured by being connected and mounted.

【0003】そして、このように構成された半導体装置
6が電子内視鏡の先端部ユニット内に組み込まれるとき
は、該ユニットの鏡枠11内において、固体撮像素子等の
パッケージ12の一方の端子13に、半導体装置6の基板1
の一端が半田付けにより接続されて固着され、外部信号
線15の一方が半導体装置6のチップ部品5に半田付けに
より接続され、他方がパッケージ12の他方の端子14に半
田付けにより接続されるようになっている。
When the semiconductor device 6 having such a structure is incorporated in the distal end unit of the electronic endoscope, one terminal of the package 12 such as a solid-state image pickup device is provided in the lens frame 11 of the unit. 13, the substrate 1 of the semiconductor device 6
So that one end of the external signal line 15 is connected to the chip component 5 of the semiconductor device 6 by soldering and the other is connected to the other terminal 14 of the package 12 by soldering. It has become.

【0004】[0004]

【発明が解決しようとする課題】ところで、このように
電子内視鏡の先端部等のユニット内に半導体装置を組み
込んだ場合、ユニットが大きい場合には問題は生じない
が、ユニットが小さくなり半導体装置の配置スペースが
限られてくると、図7に示すように、半導体装置に接続
する外部信号線と鏡枠とが干渉しあい始めるばかりでな
く、半導体基板の配設・接続作業が極めて困難となり、
ユニットの小型化も困難である。これは、半導体装置を
構成する基板がある一定の厚みをもっていることが一因
となっており、したがって基板自体を薄くすることも考
えられるが、基板自体を薄くすると基板強度が低下し、
基板割れ等が発生する。
By the way, when the semiconductor device is incorporated in the unit such as the distal end portion of the electronic endoscope as described above, the problem does not occur when the unit is large, but the unit becomes smaller and the semiconductor becomes smaller. When the space for arranging the device is limited, not only the external signal line connected to the semiconductor device and the lens frame start to interfere with each other as shown in FIG. 7, but also the work of arranging and connecting the semiconductor substrate becomes extremely difficult. ,
It is also difficult to downsize the unit. This is partly due to the fact that the substrate that constitutes the semiconductor device has a certain thickness. Therefore, it is possible to make the substrate itself thin, but if the substrate itself is made thin, the substrate strength decreases,
Substrate cracks etc. occur.

【0005】本発明は、従来の半導体装置における上記
問題点を解消するためになされたもので、基板強度を損
なうことなく小型化を図り、微小ユニット内への組み込
みも精度よく且つ作業性よく行えるようにした半導体装
置を提供することを目的とする。
The present invention has been made in order to solve the above problems in the conventional semiconductor device. The present invention can be downsized without impairing the strength of the substrate and can be incorporated in a minute unit with high precision and workability. It is an object of the present invention to provide a semiconductor device having such a structure.

【0006】[0006]

【課題を解決するための手段】上記問題点を解決するた
め、請求項1記載の発明は、少なくとも1つ以上の半導
体素子を基板の片面又は両面に搭載してなる半導体装置
において、前記基板の周辺部にその厚みを漸減する傾斜
部を設けるものである。また請求項2記載の発明は、請
求項1記載の半導体装置において、基板の傾斜部を基板
の上面又は下面に形成した面取り部で構成するものであ
り、請求項3記載の発明は、請求項1記載の半導体装置
において、基板の傾斜部を基板の上面及び下面に形成し
た面取り部で構成するものである。また請求項4,5,
6記載の各発明は、請求項2又は3記載の半導体装置に
おいて、面取り部を、その表面がほぼ平面状あるいは凹
面状あるいは凸面状をなすように構成するものである。
In order to solve the above problems, the invention according to claim 1 provides a semiconductor device in which at least one semiconductor element is mounted on one side or both sides of the substrate. An inclined portion is provided in the peripheral portion, the thickness of which gradually decreases. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the inclined portion of the substrate is formed by a chamfered portion formed on the upper surface or the lower surface of the substrate. In the semiconductor device described in 1, the inclined portion of the substrate is formed by chamfered portions formed on the upper surface and the lower surface of the substrate. Moreover, claims 4, 5,
According to the sixth aspect of the present invention, in the semiconductor device according to the second or third aspect, the chamfered portion is configured such that the surface thereof has a substantially flat shape, a concave shape, or a convex shape.

【0007】このように半導体装置を構成することによ
り、基板の強度を保持しながら、外部信号線等の他の部
材との配置関係において実質的に厚さを薄くすることが
でき、小型化を図ることができる。特に面取り部の表面
を凸面状とすることにより、面取り部によるエッジ部を
なくすことができ、外部信号線の接触時の被覆破れや断
線を有効に防止することが可能となる。
By configuring the semiconductor device in this way, the thickness of the substrate can be substantially reduced in the positional relationship with other members such as the external signal line while maintaining the strength of the substrate, and the size can be reduced. Can be planned. In particular, by making the surface of the chamfered portion convex, it is possible to eliminate the edge portion due to the chamfered portion, and it is possible to effectively prevent coating breakage or disconnection at the time of contact with the external signal line.

【0008】[0008]

【発明の実施の形態及び実施例】次に実施例について説
明する。図1は本発明に係る半導体装置の第1実施例を
示す断面図であり、図6に示した従来例と同一又は対応
する部材には同一符号を付して示している。図1におい
て、21は基板でセラミック,ガラス繊維強化エポキシ樹
脂,ガラス,金属等で構成され、一端の下面には面取り
部22が形成されている。面取り部22の形成手段として
は、比較的エッチング処理のしやすいガラス,シリコ
ン,金属を用いている場合は、乾式あるいは湿式のエッ
チング処理により面取り部を形成する。一方エッチング
処理が難しいセラミックやガラス繊維強化エポキシ樹脂
を用いている場合は、例えばグラインダー等の機械的加
工により面取り部を形成する。厚さ0.4 mm,長さ5mm程
度の基板においては、面取り部の面取り深さは0.1 〜0.
3 mm程度、面取り部の長さは端面より0.8 〜1.0 mm程度
が望ましい。
BEST MODE FOR CARRYING OUT THE INVENTION Next, examples will be described. FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention, and the same or corresponding members as those of the conventional example shown in FIG. 6 are designated by the same reference numerals. In FIG. 1, reference numeral 21 designates a substrate made of ceramic, glass fiber reinforced epoxy resin, glass, metal or the like, and a chamfered portion 22 is formed on the lower surface at one end. When glass, silicon, or metal, which is relatively easy to etch, is used as the means for forming the chamfer 22, the chamfer is formed by a dry or wet etching process. On the other hand, when a ceramic or glass fiber reinforced epoxy resin that is difficult to etch is used, the chamfered portion is formed by mechanical processing such as a grinder. In the case of a substrate with a thickness of 0.4 mm and a length of 5 mm, the chamfer depth of the chamfer is 0.1 to 0.
It is desirable that the length of the chamfer is about 3 mm and the length of the chamfer is about 0.8 to 1.0 mm from the end face.

【0009】そして、このように下面に面取り部22を形
成した基板21の表面には、信号処理用IC,演算用I
C,メモリー用IC等のICチップ2をボンディングワ
イヤ3で接続し、エポキシ,フェノール,シリコン等の
封止樹脂4で封止して搭載し、また抵抗やコンデンサ等
のチップ部品5を接続して搭載し、半導体装置6を構成
している。
Then, on the surface of the substrate 21 having the chamfered portion 22 formed on the lower surface in this way, a signal processing IC and an arithmetic I
C, an IC chip 2 such as a memory IC is connected by a bonding wire 3 and mounted by being sealed with a sealing resin 4 such as epoxy, phenol, or silicon, and a chip component 5 such as a resistor or a capacitor is connected. The semiconductor device 6 is mounted and constitutes the semiconductor device 6.

【0010】このように構成された半導体装置を、図2
に示すように、電子内視鏡の先端部ユニット内に組み込
んで用いる場合には、従来例と同様に、該ユニットの鏡
枠11内において、固体撮像素子等のパッケージ12の一方
の端子13に、半導体装置6の基板1の一端が半田付けに
より接続されて固着され、外部信号線15の一方が半導体
装置6のチップ部品5に半田付けにより接続され、他方
がパッケージ12の他方の端子14に半田付けにより接続さ
れるようになっている。その際、半導体装置を構成して
いる基板21には面取り部22が形成されているので、基板
21の強度を損なわずに実質的に薄くでき、外部信号線15
が鏡枠11と干渉する度合いが少なくなり、外部信号線15
の引回し等もスムーズに行え、微小ユニット内への組み
込みを精度よく且つ作業性よく行うことができる。な
お、上記実施例ではICチップ2の基板21への接続をワ
イヤーボンド方式としたものを示したが、フリップチッ
プ方式としてもよいことは勿論である。また、外部信号
線15は通常2〜10本程度で構成されており、パッケージ
12の端子14及び半導体装置6のチップ部品5の他に、半
導体装置6の基板21にも半田付けにより接続されてい
る。
A semiconductor device having such a structure is shown in FIG.
As shown in FIG. 2, when it is used by being incorporated in the distal end unit of the electronic endoscope, as in the conventional example, in the lens frame 11 of the unit, one terminal 13 of the package 12 such as a solid-state imaging device is provided. , One end of the substrate 1 of the semiconductor device 6 is connected and fixed by soldering, one of the external signal lines 15 is connected to the chip component 5 of the semiconductor device 6 by soldering, and the other is connected to the other terminal 14 of the package 12. It is designed to be connected by soldering. At that time, since the chamfered portion 22 is formed on the substrate 21 forming the semiconductor device, the substrate
21 can be made substantially thin without compromising the strength of the external signal line 15
Of the external signal line 15
It can be smoothly routed, etc., and can be incorporated into a minute unit with high precision and workability. In the above embodiment, the wire bonding method is used to connect the IC chip 2 to the substrate 21, but it goes without saying that a flip chip method may be used. The external signal line 15 is usually composed of about 2 to 10
In addition to the 12 terminals 14 and the chip component 5 of the semiconductor device 6, the substrate 21 of the semiconductor device 6 is also connected by soldering.

【0011】図3は、本発明の第2実施例を示す断面図
である。この実施例は、面取り部22を基板21の上面に形
成したもので、第1実施例と同様な効果が得られる。ま
た、面取り部22は第1又は第2実施例に示したように基
板21の下面又は上面にのみ設ける代わりに、基板の両面
に設けることができ、この場合は基板の更に薄型化を図
ることができる。
FIG. 3 is a sectional view showing a second embodiment of the present invention. In this embodiment, the chamfered portion 22 is formed on the upper surface of the substrate 21, and the same effect as that of the first embodiment can be obtained. Further, the chamfered portion 22 can be provided on both surfaces of the substrate 21 instead of being provided only on the lower surface or the upper surface of the substrate 21 as in the first or second embodiment. In this case, the thickness of the substrate can be further reduced. You can

【0012】図4は、第3実施例を示す断面図であり、
この実施例は、基板21の下面に設けた面取り部22aの表
面を凹面状としたものである。このように構成すること
により第1実施例と同様の効果が得られると共に、ユニ
ット内に配置する場合に、更に配置の自由度の向上を図
ることができる。
FIG. 4 is a sectional view showing a third embodiment,
In this embodiment, the chamfered portion 22a provided on the lower surface of the substrate 21 has a concave surface. With this configuration, the same effect as that of the first embodiment can be obtained, and when the unit is arranged in the unit, the degree of freedom in the arrangement can be further improved.

【0013】図5は、第4実施例を示す断面であり、こ
の実施例は、基板21の下面に設けた面取り部22bの表面
を凸面状としたものである。このように構成することに
より面取り部22bの境界にはエッジ部が形成されないた
め、ユニット内に組み込んだ場合、基板21の面取り部22
bに外部信号線15が接触しても、被覆が破れたり、断線
が生じたりするのを有効に防止することができる。
FIG. 5 is a cross section showing a fourth embodiment. In this embodiment, the surface of the chamfered portion 22b provided on the lower surface of the substrate 21 is convex. With such a configuration, no edge portion is formed at the boundary of the chamfered portion 22b. Therefore, when incorporated in the unit, the chamfered portion 22 of the substrate 21 is not formed.
Even if the external signal line 15 comes into contact with b, it is possible to effectively prevent the coating from breaking or the wire breaking.

【0014】[0014]

【発明の効果】以上実施例に基づいて説明したように,
本発明によれば、基板の強度を損なわずに実質的に基板
を薄型化することができ、半導体装置の小型化を図るこ
とができ、微小ユニット内への組み込みも精度よく且つ
作業性よく行うことが可能となる。また特に基板に設け
る面取り部の表面を凸面状とすることにより、エッジ部
をなくし外部信号線の接触時の被覆破れや断線を防止す
ることができる。
As described above on the basis of the embodiments,
According to the present invention, the substrate can be substantially thinned without impairing the strength of the substrate, the semiconductor device can be downsized, and the assembly into the minute unit can be performed accurately and with good workability. It becomes possible. In particular, by making the surface of the chamfered portion provided on the substrate convex, it is possible to eliminate the edge portion and prevent the coating from breaking or breaking when the external signal line comes into contact.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の第1実施例を示す断
面図である。
FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention.

【図2】図1に示した第1実施例の半導体装置を電子内
視鏡の先端部ユニット内に組み込んだ態様を示す図であ
る。
FIG. 2 is a diagram showing a mode in which the semiconductor device of the first embodiment shown in FIG. 1 is incorporated in a tip unit of an electronic endoscope.

【図3】本発明の第2実施例を示す断面図である。FIG. 3 is a sectional view showing a second embodiment of the present invention.

【図4】本発明の第3実施例を示す断面図である。FIG. 4 is a sectional view showing a third embodiment of the present invention.

【図5】本発明の第4実施例を示す断面図である。FIG. 5 is a sectional view showing a fourth embodiment of the present invention.

【図6】従来の半導体装置の構成例を示す断面図であ
る。
FIG. 6 is a cross-sectional view showing a configuration example of a conventional semiconductor device.

【図7】図6に示した半導体装置を電子内視鏡の先端部
ユニット内に組み込んだ態様を示す図である。
FIG. 7 is a diagram showing an aspect in which the semiconductor device shown in FIG. 6 is incorporated in a tip unit of an electronic endoscope.

【符号の説明】[Explanation of symbols]

1 基板 2 ICチップ 3 ボンディングワイヤ 4 封止樹脂 5 チップ部品 6 半導体装置 11 鏡枠 12 バッケージ 13,14 端子 15 外部信号線 21 基板 22 面取り部 22a 凹面状面取り部 22b 凸面状面取り部 1 substrate 2 IC chip 3 bonding wire 4 sealing resin 5 chip component 6 semiconductor device 11 mirror frame 12 package 13, 14 terminal 15 external signal line 21 substrate 22 chamfered portion 22a concave chamfered portion 22b convex chamfered portion

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも1つ以上の半導体素子を基板
の片面又は両面に搭載してなる半導体装置において、前
記基板の周辺部にその厚みを漸減する傾斜部を備えてい
ることを特徴とする半導体装置。
1. A semiconductor device in which at least one or more semiconductor elements are mounted on one side or both sides of a substrate, wherein a peripheral portion of the substrate is provided with an inclined portion whose thickness is gradually reduced. apparatus.
【請求項2】 前記基板の傾斜部は、基板の上面又は下
面に形成した面取り部で構成されていることを特徴とす
る請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the inclined portion of the substrate is a chamfered portion formed on the upper surface or the lower surface of the substrate.
【請求項3】 前記基板の傾斜部は、基板の上面及び下
面に形成した面取り部で構成されていることを特徴とす
る請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the inclined portion of the substrate is composed of chamfered portions formed on an upper surface and a lower surface of the substrate.
【請求項4】 前記面取り部は、その表面がほぼ平面状
をなしていることを特徴とする請求項2又は3記載の半
導体装置。
4. The semiconductor device according to claim 2, wherein the chamfered portion has a substantially flat surface.
【請求項5】 前記面取り部は、その表面が凹面状をな
していることを特徴とする請求項2又は3記載の半導体
装置。
5. The semiconductor device according to claim 2, wherein the chamfered portion has a concave surface.
【請求項6】 前記面取り部は、その表面が凸面状をな
していることを特徴とする請求項2又は3記載の半導体
装置。
6. The semiconductor device according to claim 2, wherein the chamfered portion has a convex surface.
JP24232495A 1995-08-29 1995-08-29 Semiconductor device Expired - Lifetime JP3947239B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24232495A JP3947239B2 (en) 1995-08-29 1995-08-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24232495A JP3947239B2 (en) 1995-08-29 1995-08-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0964273A true JPH0964273A (en) 1997-03-07
JP3947239B2 JP3947239B2 (en) 2007-07-18

Family

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Family Applications (1)

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