JPH0955883A - Drive method for solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve smears without changing the process condition by changing the peak of the potential in the substrate depth direction to the vertical transfer register side in the frame period when signal electric charge is transferred from an image part to a storage part. SOLUTION: In the frame shift period when signal electric charge is transferred from the image part to the storage part at a high speed, the voltage applied to a substrate 11 is made higher than a normal set value. When the voltage applied to the substrate 11 is made higher, the peak of the potential between a sensor part 2 and a vertical transfer register 4 is practically shifted toward the vertical transfer register 4. Thus, the quantity of reflected light, which is caused by multiple reflection repeated between the substrate surface and a lower end face 19a of a light shielding film 19 or a transfer electrode 18 at the time of oblique incidence of light on the sensor part 2, jumping into a signal electric charge transfer area 16 of the vertical transfer register is reduced. As the result, the substrate voltage is only changed to improve smears.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state image pickup device, and more particularly to a method for driving a solid-state image pickup device such as a frame interline transfer (FIT) system which has a storage unit separately from an image unit.

[0002]

In the solid-state image pickup device, the surface of the sensor portion is formed as a flat surface. Therefore, as is apparent from FIG. 9, when light is obliquely incident on the sensor portion 91. Of the light reflected on the surface of the sensor unit 91, there is a component that is incident on the lower end surface 92a of the light shielding film 92, and the reflected light component is the substrate surface and the lower end surface 9 of the light shielding film 92.
There is a problem in that multiple reflections are repeated between the 2a and the transfer electrode 93, and finally, the photoelectrons are generated by jumping into the signal charge transfer region 95 of the vertical transfer register 94 to increase the smear component.

Regarding the smear component, the sensor unit 91
If the effective signal charge storage area near the surface of the is expanded in the direction of the vertical transfer register 94 (horizontal direction), the reflected light that jumps into the signal charge transfer area 95 will be reduced by that amount, thus improving smear. It turns out to be effective.
As a measure to realize this, changing the profile of impurities can be considered. However, in order to change the profile of impurities, it is necessary to change the process conditions, and the number of steps also increases.

Therefore, an object of the present invention is to provide a method for driving a solid-state image pickup device which can improve smear without changing the process conditions.

[0005]

A method of driving a solid-state image pickup device according to the present invention comprises a plurality of two-dimensionally arrayed sensor units and a plurality of vertical transfer registers arranged in each vertical column of these sensor units. In a solid-state imaging device including an image section and a storage section that stores signal charges transferred at high speed from the image section, a potential peak in the substrate depth direction between the sensor section and the vertical transfer register is stored from the image section. The signal charges are transferred to the vertical transfer register side during the frame shift period in which the signal charges are transferred at high speed.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows, for example, a frame interline transfer (FI) to which the present invention is applied.
It is a schematic block diagram of a T) system CCD solid-state image sensor. FIG.
In FIG. 1, the image unit 1 includes a plurality of sensor units (pixels) 2 which are two-dimensionally arranged in a matrix form and convert incident light into signal charges (for example, electrons) having a charge amount corresponding to the light amount and accumulate the signal charges. A vertical transfer register 4 is provided for each vertical column of the sensor units 2 and vertically transfers the signal charges read from each sensor unit 2 through the read gate unit 3.

On the other hand, the storage section 5 provided independently of the image section 1 is constituted by a plurality of vertical transfer registers 6 continuously provided for each column with respect to the vertical transfer register 4 of the image section 1. It is composed and image part 1
The signal charges for one field, which are photoelectrically converted in pixel units, are accumulated at the high speed transfer from the image unit 1. The entire surface of the storage unit 5 is covered with a light shielding layer (not shown) made of aluminum, for example.

In the image section 1, the signal charges obtained by photoelectric conversion in each sensor section 2 are read out by the read gate section 3.
The data is read out to the vertical transfer register 4 via and is transferred at high speed to the storage unit 5 by the register 4 and accumulated. This high-speed transfer is frame shift. The signal charges accumulated in the storage unit 5 are transferred to the horizontal transfer register 7 by the vertical transfer register 6 in units corresponding to one line.
Is forwarded to This transfer is a line shift. This one
The signal charges for the lines are sequentially horizontally transferred by the horizontal transfer register 7.

In this example, the horizontal transfer register 7 is set to 1
Although the configuration in the case of the book is shown, it is also possible to adopt a configuration in which, for example, two horizontal transfer registers are juxtaposed and the signal charges for one line are distributed and transferred to the two horizontal transfer registers. This has the advantage that the horizontal transfer frequency can be halved. At the end of the transfer destination of the horizontal transfer register 7, a charge detection unit 8 including a floating diffusion amplifier or the like is provided. The charge detection unit 8 converts the signal charge transferred by the horizontal transfer register 7 into an electric signal and outputs it as an image signal.

Here, the vertical transfer register 4 of the image section 1 is driven by four phases by the vertical transfer clocks φIM1 to φIM4, and the vertical transfer register 6 of the storage section 6 is also driven by four phases by the vertical transfer clocks φST1 to φST4. . The horizontal transfer register 7 is driven in two phases by the horizontal transfer clocks φH1 and φH2.

FIG. 2 is a sectional structure of the peripheral portion of the sensor unit 2.
FIG. In FIG. 2, the sensor unit 2 is an N-type semiconductor substrate.
It is formed on the surface side of the P well 12 laminated on the plate 11.
P ⁺Hole accumulation layer 13 made of a type impurity and N underneath
HAD composed of a signal charge storage layer 14 composed of a type impurity
(Hole Accumulated Diode) structure, this HA
By adopting the D structure, the sensitivity is improved and the dark current is reduced.
I have. In the hole storage layer 13 and the signal charge storage layer 14,
The channel stop part (CS) 15 is formed adjacent to
I have.

The vertical transfer register 4 includes a signal charge transfer region 16 formed on the surface side of the P well 12 and a polysilicon formed on the surface of the substrate via an insulating layer 17 made of a silicon oxide film (SiO ₂ ). And a transfer electrode 18 composed of. Further, between the sensor unit 2 and the vertical transfer register 4, the sensor unit 2 and the vertical transfer register 4 are connected.
A read gate portion 3 for reading out signal charges is provided, and the transfer electrode 18 is also used as the gate electrode of the read gate portion 3 in this example. And
Above the read gate portion 3, the vertical transfer register 4, and the channel stop portion 15 except for the sensor portion 2, a light shielding film 19 made of, for example, aluminum is provided with an insulating layer 17 interposed therebetween.
Are provided so as to cover the outside of the transfer electrode 1.

In the FIT CCD solid-state image pickup device having the above structure, the semiconductor substrate 11 has a predetermined substrate voltage Vsub.
Is applied via the adder 20. A shutter pulse ΔVsub having a predetermined peak value (level) generated from a shutter pulse generation circuit 21 is selectively applied to the adder 20 via a switch 22. Switch 22
The timing control circuit 23 controls opening and closing. The timing control circuit 23 closes the switch 22 during the horizontal blanking period to realize an electronic shutter operation of sweeping the signal charges accumulated in the sensor unit 2 to the substrate 11.

That is, during normal operation, the switch 2
2 is opened so that the substrate voltage Vsu is applied to the substrate 11.
b is applied, and as a result, signal charges are accumulated in the sensor unit 2 by photoelectric conversion. On the other hand, during the electronic shutter operation, the switch 22 is closed, and the shutter pulse ΔVsub is superimposed on the substrate voltage Vsub and applied to the substrate 11, whereby the barrier on the substrate side is broken and the signal charge accumulated in the sensor unit 2 is reduced. It is swept onto the substrate 11. FIG. 3 shows a potential distribution of the sensor unit 2 in the vertical direction (substrate depth direction). In the figure, the solid line indicates the normal operation and the alternate long and short dash line indicates the electronic shutter operation.

FIG. 4 is a lateral (horizontal) potential distribution diagram of the peripheral portion of the sensor unit 2. As is apparent from the figure, during the normal operation in which the substrate voltage Vsub is applied to the substrate 11, the potentials of the sensor unit 2 and the vertical transfer register 4 become deep, and as shown by the solid line in FIG. A potential peak (mountain) is formed between the vertical transfer registers 4. Then, in the timing chart of FIG. 5, the vertical transfer clock φIM1 applied to the transfer electrode 18 after the end of the smear sweeping period (FIG. 5 shows only φIM1).
By setting the read pulse φROG at
The peak of the potential between the vertical transfer register 4 and the vertical transfer register 4 collapses, and the signal charges accumulated in the sensor unit 2 are read out to the vertical transfer register 4.

Next, an embodiment of the present invention will be described. In the present embodiment, in the timing chart of FIG. 5, the voltage applied to the substrate 11 is higher than the normal set value (substrate voltage Vsub) during the frame shift period in which the signal charges are transferred from the image unit 1 to the storage unit 5 at high speed. I am trying to do it. By increasing the voltage applied to the substrate 11, the potential of the sensor unit 2 becomes deeper as shown by the dotted line in FIG.
The peak of the potential during the period substantially shifts toward the vertical transfer register 4.

By the way, the frame shift period during which the signal charge is transferred from the image section 1 to the storage section 5 at a high speed is also a period in which the smear component is easily mixed in the signal charge in the vertical transfer register 4 read from the sensor section 2. . Therefore, as described above, by setting the substrate voltage higher than the normal set value during this frame shift period and shifting the peak of the potential between the sensor unit 2 and the vertical transfer register 4 to the vertical transfer register 4 side, The effective signal charge storage region near the surface of the sensor unit 2 expands in the lateral direction (horizontal direction).

As a result, when light is obliquely incident on the sensor unit 2, the vertical transfer register 4 of the reflected light due to the multiple reflections repeated between the substrate surface and the lower end surface 19a of the light-shielding film 19 and the transfer electrode 18. The amount of jumping into the signal charge transfer region 16 is reduced. As a result, smear can be improved only by changing the substrate voltage without changing the process conditions as in the conventional case. Further, since the frame shift period is very short in time with respect to one field period, there is little influence on characteristics.

In the present embodiment, the shutter pulse ΔVsub is used to set the substrate voltage higher than the normal set value during the frame shift period. Specifically, in FIG. 2, the timing control circuit 23 is configured to close the switch 22 during the frame shift period in addition to the electronic shutter operation. As a result, during the frame shift period, (Vs
The voltage of (ub + ΔVsub) is applied to the substrate 11.

As described above, the substrate voltage Vsub
The method of superimposing the shutter pulse ΔVsub on the substrate 11 and applying it to the substrate 11 is only an example.
In addition to a power supply that superimposes a voltage lower than sub on the substrate voltage Vsub, or that generates a Vsub voltage, another power supply that generates a higher voltage is prepared, and the voltage generated from this different power supply is used during the frame shift period. Select board 11
It is also possible to use other methods, such as applying to.
However, by using the shutter pulse ΔVsub,
There is an advantage that it is not necessary to newly prepare a separate power supply, and it can be dealt with only by changing the timing of the timing control circuit 23.

If the shutter pulse ΔVsub is superimposed on the substrate voltage Vsub, the sensitivity of the CCD solid-state image pickup device may be lowered. In such a case, the shutter pulse ΔVsub may be selectively superimposed on the substrate voltage Vsub according to the illuminance of the subject, or the superimposed shutter pulse ΔVsub may be gradually decreased as indicated by the dotted line in FIG. It is possible to deal with the decrease in sensitivity.

As an example of a method of selectively superimposing the shutter pulse ΔVsub according to the illuminance of the subject, when the illuminance of the subject is generally bright, a slight decrease in sensitivity can be ignored, so that the switch 22 during the frame shift period.
Is closed and the shutter pulse ΔV is applied to the substrate voltage Vsub.
When smear improvement is prioritized by superimposing the sub, and when the illuminance of the subject is entirely dark, the switch 22 is kept open during the frame shift period as in the normal driving, and the shutter pulse ΔVsub is set to the substrate voltage Vsub. It is sufficient to prevent the sensitivity from decreasing by not overlapping. This is a timing control circuit 23 for illuminance information.
Can be achieved by giving

Next, another embodiment of the present invention will be described. In the present embodiment, as shown in FIG. 6, a level shift circuit 25 is built in a timing generation circuit 24 for generating timing signals such as vertical transfer clocks φIM1 to φIM4, φST1 to φST4 and horizontal transfer clocks φH1 and φH2. The vertical transfer clocks φIM1 to φIM4 and φST1 to φST4 are shifted to the negative side during the frame shift period in which the signal charges are transferred at high speed from the unit 1 to the storage unit 5. Figure 7
As an example, a timing chart of only the vertical transfer clock φIM1 is shown.

As described above, when the vertical transfer clocks φIM1 to φIM4 and φST1 to φST4 are shifted to the negative side during the frame shift period, the potential of the vertical transfer register 4 becomes shallow as shown by the dotted line in FIG. The potential peak between the section 2 and the vertical transfer register 4 is substantially shifted in the direction of the vertical transfer register 4. As a result, the effective signal charge storage region near the surface of the sensor unit 2 expands in the lateral direction (horizontal direction).

As a result, when light is obliquely incident on the sensor portion 2, the reflected light due to the multiple reflections repeated between the substrate surface and the lower end surface 19a of the light shielding film 19 and the transfer electrode 18,
Since the amount of jumping into the signal charge transfer region 16 of the vertical transfer register 4 is reduced, smear can be improved only by adding the level shift circuit 25 without changing the process conditions as in the conventional case. The frame shift period is 1
Since it is very short in time with respect to the field period, there is little influence on the characteristics.

In each of the above embodiments, the substrate voltage is set higher than the normal set value during the frame shift period, and the vertical transfer clocks φIM1 to φIM4 and φST1 are set.
Although it has been stated that the shift of .about..phi.ST4 to the negative side is carried out independently of the normal transfer, it is also possible to carry out a combination thereof.

Further, in each of the above-described embodiments, the case where the present invention is applied to the CCD solid-state image pickup device in which electrons are used as signal charges has been described. Yes, in this case, the positive and negative polarities may be reversed.

[0028]

As described above, according to the present invention,
In a solid-state imaging device that has a storage unit independently of the image unit, a frame shift period in which the potential peak in the substrate depth direction between the sensor unit and the vertical transfer register is transferred at high speed from the image unit to the storage unit. By shifting to the vertical transfer register side, the effective signal charge storage area near the surface of the sensor part expands horizontally, and when the light obliquely enters the sensor part, the vertical transfer register Since it is possible to prevent the mixing of light, without changing the process conditions as in the past,
Smear can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a FIT type CCD solid-state imaging device to which the present invention is applied.

FIG. 2 is a cross-sectional structure diagram around a sensor unit.

FIG. 3 is a potential distribution diagram for explaining an electronic shutter operation.

FIG. 4 is a potential distribution diagram according to an embodiment of the present invention.

FIG. 5 is a timing chart according to an embodiment of the present invention.

FIG. 6 is a schematic configuration diagram according to another embodiment of the present invention.

FIG. 7 is a timing chart according to another embodiment of the present invention.

FIG. 8 is a potential distribution diagram according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view of the periphery of a sensor unit for explaining the problem.

[Explanation of symbols]

 1 storage unit 2 sensor unit 4,6 vertical transfer register 5 storage unit 7 horizontal transfer register

Claims (4)

[Claims] 1. An image part having a plurality of two-dimensionally arranged sensor parts and a plurality of vertical transfer registers arranged in each vertical column of these sensor parts, and a signal charge transferred at high speed from the image part. A method of driving a solid-state imaging device, comprising: a storage unit for accumulating, wherein a potential peak in a substrate depth direction between the sensor unit and the vertical transfer register is applied to a signal charge from the image unit to the storage unit. A method of driving a solid-state imaging device, characterized in that a shift is made to the vertical transfer register side during a frame shift period of high-speed transfer. 2. The method for driving a solid-state image pickup device according to claim 1, wherein the substrate voltage is set higher than a normal set value during the frame shift period. 3. The method of driving a solid-state image pickup device according to claim 1, wherein the vertical transfer clocks of the image section and the storage section are level-shifted during the frame shift period. 4. The solid-state image pickup according to claim 1, wherein the substrate voltage is set higher than a normal set value during the frame shift period, and the vertical transfer clocks of the image section and the storage section are level-shifted. Device driving method.