JPH0951290A - Spread spectrum communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost by preparing plural clocks with different phases in the spread spectrum communication equipment, selecting one clock among them and providing the output of the selected clock or of an inverted selected clock so as to reduce the number of clocks. SOLUTION: A correlation detection circuit 10 detects the correlation between an intermediate frequency reception signal and a reference spread code used for inverse spread. The correlation signal is digitized by a peak detection circuit 11 and outputted to a clock generating circuit 14 and a code phase reset circuit 15. The clock generating circuit 14 selects one of N/2 signals obtained by delaying the reference clock by a delay circuit 13, a phase of a peak signal is detected, a new clock phase is calculated to generate an output clock. When the phase is a phase slower than the reference clock by a discrimination period, a phase inverting signal is outputted. A code phase reset circuit 15 provides the output of a code reset signal to take synchronization between a reference spread code and a demodulation inverse spread code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication device.

[0002]

2. Description of the Related Art A transmission signal in a spread spectrum communication device system is a base band information signal spread over a wide frequency band by a spreading code such as a pseudo random code. At the time of demodulation, this spread spectrum communication is despread with the same code as the above spread code to obtain a base band information signal. At this time, if the code synchronization is not established, the information is not demodulated correctly.

The receiving section in the spread spectrum communication device is basically composed of a high frequency section 60, a code synchronizing section 61, and an information demodulating section 62, as shown in FIG.
The code synchronization unit 61 receives the reception IF (intermediate frequency) signal processed by the high frequency unit 60, and outputs a code generation clock S61 and a despreading code reset signal S62 (hereinafter, code reset signal) synchronized with the reception IF signal. To do. The information demodulation unit 62 despreads the spread spectrum received signal with the despread code generated at the timing of the code generation clock S61 and the code reset signal S62, and obtains a baseband information signal.

Conventionally, the code synchronization section 61 uses a sliding correlation synchronization method in which the same spread signal as the received spread signal is slid to acquire synchronization, or a correlation circuit (for example, SAW (surface acoustic wave) convolver) is used. A general method is to configure a phase-locked loop (PLL) using them to perform code and clock synchronization. However, with these synchronization methods, there is a limit to the drastic reduction of the synchronization pull-in time. Therefore, when performing bucket communication in which information is transmitted as a bucket, the brimble period for synchronization becomes longer, which lowers the slewing. There's a problem. In order to avoid this problem, we have proposed a synchronization method using a reset type code synchronization circuit as shown in FIG. The operation of the reset type code synchronization circuit will be described below with reference to FIG.

In FIG. 2, a correlation detection circuit 20 (for example, a SAW (surface acoustic wave) convolver) correlates the received IF (intermediate frequency) signal processed by the high frequency unit 60 with a reference spread code used for despreading. To detect. The correlation signal is digitized by the peak detection circuit 21 and output to the phase shift unit 23 and the code phase reset circuit 26.

The phase shifter 23 delays the reference clock signal by a delay circuit 24 for a delay amount T over one clock cycle.
One of N clocks delayed by c / N (Tc is one clock cycle) is selected. S in the correlation detection circuit 20
When performing convolutional correlation using an AW convolver, etc.,
Clock synchronization is achieved by selecting, as the code clock, a clock having a phase obtained by doubling the phase delay of the peak signal with respect to the clock selected up to that point (hereinafter referred to as the code clock). In addition, the phase shifter 23
Alternatively, a reference clock having a frequency of N times may be used to start dividing the reference clock by N at a desired timing and output the code clock.

Further, the code phase reset circuit 26 obtains by doubling the phase delay of the peak signal with respect to the code generation timing of the reference spread code, when the correlation detection circuit 20 uses a SAW convolver or the like to perform convolutional correlation. The code reset signal is output at the code phase thus obtained, and the reference spread code and the despread code are code-synchronized.

[0008]

However, in order to improve the accuracy of clock synchronization in the reset type code synchronization circuit of FIG. 2, a delay circuit that maintains at least the delay amount of the code clock period with high accuracy, or a high speed However, there was a drawback that a highly accurate clock was required.

Further, in such a code synchronization method of digital processing, since the resolution of peak detection is one chip, an error of ± 1 chip occurs in the code synchronization by the code phase reset circuit 26, and accurate information demodulation cannot be performed. There was a possibility.

An object of the present invention is to provide a spread spectrum communication device that solves such a problem.

[0011]

Therefore, in the present invention, the code synchronizing circuit has the following configuration.

That is, a plurality of clocks having different phases are prepared, one of the clocks is selected, and as it is,
Alternatively, by adopting a configuration in which the phase is inverted and output, the number of required clocks can be reduced, and the system price can be reduced.

In addition, since the digital processing part for determining the phase inversion can be integrated into a gate array or the like on one chip, there is an effect that the circuit around the delay means can be simplified.

Further, the correlation means is SAW (surface acoustic wave).
When performing convolutional correlation using a convolver or the like, by detecting the loss of code synchronization from the clock phase inversion signal after the clock synchronization is established, the output timing of the code phase reset signal is advanced or delayed by one clock. Out of synchronization of ± 1 chip of code synchronization can be prevented, and the reliability of information demodulation can be improved.

[0015]

1 is a block diagram of a code synchronization circuit of a spread spectrum communication apparatus embodying the present invention, and FIG. 3 is a diagram showing a structure of a clock generation circuit 14 in FIG.

In FIG. 1, a correlation detection circuit 10 (for example, a SAW (surface acoustic wave) convolver) correlates the received IF (intermediate frequency) signal processed by the high frequency unit 60 with a reference spread code used for despreading. To detect. The correlation signal is digitized by the peak detection circuit 11 and output to the clock generation circuit 14 and the code phase reset circuit 15.

First, the clock generation circuit 14 will be described. The clock generation circuit 14 delays the reference clock signal by a delay amount Tc /
The phase of the peak signal is detected by using N / 2 clocks delayed by N (Tc is one clock cycle), the phase of the clock to be newly output is calculated, and the output clock is generated.

FIG. 3 shows a concrete configuration of the clock generation circuit 14. The clock generation circuit 14 includes a clock phase determination circuit 30, a selector 31, and a clock phase inversion circuit 32. The clock phase determination circuit 30 detects the phase of the correlation peak signal using the plurality of clock signals generated by the clock delay circuit 13 and calculates the phase of the clock to be newly output, and further, the calculated phase is the reference. If the phase is half cycle or more later than the clock, the clock phase inversion signal is output, and the selector 31 is requested to select the clock whose half cycle phase is earlier than the calculated phase. If the output clock can be generated with the resolution of Tc / N even when the clock phase is delayed by a half cycle or more by inverting the clock phase, the duty ratio of each clock is set to about 50%. Good. The selector 31 receives the output of the clock phase determination circuit 30 and generates an output clock from the plurality of clock signals,
When the clock phase inversion circuit 32 receives the clock phase inversion signal from the clock phase determination circuit 30, it also inverts the phase of the generated output clock.

Specifically, as shown in FIG. 7, for example, the clock phase determination circuit 30 detects the phase of the correlation peak signal by a plurality of flip-flops in which each delayed clock is used as data and the peak signal is input to CLK, and the phase is detected. The phase of the clock to be newly output is calculated using the result.

When performing convolutional correlation using a SAW convolver or the like in the correlation detection circuit 10, the phase of the clock to be newly output is calculated by doubling the phase delay of the peak signal with respect to the clock that has been selected up to that point. it can.

An example of the phase detection method of the correlation peak signal is as follows:
A timing chart will be described with reference to FIG. In FIG.
The case where the delay circuit 13 detects the phase using the five clocks CLK # 0 to CLK # 4 delayed by the delay amount Tc / 10 (Tc is one clock cycle) is shown. When the peak signal is in the position shown in the figure, the output of each flip-flop is like CS0 to CS4, the outputs of CS2 and CS3 are different, and the previous flip-flop (CS2 in this case)
Since the output level of is high level, the peak signal is CLK
It can be seen that it is near the rising edge of # 3. Therefore, the phase of the peak signal is the reference clock (CL in this case).
It is detected that the position is 3Tc / 10 behind K # 0).

This peak signal is sent to the correlation detection circuit 10 as SA.
If it is obtained by convolutional correlation using a W convolver or the like, the phase of the clock to be newly generated is twice the phase of the peak signal, that is, 6Tc / 10.
It is a delayed phase. Since 6 Tc / 10 is a phase that is a half cycle or more later than the reference clock, the clock phase determination circuit 30 outputs a clock phase inversion signal, and the clock is delayed by Tc / 10, which is a half cycle phase earlier than the calculated phase, that is, CLK # 1. Request the selector 31 to select.
Therefore, the clock generation circuit 14 outputs the clock obtained by inverting the sign of CLK # 1 as the code clock, and the code synchronization can be established.

Next, the code phase reset circuit 15 will be described. When the SAW convolver or the like is used for the correlation detection circuit 10 to perform convolutional correlation, the code phase reset circuit 15 codes a code phase obtained by doubling the phase delay of the peak signal with respect to the code generation timing of the reference spreading code. A reset signal is output to synchronize the reference spreading code and the despreading code.

Since the resolution of the correlation peak detection is 1 chip, there is a possibility that an error of ± 1 chip may occur in code synchronization only by this operation. Therefore, after clock synchronization is established by the clock generation circuit 14 and reset by the code reset circuit 15 even once, as shown in FIG. 5, if (a) code synchronization is achieved, (b) code synchronization is performed. There are two possible cases in which 1 is shifted by 1 chip.

(A) The correlation peak when code synchronization is established appears near the rising edge of the code clock,
(B) The correlation peak when the code synchronization is shifted by one chip appears near the falling edge of the code clock. Therefore, in the clock phase calculation circuit shown in FIG. 7, after the code is reset even once by the code phase reset circuit 15, the correlation peak is near the edge of any of the delayed N / 2 clocks. Detect if it appears. Also, the doubling of the phase delay of the peak signal with respect to the selected clock is stopped, and the clock indicating the phase of the correlation peak signal and the phase inversion signal are output as they are. The code phase reset circuit 15 considers that the code synchronization is shifted by one chip when the phase inversion signal at the time of generating the code clock and the subsequent phase inversion signal are different from each other, and considers the relationship between the peak signal and the code generation timing signal. The output timing of the code phase reset signal is advanced or delayed by one clock. However, even if the phase inversion signals are different, the phase inversion circuit 32 does not invert the phase of the output clock. For example, when the inversion of CLK # 1 is selected, if the code synchronization is shifted by one chip, the correlation peak appears near the rising edge of CLK # 1, so that the phase inversion signal changes from on to off. When the code synchronization is established, the correlation peak appears near the falling edge of CLK # 1, so the phase inversion signal remains ON. Therefore, it is possible to accurately detect and correct the deviation of the code synchronization of ± 1 chip.

[0026]

As described above, a plurality of clocks having different phases are prepared, and one of the clocks is selected and directly output, or the phase is inverted and output. Since it is not necessary to prepare the number of clocks, the number of expensive circuits can be reduced and the system price can be reduced.

In addition, since the analog processing section is reduced and the phase inversion determination and the like are digitally processed, the digital processing can be made into a single chip such as a gate array, which means that the circuit around the delay means is simple and downsized. There is also an effect.

In the present invention, at least a half cycle of the reference clock may be prepared. Also, the number of delay means is half.

Further, by detecting the deviation of the code synchronization from the correlation peak after the clock synchronization is established and the deviation of the code clock and advancing or delaying the output timing of the code phase reset signal by one clock, the code synchronization can be achieved. Since the synchronization loss of ± 1 chip is prevented, the reliability of information demodulation is improved and the error rate is reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a code synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a code synchronization circuit of a comparative example.

FIG. 3 is a diagram showing a configuration of a clock generation circuit in the code synchronization circuit according to the exemplary embodiment of the present invention.

FIG. 4 is an explanatory diagram of a clock selection method according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of code synchronization deviation detection according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a receiving device in a spread spectrum communication system.

FIG. 7 is a diagram showing an example of a clock phase determination circuit according to the embodiment of the present invention.

[Explanation of symbols]

 10 Correlation Detection Circuit 11 Peak Detection Circuit 12 Oscillator 13 Delay Circuit 14 Clock Generation Circuit 15 Code Phase Reset Circuit 16 Reference Code Generation Circuit

Claims (11)

[Claims] 1. A correlation detecting means for detecting a correlation between a received signal and a reference spread code to generate a correlation output signal, and a clock for generating a clock corresponding to a peak of the correlation output signal from a plurality of clocks having different phases. The clock generation means has a generation means and a code generation means for generating a despreading code for demodulation in response to the peak of the correlation output signal, and the clock generation means includes one of the plurality of clocks in accordance with the peak of the correlation output signal. A spread spectrum communication device, which selects two clocks and outputs them as they are or after inverting the phase. 2. The clock generation means according to claim 1, wherein the clock generation means detects a peak of a correlation output signal using a plurality of clock signals and calculates a phase of a clock to be newly output, The clock phase deciding means is composed of selector means for selecting an output clock from a plurality of clock signals and clock phase inverting means. A spread spectrum communication device, wherein a clock phase inversion signal is output to the inverting means, and the selector means is requested to select a clock having a half cycle earlier than the calculated phase. 3. The clock signal output from the clock generating means according to claim 1, wherein the clock signal has a duty ratio such that a clock phase can be generated even by a phase delayed by a half cycle or more of the clock by inverting the clock phase. Spread spectrum communication device. 4. The spread spectrum communication device according to claim 1, wherein a SAW (surface acoustic wave) convolver is used as the correlation detecting means. 5. The code generation means according to claim 2, wherein the code generation means receives the clock phase inversion signal after the clock synchronization is established, detects the code synchronization loss, and advances or delays the code phase reset timing by one clock. Characteristic spread spectrum communication device. 6. The spread spectrum communication device according to claim 1, wherein the clock generation means delays a reference clock signal generated from a frequency oscillator to generate a plurality of clocks having different phases. 7. The spread spectrum communication device according to claim 6, wherein the maximum clock delay amount of the clock generation means is 1/2 of clock synchronization. 8. The spread spectrum communication device according to claim 1, wherein the code generating means generates a reference spreading code and a demodulation despreading code according to a peak of the correlation output signal. 9. The spread spectrum communication device according to claim 1, wherein the code generation means includes a reset means for resetting the despreading code for demodulation. 10. Correlation means for outputting a correlation signal between a received signal and a reference spread signal, a clock generation means for generating a plurality of clocks having different phases, and a plurality of clocks generated by the clock generation means. From the correlation signal and the clock generation means, a clock generation means for generating a clock according to the correlation signal, a reset means for resetting the reference spreading code and the demodulation despread code according to the correlation output signal, Based on a plurality of generated clocks, the resetting means resets the reference spreading code to determine whether the code synchronization is achieved or the code synchronization is shifted by one chip, and the determining means determines the code synchronization. Is determined to be one chip off, the generation timing of the despreading code for demodulation of the code generating means is set to 1 Tsu spread spectrum communication device having a click shifting control means. 11. The determination means according to claim 10, wherein the code synchronization is established or the chip is shifted by one chip depending on whether the clock generated by the clock generation means matches the correlation signal or is shifted by a half cycle. A spread spectrum communication device characterized by determining whether or not there is.