JPH0951044A - Involatile semiconductor storage device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the drop of breakdown strength in a contact area without a recessed part on a substrate generating during etching of laminated film for realizing a gate structure by providing a polycrystal silicon film made of floating gate material to a contact forming area. SOLUTION: A space between first field oxide films 2A in a Y direction is a cell formation area 60 for forming an EEPROM memory cell. In addition, a space between first field oxide films 2A and second field oxide films 2B in an X direction is an area 70 for forming N<+> -type source diffusion wiring layer wherein an N<+> -type diffusion source wiring extending in a Y direction is formed. Among them, a space between the second field oxide films 2B is a contact formation area 80 for connecting the N<+> -type source diffusion wiring layer extending in a Y direction with a metallic source line extending in an X direction. A polycrystal silicon pattern made of conductive film on the first layer is adhered to the upper face of silicon oxide film in the area 80 and further is extended thereon in an X direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable read-only memory nonvolatile semiconductor memory device (hereinafter referred to as "E").
EPROM) and a manufacturing method thereof, and more particularly, to a manufacturing method of a flash EEPROM capable of electrically erasing data collectively.

[0002]

2. Description of the Related Art A general flash EEPROM performs writing by injecting electrons generated by impact ionization into a floating gate, and in batch erasing, a control gate and a substrate are grounded, a drain is opened, and a high voltage is applied to a source. This is done by applying a voltage and tunneling electrons from the floating gate to the source.

On the other hand, the flash EEPROM disclosed in Japanese Patent Application Laid-Open No. 7-161853 (Japanese Patent Application No. 5-325787) is the invention of the inventor of the present invention.
The N ⁺ type source and the N ⁺ type drain have a symmetrical structure in which the P ⁺ type region is in contact with each other, and data writing is performed by floating electrons generated by impact ionization generated near the drain of the selected EEPROM cell. The single erasure is performed by injecting into the substrate, and hot erasing is performed by injecting hot carriers generated by the avalanche breakdown generated between the source to which a high voltage is applied and the substrate.

Any type of EEPROM basically has a circuit as shown in FIG. That is, control gate (CG), floating gate (FG), source (S)
And EEPROM cell 10 having a drain (D)
0s are arranged in a matrix and word lines (W ₁ ,
_{W 2, W 3 ......... W n} ) of each commonly connected control gates of the EEPROM cells arranged in the row direction, bit lines (B _1, B ₂ ...... arranged in the column direction each B _n) The drains of the formed EEPROM cells are commonly connected.
Further, each of the source lines (SL ₁ , SL _2, ..., SL _n ) commonly connects the sources of the EEPROM cells arranged in the column direction, and these source lines are connected to the common source line S.
It is connected to L so that the same source voltage is applied to the sources of all the EEPROM cells.

Here, the word line is composed of a polycrystalline silicon film or a polycide film which is continuously formed with the control gate, and the bit line is composed of a metal wiring such as aluminum and contacts each of the N ⁺ type drains. There is. On the other hand, the source line can be composed of N ⁺ -type source diffusion wiring layer which is continuously formed with the N ⁺ -type source.

However, in the flash EEPROM, all the EEPROM cells are erased at the same time, so if the source line is composed of only the diffusion layer having a high layer resistance, the EEPR is formed.
This is inconvenient because the source voltage varies greatly among the OM cells. Therefore, a source line made of aluminum or the like (hereinafter referred to as a metal source line) is connected to the N ⁺ type source diffusion wiring layer for every several EEPROM cell rows to suppress the variation of the source voltage among the EEPROM cells. .

On the other hand, a general method of manufacturing an EEPROM, not limited to a flash EEPROM, is to first form a pattern in the width direction of the floating gate by patterning one direction of a polycrystalline silicon film which is the first conductive film. After that, the word line including the control gate is formed by patterning the second-layer conductive film such as a polycide film, and the same shape as the control gate is formed in the direction perpendicular to the first-layer polycrystalline silicon film. Is patterned to form a shape in the length direction of the floating gate.

In the case of manufacturing the flash EEPROM by following such a conventional technique, the method shown in FIGS. 15 to 17 is used.

FIG. 15 is a plan view showing a polycrystalline silicon film pattern (hatched) 4 which is a first-layer conductive film formed in the Y direction. A long first field oxide film 2A and a drum-shaped second field oxide film 2B are formed in an array on the main surface of a P-type silicon substrate. Between the first field oxide films 2A in the Y direction is a cell formation region 60 forming an EEPROM cell,
First and second field oxide films 2 in the X direction
A, 2B between is N ⁺ -type source diffusion wiring layer forming region 70 of N ⁺ -type source diffusion wiring layer is formed extending in the Y-direction, extending these between the second field oxide film 2B is a Y-direction This is a contact formation region 80 in which the existing N ⁺ type source diffusion wiring layer and the metal source line extending in the X direction are connected.

The polycrystalline silicon film pattern 4 forming the floating gate is formed with a width W (dimension in the Y direction) W of the floating gate and a band extending in the X direction with a space 7 kept between them. Further, the EEPRs adjacent to each other by this interval
The floating gate of the OM cell is isolated on the first field insulating film 2A.

Since this polycrystalline silicon film pattern 4 is a film forming a floating gate, it is unnecessary in the contact forming region 80 where the N ⁺ type source diffusion wiring layer and the metal source line are in contact with each other. No polycrystalline silicon film is formed in the region 80.

16 (A), (B), (C) and (D) show the steps after A shown in FIG. 15 in AA, BB, CC and DD of FIG. 15, respectively. It is sectional drawing containing and shown. The selectively formed field insulating film 2A,
A silicon oxide film 3 serving as a first gate insulating film is formed on the main surface of the P-type silicon substrate 1 which is partitioned and exposed by 2B, and a polycrystalline silicon film pattern 4 patterned only in the Y direction is formed thereon. An ONO film (silicon oxide film-silicon nitride film-silicon oxide film) 5 to be a second gate insulating film is formed thereon, and a polycide film 6 to be a control gate material is formed on the entire surface thereof. .

As shown in (A) and (B), since the polycrystalline silicon film pattern 4 does not exist in the contact formation region 80, the silicon oxide film 3 and the ONO film 5 are formed on the main surface of the P-type silicon substrate 1. Is integrally formed, and the polycide film 6 is adhered and formed thereon.

FIG. 17 is a sectional view showing a step after FIG. 16, wherein FIGS. 17A, 17B, 17C and 17D are respectively FIGS. 16A, 16B and 16B. (C) and (D)
It corresponds to.

From the state shown in FIG. 16, the polycide film 6, the ONO film 5 and the polycrystalline silicon film pattern 4 are sequentially selectively removed by etching using the photoresist as a mask to perform patterning in the X direction. Y
The word line 16W including the control gate 16 extending in the direction is formed, the second gate insulating film 15 is formed from the ONO film 5, and the X of the polycrystalline silicon film pattern 4 already formed in the Y direction is formed. The floating gate 14 is formed by patterning in the direction, and the first gate insulating film 13 is formed from the silicon oxide film 3 to obtain the gate structure 50 shown in FIGS.

In the above process, a mixed gas system of sulfur hexafluoride and hydrogen bromide is used for the tungsten silicide in the upper part of the polycide film 6, and a mixed gas system of chlorine and hydrogen bromide is used for the lower polysilicon. The ONO film 5 serves as an etching stopper during etching.

Next, the insulating film is etched with a carbon fluoride gas system. At this time, in the contact formation region 80 shown in (A) and (B), the ONO film 5 and the silicon oxide film 3 which are integrally formed by the silicon substrate 1 serving as an etching stopper are etched. on the other hand,
Of the cell formation region 60 and the N ⁺ type source diffusion wiring layer formation region 70 shown in (C) and (D), the contact formation region 8
At locations other than 0, the polycrystalline silicon film pattern 4 serves as an etching stopper to etch the ONO film 5.

Next, the polycrystalline silicon film pattern 4 is etched with a mixed gas system of chlorine and hydrogen bromide. (C),
In the cell formation region 60 and the N ⁺ -type source diffusion wiring layer formation region 70 shown in (D) other than the contact formation region 80, the silicon oxide film 3 serves as an etching stopper to etch the polycrystalline silicon film pattern 4. To be done.

However, at this time, since the silicon substrate 1 made of the same silicon is exposed in the contact formation region 80, the surface of the silicon substrate 1 is also etched to form the recess 10 having a depth of, for example, 0.5 μm. I will end up.

After performing such a series of etching steps by, for example, a parallel plate type dry etcher, while using the field oxide films 2A and 2B and the gate structure 50 as a mask, boron of a P type impurity is rotated while rotating the semiconductor wafer. Ion implantation is performed from an oblique direction, arsenic as an N-type impurity is vertically implanted, and by subsequent activation heat treatment,
The N ⁺ type source 23 and the N ⁺ type drain 22 are formed with the channel region in between, and the N ⁺ type source 23 and the N ⁺ type source 23 are continuously formed.
^{A +} type diffusion source wiring layer 24 is formed, and these N
^{The +} type regions 22, 23 and 24 are in contact with the side surfaces from the bottom surface to form a P ⁺ type region 25 forming a PN junction.

[0021]

In a flash EEPROM in which batch erasing is performed by avalanche breakdown, it is necessary to break down the portion facing the source channel first, and the breakdown withstand voltage of other portions is relatively increased to erase. Although it is necessary to improve efficiency, there is a concern that the above-mentioned related art may cause problems in the following points.

First, since a recess is formed in the substrate in the contact formation region, the withstand voltage at this portion may be lowered and an undesired breakdown may occur. This is compared with the impurity concentration in the peripheral portion of the P ⁺ type region formed from the flat surface, as compared with the peripheral portion of the P ⁺ type region formed from within the recess,
That is, the concave portion 10 shown by A in FIGS. 17 (A) and 17 (B).
This is because the impurity concentration of the P ⁺ type region in the vicinity of the corner of the bottom surface of is high.

Further, the bottom portion of the contact formation region has the same impurity concentration relationship as the portion facing the source channel. Therefore, the bottom of the contact formation region may first break down undesirably.

Further, even in the EEPROM cell, the portion facing the channel of the source and the bottom portion of the source have the same impurity concentration structure. Therefore, the bottom portion of the source may break down undesirably. For this reason, the P ⁺ type region can be provided only in contact with the source channel, but this is not a sufficient countermeasure.

Therefore, it is an object of the present invention to provide a method of manufacturing an EEPROM capable of patterning a gate structure without forming a recess in a substrate in a contact formation region.

Another object of the present invention is to provide an EEP having a relatively increased breakdown voltage of the bottom surface of the contact formation region.
A ROM and a method for manufacturing the same.

Another object of the present invention is to provide an EEPROM capable of reliably increasing the breakdown withstand voltage at the bottom surface portion of the source in the EEPROM cell as compared with the portion facing the channel, and a manufacturing method thereof.

[0028]

A feature of the present invention is that a first conductivity type semiconductor substrate on which a field insulating film is selectively formed and the first conductivity type formed on a main surface of the semiconductor substrate. A source and a drain of a second conductivity type opposite in conductivity type, a first gate insulating film formed on a channel region between the source and the drain, and a first gate insulating film on the first gate insulating film; A nonvolatile memory cell including a formed floating gate, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. A large number of the semiconductor substrates are the first
Direction and a second direction perpendicular to the first direction, the second conductivity type being formed continuously with the sources of the plurality of nonvolatile memory cells arranged in the first direction. Diffusion source wiring layers extend in the first direction, contact portions respectively located in a plurality of the diffusion source wiring layers are arranged in the second direction, and metal source wirings diffuse in the contact portions. In a method of manufacturing a nonvolatile semiconductor memory device connected to a source wiring layer and extending in the second direction, a material film of the first gate insulating film is formed on all exposed surface portions of the semiconductor substrate. The step of forming the first insulating film; and, after depositing the first conductive film serving as the material film of the floating gate on the entire surface, shape the first direction of the floating gate and form the contact formation region. First guide to cover A step of forming a film pattern, a step of forming a second insulating film which is a material film of the second gate insulating film on the first conductive film pattern, and the control on the second insulating film. A step of depositing a second conductive film which will be a material film of a gate, and a step of selectively sequentially etching the laminated film of the second conductive film, the second insulating film and the first conductive film. Patterning into the same plane shape to form a word line including the control gate extending in the first direction from the second conductive film, and shaping the second conductive film pattern in the second direction. A method of manufacturing a nonvolatile semiconductor memory device, wherein the floating gate having the dimension in the second direction defined by forming the floating gate is obtained.

Here, the first conductive film pattern is formed to have a dimension in the first direction of the floating gate by patterning only the first direction of the first and second directions. Then, the first pattern of the strip-shaped first conductive film extending in the second direction and the contact formation regions in which the contact portions arranged in the second direction are formed are covered to form the first pattern. The second pattern of the band-shaped first conductive film extending in the direction 2 can be configured. Alternatively, the first conductive film pattern is
A pattern may be formed in which the dimension of the floating gate in the first direction is formed by a slit, and a portion where the floating gate is formed and a portion where the contact formation region is covered are connected between the slits.

Here, using the gate structure and the field insulating film obtained by patterning the laminated film as a mask, the first conductive film of the second conductivity type is formed in the nonvolatile memory cell forming region and the diffusion source wiring layer forming region. Ion implantation, second ion implantation of the second conductivity type having higher energy and lower dose than the first ion implantation, and first ion implantation
Conduction type ion implantation is performed, whereby the source and drain of the non-volatile memory cell and the diffusion source wiring layer are formed inward from the main surface and a second conductivity type high impurity region and the second conductivity type high impurity region. And a second conductivity type low impurity region formed to be connected to the bottom part of the source and drain, and shallower than the second conductivity type high impurity region on the side of the source and drain on the channel region side. In addition, the first conductivity type high impurity region having a higher impurity concentration can be formed in contact with the semiconductor substrate.

Further, using the gate structure obtained by patterning the laminated film and the field insulating film as a mask, the first ion of the second conductivity type is formed in the nonvolatile memory cell forming region and the diffusion source wiring layer region. Implanting and ion implantation of the first conductivity type are performed, and the energy is higher and the dose amount is lower in the diffusion source wiring layer formation region than in the first ion implantation while the nonvolatile memory cell formation region is masked. The second conductivity type ion implantation is performed, so that the second conductivity type is formed on the side of the source and drain, which is formed by the second conductivity type high impurity region formed inside from the main surface, on the side of the channel region. A first conductivity type high impurity region that is shallower than the high impurity type region and has a higher impurity concentration than the semiconductor substrate, and the diffusion The source wiring has a second-conductivity-type high-impurity region formed inside from the main surface and a second-conductivity-type low-impurity region formed so as to be connected to the bottom of the second-conductivity-type high-impurity region. can do.

Another feature of the present invention is that a source and a drain of a second conductivity type opposite to the first conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type, and the source. Formed on the channel region between the drain and the drain
Gate insulating film, a floating gate formed on the first gate insulating film, and a second gate formed on the floating gate.
A non-volatile semiconductor memory device having a plurality of non-volatile memory cells arranged in a matrix, the non-volatile memory cells having a gate insulating film and a control gate formed on the second gate insulating film. The source and the drain are formed by connecting the second conductivity type high impurity region formed inside from the main surface and the second conductivity type high impurity region bottom portion.
A first conductivity type low-impurity region, and a side region of the source and drain on the channel region side that is shallower than the second conductivity-type high impurity region and has a higher impurity concentration than the semiconductor substrate. A non-volatile semiconductor memory device having a conductive high impurity region formed in contact therewith.

Another feature of the present invention is that the first conductivity type semiconductor substrate on which a field insulating film is selectively formed and the first conductivity type opposite to the first conductivity type formed on the main surface of the semiconductor substrate. A second conductivity type source and drain, a first gate insulating film formed on a channel region between the source and the drain, and a floating film formed on the first gate insulating film. A plurality of nonvolatile memory cells each including a gate, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film are The semiconductor substrates are arranged in a first direction and in a second direction perpendicular to the first direction, and are formed continuously with the sources of the plurality of nonvolatile memory cells arranged in the first direction. The second conductive type diffusion source wiring layer is Contact portions located in a plurality of the diffusion source wiring layers and arranged in the second direction, and metal source wirings are connected to the diffusion source wiring layers at the contact portions. In the non-volatile semiconductor memory device extending in the second direction, a first conductivity type semiconductor that is shallower than the source and drain and has a higher impurity concentration than the semiconductor substrate is formed on a side portion of the source and drain on the channel region side. Impurity regions are formed in contact with each other, and the diffusion source wiring is formed so as to be connected to a second conductivity type high impurity region formed inside from the main surface and a bottom portion of the second conductivity type high impurity region. A non-volatile semiconductor memory device configured to have two conductivity type low impurity regions.

In the above manufacturing method or apparatus, the first insulating film is a silicon oxide film, the first conductive film is a polycrystalline silicon film, and the second insulating film is ON.
The second conductive film may be an O film, and the second conductive film may be a polycide film. Also, generally, the first conductivity type is P-type and the second conductivity type is N-type.

As described above, in the present invention, since the first conductive film of the floating gate material is provided as the second pattern also in the contact formation region, the substrate is etched when the laminated film for obtaining the gate structure is etched. No recess is formed in the. Therefore, the breakdown withstand voltage in the contact region does not decrease.

Alternatively, the diffusion source wiring layer may have a second conductivity type high impurity region at the bottom or a diffusion source wiring layer and a source / drain second conductivity type high impurity region at the bottom.
Since the conductivity type low impurity regions are connected, the breakdown withstand voltage of these bottom portions becomes high and the parasitic capacitance value decreases.

[0037]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

FIGS. 1 to 11 are views showing the method of manufacturing the EEPROM of the first embodiment of the present invention in the order of steps.

First, a plan view of FIG. 1 shows a state in which a field insulating film is formed. In addition, (A), (B) of FIG.
(C) and (D) are portions AA and BB in FIG. 1, respectively.
It is sectional drawing which expanded and showed the part, CC section, and DD section.

1 and 2, a selective thermal oxidation method is used to form a field insulating film on the main surface of the P-type silicon substrate 1 having an impurity concentration of 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻³ .
The first and second field oxide films 2A and 2B hatched in the plan view of FIG. 1 are arrayed. The first field oxide film 2A has a rectangular plane shape, and the second field oxide film has a drum plane shape.

First field oxide film 2 in the Y direction
A cell forming region 60 forming an EEPROM memory cell is located between A and A. Further, in the N ⁺ -type source diffusion wiring layer forming region 70 where the N ⁺ -type diffusion source wiring extending between the first field oxide films 2A and the second field oxide films 2B in the X direction extends in the Y direction is formed. Of these, the contact formation region 80 where the N ⁺ type source diffusion wiring layer extending in the Y direction and the metal source line extending in the X direction are connected between the second field oxide films 2B.

Further, a film thickness of 8 to 15 n is formed on the main surface of the substrate where the first and second field oxide films 2A and 2B are not present.
m silicon oxide film 3 is formed, and this silicon oxide film 3 serves as a first gate insulating film of the EEPROM memory cell.

FIG. 3 shows a film thickness of 100 as the first-layer conductive film.
˜300 nm, for example, a 250 nm-thickness polycrystalline silicon film is deposited, and only the Y direction of the Y direction and the X direction is patterned to extend in the X direction. Is shown in FIG. 4A), and FIGS. 4A, 4B, 4C, and 4D are views AA, BB of FIG. 3, respectively. It is sectional drawing which expanded and showed the part, CC section, and DD section.

In FIGS. 3 and 4, the polycrystalline silicon film pattern 4 has the width W (dimension in the Y direction) W of the floating gate with the interval 7 kept therebetween. W is 0.8-4μ
m, for example 2.5 μm, and the dimension between the first field oxide films 2A in the Y direction, that is, the channel width is 0.5 to 3.0 μm, for example 1.8 μm. Therefore, both ends in the Y direction of the polycrystalline silicon film pattern 4 extend on the first field oxide film 2A. Further, the floating gates of the adjacent EEPROM memory cells are insulated and separated by the space 7 on the first field oxide film 2A. The polycrystalline silicon film pattern 4 and the polycrystalline silicon film pattern 4C are also separated by a space 7. The size of the space 7 is 0.4 to 1.5 μm, for example 0.7 μm.

In the present invention, the polycrystalline silicon film pattern 4C of the first conductive film is formed on the upper surface of the silicon oxide film 3 in the contact formation region 80 and extends in the X direction. It is a feature. The width of the polycrystalline silicon film pattern 4C, that is, the dimension in the Y direction is 1.5 to 6 μm,
For example, it is 4 μm and covers almost the entire contact formation region.

FIGS. 5A, 5B, 5C and 5D, which are cross-sectional views showing steps after FIG. 4, show FIGS. 4A, 4B, 4C and 4C, respectively. It corresponds to (D).

In FIG. 5, an ONO film 5 is deposited on the entire surface as a material film of a second gate insulating film, and polycrystalline silicon is used as a second conductive film which is a material film of a word line including a control gate thereon. Tungsten silicide (WS
i) The polycide film 6 that has produced the film is deposited. The ONO film 5 has a film thickness of 5 to 15 nm, for example, a film thickness of 1
With a 2 nm silicon oxide film as the lower layer, the film thickness is 7 to 12 n.
m, for example, a silicon nitride film having a thickness of 9 nm as an intermediate layer,
It is a composite film having a film thickness of 5 to 15 nm, for example, a silicon oxide film having a film thickness of 7 nm as an upper layer. The thickness of the lower polycrystalline silicon film forming the polycide film 6 is, for example, 15
0 nm, tungsten silicide (WS
i) The film thickness of the film is, for example, 150 nm.

FIG. 6 is a plan view showing a step after FIG. 5, and FIGS. 7A, 7B, 7C, and 7D are portions AA and BB in FIG. 6, respectively. Section, CC section and DD
It is sectional drawing which expands and shows a part.

From the state shown in FIG. 5, the polycide film 6, the ONO film 5 and the polycrystalline silicon film patterns 4 and 4C are sequentially and selectively etched by, for example, a parallel plate type dry etcher using a photoresist (not shown) as a mask. After removal, as shown by hatching in the plan view of FIG. 6, a word line 16W including the control gate 16 extending from the polycide layer 6 in the Y direction is formed, and the ONO film 5 and the second gate are formed. The insulating film 15 is formed, and the floating gate 14 is formed by patterning the polycrystalline silicon film pattern 4 which is already formed in the Y direction in the X direction, and the silicon oxide film 3 is formed into the first gate insulating film 13. After the formation, the gate structure 50 of the EEPROM cell is obtained in the cell formation region 60 as shown in FIGS. It should be noted that, on the second field oxide film 2B, there remains a remaining polycrystalline silicon film 14R which is insulated from the floating gate 14 at an interval 7, but this is not related to the function.

This patterning etching can be carried out under the following conditions, for example, in the above material structure.

First, with respect to the polycide film 6, the surface of the tungsten silicide film is made to have a power of 0.5 to 1.8 by a mixed gas system of sulfur hexafluoride ((SF ₆ ) and hydrogen bromide (HBr).
W / cm ² ) (anode coupling), pressure 150-
Etching is performed at 300 Torr, and then the polycrystalline silicon film is mixed with chlorine (Cl ₂ ) and hydrogen bromide at a power of 0.5 to 1.8 W / cm ² (anode coupling) and a pressure of 300 to 500 Torr. Etching is performed. At this time, all the regions 60, 70, 80 ONO film 5
Serves as an etching stopper.

Next, for the ONO film 5, a carbon fluoride (CF ₄ ) gas system power of 2.0 to 3.0 W / cm is used.
² ) (Anode coupling), pressure 100 ~ 300T
Etching is performed at orr. At this time, the cell formation region 6
0 and the N ⁺ type source diffusion wiring layer forming region 70 excluding the contact forming region 80, the polycrystalline silicon film pattern 4 is formed.
Acts as an etching stopper, and the contact formation area 8
At 0, the polycrystalline silicon film pattern 4C serves as an etching stopper.

Next, with respect to the polycrystalline silicon film patterns 4 and 4C, a mixed gas system of chlorine and hydrogen bromide gives a power of 0.5 to.
1.8 W / cm ² ) (anode coupling), pressure 3
Etching is performed at 00 to 500 Torr. At this time,
The silicon oxide film 3 serves as an etching stopper in all the regions 60, 70, 80.

After that, the silicon oxide film 3 is usually removed by wet etching, and a thin silicon oxide film is newly formed there as a protective film at the time of ion implantation.

As described above, the laminated film structure of the N ⁺ type source diffusion wiring layer forming region 70 and the laminated film structure of the contact forming region 80 excluding the cell forming region 60 and the contact forming region 80 are the same, and the cell forming region 60 is the same. With EEPROM
Since the same polycrystalline silicon film as the polycrystalline silicon film to be the floating gate of the memory cell is also formed in the contact formation region, during the above-described series of etching for forming the gate electrode structure and word line, the contact formation region Undesired depressions are prevented from being formed on the substrate.

FIG. 8 is a plan view showing the subsequent steps,
9A, 9 </ b> B, 9 </ b> C and 9 </ b> D are enlarged cross-sectional views of the AA section, the BB section, the CC section and the DD section of FIG. 8, respectively. is there.

In FIGS. 8 and 9, the field oxide film 2 is formed.
By using A, 2B and the gate structure 50 as a mask, boron of a P-type impurity is ion-implanted from an oblique direction while rotating the semiconductor wafer, arsenic of an N-type impurity is vertically ion-implanted, and the subsequent activation heat treatment is performed. N ⁺ type source 2
3, N ⁺ type drain 22, N ⁺ type source 23, and N ⁺ type diffused source wiring 24 formed continuously, and these N ⁺ type regions 22, 23 and 24 are in contact with the side surface from the bottom surface to PN.
A P ⁺ type region 25 forming a junction is provided. For example, N ⁺
The impurity concentrations of the mold regions 22, 23 and 24 are 10 ¹⁹ to 10 ^21.
cm ⁻³ order, the impurity concentration of the P ⁺ type region 25 is 10 ¹⁸ to
It is on the order of 10 ¹⁹ cm ⁻³ , and the formation locations of these regions are indicated by hatching in the plan view of FIG.

FIG. 10 is a plan view showing the subsequent steps. FIGS. 11A, 11B, 11C and 11D are respectively AA section, BB section and C section in FIG. -C part and D
It is sectional drawing which expands and shows a D section. 10 and 11, after depositing an interlayer insulating film 30 such as BPSG, a contact hole 26 reaching the N ⁺ type diffusion source wiring 24 in the contact forming region 80 is formed in the interlayer insulating film 30, and the cell forming region 60 is formed. Then each N ⁺ type drain 2
A contact hole 27 reaching 2 is formed to form a contact portion. The contact formation region 80 is 1.0 to 5.0 μm, for example 3.0 μm in both the Y and X directions,
The contact hole 26 has a square planar shape with one side of 0.4 to 1.5 μm, for example 0.8 μm.

After that, an aluminum film is deposited on the entire surface and patterned to form a metal source wiring 28 connected to the N ⁺ type diffusion source wiring 24 through the contact hole 26 and extending in the X direction, and the contact hole 27. A bit line 29 extending in the X direction is formed by being connected to the N ⁺ type drain 22 which is a common drain of the left and right memory cells.

As described above, in the embodiment, since the concave portion is not formed on the surface of the silicon substrate 1 in the contact formation region 80, the impurity in the peripheral portion of the P ⁺ type region 25 becomes too high and an undesired breakdown occurs. It can be prevented from occurring.

FIG. 12 is a plan view showing a second embodiment of the present invention and corresponds to FIG. 3 of the first embodiment. In the second embodiment, a polycrystalline silicon layer forming a floating gate is deposited on the entire surface in the cell formation region 60 to expose only the central portion of the field oxide film 2A and both end portions of the field oxide film 2B. A polycrystalline silicon film pattern (shown by hatching in FIG. 12) 34 having the slit 17 opened is formed.

Slit 17 and slit 1 in the Y direction
The distance W between the floating gates 7 and 7 becomes the dimension of the floating gates in the Y direction, that is, the width of the floating gates, and the slits 17 electrically isolate the floating gates of the EEPROM memory cells arranged in the Y direction. That is, the polycrystalline silicon layer pattern 34 of the second embodiment is formed integrally with all the regions 60, 70, 80 by providing slits 17 for necessary insulation separation in the Y direction.

FIG. 13 is a cross-sectional view showing a third embodiment of the present invention. FIGS. 13A and 13B are, respectively, FIGS. 11B and 11D of the first embodiment. ) Is supported.

In FIG. 13, N ⁺ type source 23, N ⁺
A P ⁺ -type region 25 ′ that forms a PN junction by contacting only the upper side surface of the N ⁺ -type diffused source wiring layer 24 formed continuously with the type drain 22 and the N ⁺ -type source 23, that is, N
^A P ⁺ type region 25 ′ shallower than the ⁺ type regions 22, 23 and 24 is formed, and an N ⁻ type region 31 is formed in contact with the bottom surfaces of the N ⁺ type regions 22, 23 and 24.

The impurity concentration of the N ⁺ type regions 22, 23 and 24 is on the order of 10 ¹⁹ to 10 ²¹ cm ^-3 , and the impurity concentration of the shallow P ⁺ type region 25 'is on the order of 10 ¹⁷ to 10 ¹⁹ cm ^-3 . , The impurity concentration of the N ⁻ -type region 31 at the bottom is 10 ¹⁷ to 10
It is on the order of ¹⁹ cm ^-3 .

With such a structure, the field oxide film 2
While rotating the semiconductor wafer using A, 2B and the gate structure 50 as a mask, the dose of arsenic is 1 × 10 ¹⁵ to 1 from the vertical direction in order to obtain the N ⁺ type regions 22, 23 and 24.
× 10 ¹⁶ cm ^-2 ,, energy implanted at 30~80keV, P ⁺ dose of boron to obtain -type region 25 'in an oblique direction ^{1 × 10 13 ~8 × 10 14} cm -2, energy 30 Ion implantation is performed at 100 keV, and arsenic is dosed in a vertical direction of 1 × 10 5 to obtain an N ⁻ type region 31.
^{13 ~8} × 10 ¹⁴ cm ^-2 ,, energy 100~200k
It is obtained by ion implantation at eV and subsequent activation heat treatment.

With such a structure, the breakdown withstand voltage of the PN junction between the N ^- type region 31 at the bottom of the contact and the bottom of the source / drain and the P-type substrate 1 becomes 9 to 12 V, and this value is an avalanche for batch erasing. N ⁺ type source 23 and shallow P ⁺ type region 25 'for generating breakdown
Since the breakdown voltage of the PN junction is much higher than 6 to 8 V, the erase efficiency can be improved without causing a breakdown at an undesired portion. Further, in the third embodiment, as in the first or second embodiment, the method of patterning the gate electrode by using the polycrystalline silicon pattern film for forming the floating gate on the contact formation region is used. For example, the above effect will be further enhanced.

FIG. 14 is a sectional view showing the fourth embodiment.

In the third embodiment, the ion implantation for forming the N ⁻ type regions 31 is performed by the N ⁺ type regions 22, 23, 24.
Of the field oxide films 2A and 2A as well as the ion implantation for forming the P ⁺ -type region 25 '.
Since the B and gate structure 50 is used as a mask, the N ⁻ type region 31 is provided at the bottom of the N ⁺ type diffusion source wiring layer and the bottom of the N ⁺ type source and drain of the EEPROM memory cell. Therefore, the breakdown withstand voltage at the bottoms of the N ⁺ type source and drain is increased similarly to the bottom of the N ⁺ type diffused source wiring layer.

[0070] Depending on the type of EEPROM, however, N at the bottom of the N ⁺ -type source and drain than to increase the breakdown voltage of the bottom of the N ⁺ -type source and drain ^- want to eliminate the influence of the characteristic due to the type region is present There are also things.

In such an EEPROM, the field oxide films 2A and 2B and the gate structure 50 are not used as a mask to perform ion implantation for forming the N ^-- type region.
N ⁺ type region 2 is formed by ion implantation using these as masks.
2, 23, 24 and P ⁺ type region 25 '. After that, a cell formation region 6 for forming an EEPROM memory cell
0 is covered with a photoresist pattern 33, and N ⁺ including a contact formation region 80 in the opening 33A of this pattern.
Ion implantation is performed to selectively expose the type source diffusion wiring layer forming region 70 to form an N ⁻ type region, and after removing the photoresist pattern 33, activation heat treatment is performed.

The N ⁻ type region 32 thus obtained enhances the breakdown withstand voltage at the bottom of the N ⁺ type diffused source wiring layer, while the N ⁻ type region is provided at the bottom of the N ⁺ type source and drain. Since it does not exist, the influence of the characteristic due to the presence of the N ⁻ type region can be eliminated.

[0073]

As described above, according to the present invention, the contact formation region 80 is also provided with the polycrystalline silicon film of the floating gate material as the second pattern 4C.
No recess is formed in the substrate 1 when the stacked films 6, 5, 4, 3 for obtaining the gate structure 50 are etched.
Therefore, the breakdown withstand voltage in the contact region does not decrease.

[0074] Alternatively, the bottom of the N ⁺ -type diffusion source wiring layer 24 or the N ⁺ diffusion source wiring layer 24 and the N ⁺ -type source, the bottom of the drain 23, 22 N ^- -type region 31,
Since 32 is provided, the breakdown voltage of these bottom parts becomes high.

In either case, the breakdown voltage of the portion other than directly below the gate is improved, and only the source side portion facing the channel region undergoes avalanche breakdown, so that the erase current can be reduced and the erase efficiency can be improved. .

Further, by providing the N ^-- type regions 31 and 32, the junction parasitic capacitance is reduced, so that the reading speed is improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a step of a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of each part in FIG.
(A), (B), (C) and (D) respectively show AA section, BB section, CC section and DD section of FIG.

FIG. 3 is a plan view showing a step subsequent to FIG.

FIG. 4 is an enlarged cross-sectional view of each part in FIG.
(A), (B), (C) and (D) respectively show AA section, BB section, CC section and DD section of FIG.

FIG. 5 is a cross-sectional view showing a step after FIG.
(B), (C) and (D) are respectively (A) and (A) of FIG.
It corresponds to (B), (C) and (D).

FIG. 6 is a plan view showing a step subsequent to FIG.

FIG. 7 is an enlarged sectional view of each part in FIG.
(A), (B), (C) and (D) respectively show AA section, BB section, CC section and DD section of FIG.

FIG. 8 is a plan view showing a step subsequent to FIG. 6;

9 is an enlarged cross-sectional view of each part in FIG.
(A), (B), (C) and (D) respectively show AA section, BB section, CC section and DD section of FIG.

10 is a plan view showing a step subsequent to FIG.

11 is an enlarged cross-sectional view of each portion in FIG. 10, and (A), (B), (C), and (D) are portions AA, BB, and CC in FIG. 10, respectively. Section and DD section are shown.

FIG. 12 is a plan view showing the manufacturing method according to the second embodiment of the present invention, which corresponds to FIG. 3 of the first embodiment.

FIG. 13 is a cross-sectional view showing a third embodiment of the present invention, in which (A) and (B) correspond to (B) and (D) of FIG. 11 of the first embodiment, respectively. There is.

FIG. 14 is a sectional view showing a fourth embodiment of the present invention.

FIG. 15 is a plan view showing a conventional manufacturing method.

16 is a cross-sectional view showing a step after FIG. 15,
(A), (B), (C) and (D) are respectively shown in FIG.
It corresponds to the AA section, the BB section, the CC section and the DD section.

FIG. 17 is a cross-sectional view showing a step after FIG.
16 (A), (B), (C) and (D) are shown in FIG.
(A), (B), (C), and (D).

FIG. 18 is a diagram showing an outline of a flash EEPROM.

[Explanation of symbols]

1 P-type silicon substrate 2A, 2B Field oxide film 3 Silicon oxide film (material film of first gate insulating film) 4 Polycrystalline silicon film pattern (material film of floating gate) 4C Polycrystalline silicon film pattern 5 ONO film (No. 2 Material film of gate insulating film) 6 Polycide film (material film of word line including control gate) 7 Interval 10 Recess 13 First gate insulating film 14 Floating gate 14R Remaining polycrystalline silicon film 15 Second gate insulation Film 16 Control gate 16W Word line 17 Slit 21 Channel region 22 N ⁺ type drain 23 N ⁺ type source 24 N ⁺ type diffusion source wiring layer 25 P ⁺ type region 25 'Shallow P ⁺ type region 26 N ⁺ type diffusion source wiring the contact hole 27 the contact hole 28 a metal source line 29 bit lines to N ⁺ -type drain 30 interlayer insulating films 31 and 32 ^- type region 33 the photoresist pattern 33A photoresist pattern opening 34 polycrystalline silicon layer pattern (material film of the floating gate) of the 50 gate structure 60 cell forming region 70 N ⁺ -type source diffusion wiring forming region 80 contact region 100 EEPROM cells

Claims (14)

[Claims] 1. A semiconductor substrate of a first conductivity type in which a field insulating film is selectively formed, and a second conductivity type of a conductivity type opposite to the first conductivity type formed on a main surface of the semiconductor substrate. Source and drain, a first gate insulating film formed on a channel region between the source and the drain, a floating gate formed on the first gate insulating film, and the floating gate A large number of non-volatile memory cells each having a second gate insulating film formed on the semiconductor substrate and a control gate formed on the second gate insulating film have the semiconductor substrate formed on the semiconductor substrate as the first substrate. Direction and a second direction perpendicular to the first direction, and of a second conductivity type formed continuously with the sources of the plurality of nonvolatile memory cells arranged in the first direction. A diffusion source wiring layer extends in the first direction, The contact portions respectively located in the plurality of diffusion source wiring layers are arranged in the second direction, and the metal source wirings are connected to the diffusion source wiring layers at the contact portions and extend in the second direction. A method of manufacturing a non-volatile semiconductor memory device, comprising: forming a first insulating film to be a material film of the first gate insulating film on all exposed surface portions of the semiconductor substrate; Forming a first conductive film pattern on the entire surface of the floating gate and forming a first conductive film pattern covering the contact formation region in the first direction; Forming a second insulating film to be a material film of the second gate insulating film on the first conductive film pattern; and forming a second conductive film to be a material film of the control gate on the second insulating film. Deposit membrane And a step of patterning the stacked film of the second conductive film, the second insulating film, and the first conductive film in the same plane shape by selectively sequentially etching and extending in the first direction. A word line including the existing control gate is formed from the second conductive film, and the second line of the first conductive film pattern is formed.
A method of manufacturing a nonvolatile semiconductor memory device, characterized in that the floating gate having dimensions defined in the second direction is obtained by forming a shape in the direction of. 2. The first conductive film pattern is the first conductive film pattern.
By patterning only the first direction of the second direction and the second direction, the size of the floating gate in the first direction is formed to form a strip-shaped first extending in the second direction.
The first pattern of the conductive film and the first strip-shaped extending in the second direction, covering the contact formation regions in which the contact portions arranged in the second direction are formed, respectively.
2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the conductive film is configured to have a second pattern. 3. The first conductive film pattern is formed by forming the dimension of the floating gate in the first direction by slits, and the portions forming the floating gate between the slits and the portions covering the contact formation region. 2. The method for manufacturing a non-volatile semiconductor memory device according to claim 1, wherein the pattern is connected to and. 4. The first insulating film is a silicon oxide film, the first conductive film is a polycrystalline silicon film, and the second insulating film is an ONO film (silicon oxide film-silicon nitride film-silicon oxide film). 2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the second conductive film is a polycide film. 5. The first conductivity type second region is formed in the non-volatile memory cell formation region and the diffusion source wiring layer formation region by using the gate structure obtained by patterning the laminated film and the field insulating film as a mask. Ion implantation,
A second conductivity type second ion implantation having a higher energy and a lower dose amount than the first ion implantation and a first conductivity type ion implantation are performed, whereby the source and drain of the nonvolatile memory cell and the diffusion are performed. The source wiring layer has a second-conductivity-type high-impurity region formed inside from the main surface and a second-conductivity-type low-impurity region formed so as to be connected to the bottom of the second-conductivity-type high-impurity region. A first conductivity type high impurity region, which is shallower than the second conductivity type high impurity region and has a higher impurity concentration than the semiconductor substrate, is formed in contact with a side portion of the source and drain on the channel region side. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein 6. The first conductivity type first layer is formed in the non-volatile memory cell formation region and the diffusion source wiring layer formation region by using the gate structure obtained by patterning the laminated film and the field insulating film as a mask. And ion implantation of the first conductivity type are performed to increase the energy and lower the dose in the diffusion source wiring layer formation region in comparison with the first ion implantation while masking the non-volatile memory cell formation region. The second ion implantation of the second conductivity type is performed, so that the second ion formed from the main surface to the inside
A first-conductivity-type high-impurity region that is shallower than the second-conductivity-type high-impurity region and has a higher impurity concentration than the semiconductor substrate is formed on a side portion of the source and drain formed of the conductivity-type high-impurity region on the channel region side. Are formed in contact with each other,
The diffusion source wiring layer has a second conductivity type high impurity region formed inside from the main surface and a second conductivity type low impurity region formed by being connected to a bottom portion of the second conductivity type high impurity region. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the method is provided. 7. The first conductivity type is a P type, and the second conductivity type is a P type.
The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the conductivity type is N type. 8. A source and a drain of a second conductivity type opposite to the first conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type, and between the source and the drain. A first gate insulating film formed on the channel region of
A floating gate formed on the first gate insulating film,
A second gate insulating film formed on the floating gate;
In a non-volatile semiconductor memory device having a plurality of non-volatile memory cells arranged in a matrix, the non-volatile memory cell having a control gate formed on the second gate insulating film, the source and the drain having a main surface. And a second conductivity type high impurity region formed inside and a second conductivity type low impurity region formed so as to be connected to a bottom portion of the second conductivity type high impurity region. A first conductivity type high impurity region shallower than the second conductivity type high impurity region and having a higher impurity concentration than the semiconductor substrate is formed in contact with a side portion of the drain on the channel region side. Nonvolatile semiconductor memory device. 9. The first gate insulating film is composed of a silicon oxide film, the floating gate is composed of a polycrystalline silicon film, the second gate insulating film is composed of an ONO film, and the control gate is composed of: 9. The non-volatile semiconductor memory device according to claim 8, wherein the non-volatile semiconductor memory device comprises a polycide film. 10. The non-volatile semiconductor memory device according to claim 8, wherein the first conductivity type is P type, and the second conductivity type is N type. 11. A semiconductor substrate of a first conductivity type in which a field insulating film is selectively formed, and a second conductivity type of a conductivity type opposite to the first conductivity type formed on a main surface of the semiconductor substrate. Type source and drain, a first gate insulating film formed on a channel region between the source and the drain, a floating gate formed on the first gate insulating film, and the floating gate A large number of non-volatile memory cells each having a second gate insulating film formed on the semiconductor substrate and a control gate formed on the second gate insulating film have the semiconductor substrate formed on the semiconductor substrate as the first substrate. Direction and a second direction perpendicular to the first direction, and of a second conductivity type formed continuously with the sources of the plurality of nonvolatile memory cells arranged in the first direction. The diffusion source wiring layer extends in the first direction Contact portions respectively located in the plurality of diffusion source wiring layers are arranged in the second direction, and metal source wirings are connected to the diffusion source wiring layers at the contact portions and extend in the second direction. In the nonvolatile semiconductor memory device described above, a first conductivity type high impurity region shallower than the source and drain and having a higher impurity concentration than the semiconductor substrate is formed in contact with a side portion of the source and drain on the side of the channel region. And the diffusion source wiring layer is formed of a second conductivity type high impurity region formed inward from the main surface and a second conductivity type low impurity region formed by being connected to the bottom of the second conductivity type high impurity region. And a non-volatile semiconductor memory device. 12. The source and drain are second conductivity type high impurity regions formed inward from the main surface and second conductivity type low impurity regions formed by being connected to the bottom of the second conductivity type high impurity regions. 12. The non-volatile semiconductor memory device according to claim 11, wherein said first conductivity type high impurity region is shallower than said second conductivity type high impurity region of said source and drain. 13. The first gate insulating film is formed of a silicon oxide film, the floating gate is formed of a polycrystalline silicon film, the second gate insulating film is formed of an ONO film, and the control gate is formed. The nonvolatile semiconductor memory device according to claim 11, wherein the nonvolatile semiconductor memory device is composed of a polycide film. 14. The nonvolatile semiconductor memory device according to claim 11, wherein the first conductivity type is P type and the second conductivity type is N type.