JPH0950421A - Common bus data collecting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the operation efficiency of a processor as the entire system without stopping the processing operation of the processor even in the case the contention of a common bus is caused between the respective processors when the respective processors repeatedly perform the input/output processings or the like of data through the common bus. SOLUTION: Respective memories 21A and 21B for input/output are provided corresponding to the respective processors between the common bus 1 and the respective processors 11A and 11B and the respective processors 11A and 11B repeatedly execute write and read processings to the corresponding respective memories 21A and 21B for input/output at respective time intervals t1 and t2 respectively determined beforehand. Then, In the respective write and read processings, a processing requiring repetition is executed at a predetermined first timing within the time interval and a priority processing to be arbitrarily required is executed at a predetermined second timing within the time interval and the common bus 1 is accessed at a timing other than the respective timings within the time interval in the memories 21A and 21B for input/output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system in which a plurality of processors collect data from an input / output device or a recording device connected to the same common bus via the common bus. The present invention relates to a common bus data collection method for accessing data and collecting data from an input / output device or a recording device.

[0002]

2. Description of the Related Art Generally, in this type of common bus access control, the use efficiency of the bus is reduced due to the occurrence of waiting time (hereinafter, wait), and the priority of the common bus access to a specific device (including a processor) Unbalanced usage frequency is a problem.

Therefore, in order to avoid such a problem, a method of cyclically switching the priority of bus use (for example, Japanese Patent Laid-Open No. 56-97129) and weighting of the priority of bus use are performed. Method for increasing the bus usage frequency of a device having a higher priority (for example, Japanese Laid-Open Patent Publication No. 1-21)
No. 70161), a method of arranging two types of bus use priorities and circulating them to average the bus use frequency of each device (for example, JP-A-3-6764), and a bus use request signal in advance. After outputting and storing the request signal in each device connected to the common bus, the request signal of the device that processed on the bus is discarded and the frequency of bus usage is averaged among the devices. A method (for example, JP-A-3-132854) has been proposed.

[0004]

However, in any of the above-mentioned methods, when each processor repeatedly performs input / output processing of data via the common bus and the contention of the common bus occurs, There is a drawback in that the other processors remain in a wait state until the processing of the processor using is finished, and therefore the operating efficiency of the processor is reduced as a whole system. Further, even in the above-described method in which the bus usage priority is cyclically assigned among the processors or averaged by a procedure, if any processor needs to perform a very high-priority process, it is still waited. However, there is a problem that the process is stopped due to the delay.

Therefore, according to the present invention, when the processors repeatedly perform input / output processing of data via the common bus, even if contention for the common bus occurs between the processors, the operating efficiency of the processor as a whole system is improved. In addition, it is an object of the present invention to prevent the high-priority processing from being stopped when an arbitrary processor needs to perform the high-priority processing.

[0006]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention provides a common bus in a system including a plurality of processors and a device which is accessed by each processor via a common bus to collect data. An input / output memory is provided between each processor and each processor, and when each processor accesses the above-mentioned device via a common bus, the processing of writing and reading data to and from each corresponding input / output memory is performed. The process is repeatedly executed at different time intervals, and among the processes of writing and reading data, the process that needs to be repeated is executed at the predetermined first timing within the above time interval, and any necessary priority can be given. The process is executed at a predetermined second timing within the above time interval. As a result, when a process that needs to be repeated is being executed, other processors can execute the process without waiting even if bus contention occurs. And the priority process can be executed without being stopped even if the priority process occurs arbitrarily.

Further, a notifying means for notifying the use status of the common bus to each processor and the input / output memory is provided. Therefore, the processor can easily detect contention for the common bus. Further, the input / output memory is configured to repeatedly access the common bus at timings other than the first and second timings of the above time interval.
As a result, contention on the common bus of each processor can be avoided.

[0008]

1 is a block diagram showing the configuration of a system to which a common bus data collection system according to the present invention is applied. In the figure, 1 is a common bus, 2 is a bus monitor circuit, 11A and 11B are processors, 21A and 21B are input / output memories, 31A and 31B are memory buffers,
41A and 41B are bus buffers, 51A and 51B are timing control circuits, and 61A and 61B are devices.

That is, the processor 11A which performs each processing in the system is connected to the common bus 1 via the memory buffer 31A, the input / output memory 21A and the bus buffer 41A. Further, the processor 11B is connected to the common bus 1 via the memory buffer 31B, the input / output memory 21B, and the bus buffer 41B. Further, the output signal of the bus monitor circuit 2 which is connected to the common bus 1 and monitors the usage state of the common bus 1 is sent to the timing control circuits 51A and 51B. In this case, the timing control circuit 51A controls the input / output memory 21A and the bus buffer 41A according to the bus use state signal from the bus monitor circuit 2. In addition, the timing control circuit 51
B controls the input / output memory 21B and the bus buffer 41B in response to the bus use state signal from the bus monitor circuit 2.

In the system thus constructed,
The data collection processing operation of each processor 11A, 11B will be described based on the time chart of FIG. The processor 11A in this system repeatedly accesses the devices 61A and 61B connected to the common bus 1 to perform data writing and data reading processes. Further, the processor 11A performs high-priority processing according to a request from the system generated at an arbitrary time by the time-division processing, and thus accesses the devices via the common bus 1 at this arbitrary time and writes data. Perform processing and reading processing. The processor 11B also performs the same processing operation as the processor 11A.

In the present invention, the processing interval (hereinafter, term) of each processor is determined for each processing timing of writing and reading in such a processor 11A, 11B, and within this determined term. The timing of performing the above-described repeated processing and the timing of performing high-priority processing that occurs at an arbitrary time are determined.

That is, the processing of the processor 11A is as shown in FIG.
As shown in (a), the time MWa for writing the bus access data for the repetitive processing in the input / output memory 21A.
1 and time MRa1 for reading the bus access data for repetitive processing from the input / output memory 21A are performed at a predetermined timing in one term of the time t1. Further, as for the access (writing / reading) to the input / output memory 21A at the time of arbitrarily occurring high-priority processing, as shown in FIG. 2 (a), the predetermined timing MWr1 in the one term is set. , MRr1.

In the input / output memory 21A,
As shown in FIG. 2B, the connected processor 11A
Specified timing MWa in the same 1 term as
1, MRa1, MWr1, and MRr1 write and read data, and at the timing BR / W1, as shown in FIGS.
The common bus 1 is accessed via A.

Next, regarding the processing of the processor 11B, as shown in FIG. 2 (c), the time interval t2 different from that of the processor 11A is set to 1 term, and the iterative processing is performed at predetermined timings MWa2 and MRa2. I,
Arbitrarily generated priority processing is defined timing MWr
2, MRr2. In addition, the input / output memory 21B
Then, as shown in FIG. 2D, a predetermined timing M in the same one term as the connected processor 11B is set.
Data is written and read by Wa2, MRa2, MWr2, and MRr2, and access to the common bus 1 is performed via the bus buffer 41A at timing BR / W2 as shown in FIGS. 2 (d) and 2 (e). To do.

In this way, each processor 11A, 11B
Access times for the respective input / output memories 21A, 21B are set to fixed constant time intervals different from each other, and access times to the common bus 1 of the input / output memories 21A, 21B are also set to different fixed constant time intervals. By being defined, contention of data on the common bus 1 can be avoided.

By the way, since the processor 11A and the processor 11B have different operating reference clocks and different term lengths, the common bus 1 shown in FIG.
Both access timings BR / W1, B shown in (e)
R / W2 may conflict. Here, for example, if the processor 11B has accessed the common bus 1 first, the bus monitor circuit 2 that monitors the common bus 1 determines that any processor is using the bus by the timing control circuit 51A and the timing. Notify the control circuit 51B.

In this case, the timing control circuit 51A is
The processor 11B controls to close the bus buffer 41A until the use of the common bus 1 is completed. As a result, data collision on the common bus 1 is avoided. Here, the contention time on the common bus 1 as described above is only when the bus access time of each of the input / output buffers 41A and 41B is within the predetermined time in the term determined as described above. So it's a very short time. Further, if the processing of the processor is not completed within one term due to the occurrence of the access conflict of the common bus 1 or the like, the processing can be ended within at least the following several terms, so that the processing in each of the processors 11A and 11B is performed. The delay can be minimized.

Furthermore, once each processor writes the processing command or the like in the corresponding input / output memory, it is possible to eliminate the wait depending on the contention on the common bus 1, and thus the common Even if contention occurs on the bus 1, the processor can execute other processing than the access to the common bus 1.

By thus defining the access time to the common bus 1 so as to be fixedly accessed at fixed time intervals, the bus occupancy ratio among the processors is averaged, and the access to the common bus is suppressed. By reducing the number of waits due to competition, it is possible to improve the processing efficiency of the entire system.

[0020]

As described above, according to the present invention, an input / output memory is provided between the common bus and each processor so as to correspond to each processor, and each processor accesses the above-mentioned device through the common bus. In this case, the process of writing and reading data to and from each corresponding input / output memory is repeatedly executed at each predetermined time interval, and among the processes of writing and reading, the process that needs to be repeated is described above. Since the process is executed at the first predetermined timing within the time interval and the optional priority process is executed at the second predetermined timing within the above time interval, the process that needs to be repeated is If there is bus contention when it is running, it can do its work without waiting on the processor, thus Both can be improved operating efficiency of the processor as a whole arm, can be executed without the process even if the priority processing is arbitrarily generated is stopped. Further, since the usage status of the common bus is notified to each processor and the input / output memory, the processor can easily detect the competition of the common bus. Further, since the input / output memory is configured to repeatedly access the common bus at timings other than the first and second timings of the above time interval, it is possible to avoid contention of each processor on the common bus.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a system to which a common bus data collection method according to the present invention is applied.

FIG. 2 is a timing chart showing operation timings of respective parts constituting the system.

[Explanation of symbols]

1 ... Common bus, 2 ... Bus monitor circuit, 11A, 11B ...
Processors, 21A, 21B ... Input / output memory, 31
A, 31B ... Memory buffer, 41A, 41B ... Bus buffer, 51A, 51B ... Timing control circuit, 6
1A, 61B ... Device.

Claims (3)

[Claims] 1. A system comprising a plurality of processors and a device which is accessed by each of the processors via a common bus to collect data, the system being provided between the common bus and the processors in correspondence with each processor. An output memory is provided, and when each processor accesses the device via the common bus, data writing and reading processing with respect to each corresponding input / output memory are performed at different time intervals. Of the write and read processes that are repeatedly executed, the process that needs to be repeated is executed at a predetermined first timing within the time interval, and the optional priority process is performed within the time interval. Executed at a second predetermined timing to collect data from the device via the input / output memory and a common bus. Common bus data collection system, characterized in that. 2. The common bus data collection method according to claim 1, further comprising notifying means for notifying the use status of the common bus to each processor and the input / output memory. 3. The common bus data collection method according to claim 1, wherein the input / output memory repeatedly accesses the common bus at timings other than the first and second timings within the predetermined time interval. A common bus data collection method characterized in that