JP3219974B2 - Multiple processing of synchronous type I / O instructions - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for multiplexing synchronous type input / output instructions issued from a plurality of instruction processors.

[0002]

2. Description of the Related Art Synchronous type input / output instructions are generally implemented by a hardware interface between the instruction processor and the input / output processor. , An input / output interrupt that reports the end of an instruction, and the instruction processor and the input / output processor execute the instruction in synchronization with each other. Since this hardware interface is occupied from the start to the end of one synchronous type input / output instruction, only one synchronous type input / output instruction can be executed at the same time.

In order to process synchronous type input / output instructions in a multiplex manner, the interface between each instruction processor and each input / output processor is independently provided, so that the execution of synchronous type input / output instructions from a plurality of instruction processors can be performed. Are performed in parallel, but as the number of instruction processors and input / output processors increases, the amount of hardware increases.

On the other hand, the asynchronous type input / output instruction proceeds to the next instruction when the instruction processor registers the instruction in the queue, and the input / output processor asynchronously reads the instruction from the queue and executes the instruction. The output instruction can be processed, but the time from when the instruction is activated to when it is executed is uncertain.

FIG. 4 is a diagram showing a conventional data processing system. Reference numeral 1 denotes a plurality of instruction processors for analyzing a program and performing input / output instruction activation and termination processing for the input / output processor; 2, an interface control device for connecting one instruction processor to one input / output processor; A selector for selecting a processor, a plurality of input / output processors for accepting and executing activation of an input / output instruction and reporting the end thereof, a channel path control unit for selecting and activating a channel, and a device for activating a device A channel 7, a storage device accessible from both the instruction processor 1 and the input / output processor 4, a storage area 8 for synchronous input / output instruction start information common to a plurality of instruction processors, and a reference numeral 9 asynchronous with the synchronous type input / output instruction It is a program that has type I / O instructions. Each channel 6 is connected to a device (not shown) or another data processing system.

FIG. 5 is a diagram for explaining the flow of processing of a conventional synchronous type input / output instruction. The operation will be described assuming that n instruction processors simultaneously execute, for example, synchronous type input / output instructions. The same applies to a case where a plurality of instruction processors out of n units simultaneously execute input / output instructions or a case where a plurality of instruction processors sequentially execute input / output instructions.

First, the n instruction processors 1 request acquisition of a storage area 8 for synchronous input / output instruction start information on the storage device 7. For example, assume that the instruction processor 1a has acquired this storage area 8. The instruction processor 1a stores command information and instruction information of a device to be activated in the storage area 8 as activation information for synchronous input / output instructions.

Thereafter, the instruction processor 1a issues a selection signal for selecting the input / output processor 4 and an input / output activation to the interface control device 2. The selector 3 of the interface control device 2 selects, for example, the input / output processor 4a and sends an input / output activation 201. Input / output processor 4a
Of the interface control device 2
, An input / output activation response 202 is returned to the instruction processor 1a, and the channel path control unit 5 refers to the activation information in the storage area 8 on the storage device 7, selects the channel 6, and activates the channel. I do.

The channel 6 activates the designated device to execute the processing 203 of the synchronous type input / output instruction, and when the processing in the channel 6 and the device is completed, the channel 6
Reports an end interrupt to the channel path control unit 5. In response, the channel path control unit 5 sends the input / output interrupt 204 to the instruction processor 1a via the interface control device 2.
Report. The instruction processor 1a has an input / output interrupt 204
Is received, the end report 205 is executed for the program 9.

As described above, the interface controller 2 and the channel path controller 5 are occupied by one instruction processor from the reception of the input / output activation to the reporting of the input / output interrupt. After the input / output instruction has been completed, the second instruction processor operates, and similarly the nth instruction processor is sequentially executed. Therefore, the processing capability of this data processing system is equivalent to the case where n-1 instruction processors are stopped and one instruction processor executes n synchronous type input / output instructions. Even with a plurality of instruction processors, sufficient processing performance cannot be obtained.

[0011]

As the number of instruction processors increases, the number of issued I / O instructions also increases. As a result, asynchronous type I / O instructions have been developed, and many instructions can be executed with less hardware. Can be processed. However, in recent years, due to the demand for processing speed, it has become necessary to perform high-speed processing again using synchronous type input / output instructions. For this reason, even in a system which has been mainly processing asynchronous type instructions, it has been necessary to process synchronous type input / output instructions from a plurality of instruction processors. Since another synchronous type input / output instruction cannot be executed until the output instruction is completed, another instruction processor has to wait, and there has been a problem that high-speed processing cannot be performed.

An object of the present invention is to provide a synchronous type input / output instruction multiple processing method in which, when synchronous type input / output instructions are issued from a plurality of instruction processors, the instructions are processed in a multiplexed manner to speed up the processing. Is to do.

[0013]

In order to achieve the above object, according to the present invention, a synchronous type input / output instruction (hereinafter, referred to as an input / output instruction) is executed for an input / output processor, and a termination process of the instruction is executed. A plurality of instruction processors that receive the input / output instruction, return a response to the instruction processor, select a channel based on the activation information and activate the channel, and a device based on the activation information. And a plurality of input / output processors having a plurality of channels for executing the processing of the input / output instructions, and an interface control means for connecting the instruction processor and the input / output processor selected by the instruction processor. , A data processing system comprising: a storage unit in which the start information is stored and accessed by the plurality of instruction processors and the plurality of input / output processors. A method of processing input / output instructions issued from the plurality of instruction processors in a multiplex manner, wherein, among the plurality of instruction processors, activation information and information for identifying the instruction processors are written in the storage means. One instruction processor is selected, input / output activation of channel path control means in the input / output processor selected by the first instruction processor is instructed, and the first instruction processor is instructed in response to the input / output activation. A response is returned, and a channel and a device are activated based on the activation information. In response to the activation of the device, an input / output interrupt is notified from the channel path control means to the first instruction processor. When notified, the interface control means and the channel path control means are released to another instruction processor. It is.

When the channel is activated, the identification information is read from the storage means and stored in the channel, and is designated by the identification information in the channel in response to completion of the processing in the device. Information including an end notification is stored in an area in the storage unit, and the first instruction processor notified of the input / output interrupt stores information including the end notification in the area allocated to the instruction processor. It is characterized by polling the area until it is stored.

[0015]

The instruction processor issues a synchronous type input / output instruction to the input / output processor, and when the input / output processor accepts the activation, releases the interface between the instruction processor and the input / output processor to allow the input / output processor to execute the instruction. Enable another synchronous type input / output instruction. The instruction processor performs polling until an end report is received in the storage area, the input / output processor executes processing of the received synchronous type input / output instruction, and stores an end notification in the storage area after the processing is completed. When the instruction processor receives the termination notification,
End the synchronous type I / O instruction. Thus, while the input / output processor is executing the processing of one synchronous type input / output instruction, it can accept the activation of the synchronous type input / output instruction from another instruction processor and execute the processing. Can be multiplexed up to the number of instruction processors.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of the data processing system of the present invention. The instruction processor 1 and the interface control device 2 are the same as the conventional one described in FIG. In the present invention, the storage device 7 is provided with a storage area 11 corresponding to the instruction processor and a storage area 10 for identification information of the instruction processor (instruction processor number) in the storage area 8 for the activation information. An area 12 for storing instruction processor identification information and device information is provided in the channel 6 of the input / output processor 4.

Storage area 11 corresponding to each instruction processor
For example, the instruction processor 1a corresponds to the storage area 11a, the instruction processor 1b corresponds to the storage area 11b, and a storage area is assigned to each instruction processor.

FIG. 3 shows a storage area 11 assigned to each instruction processor. Each storage area 11 stores information 21 for notifying the end of the synchronous type input / output instruction, information 22 of the execution result of the instruction (for example, success or failure of data transfer and message transfer), and the like. The addresses of the storage areas allocated to the respective instruction processors are fixed addresses.

The identification information storage area 10 in the storage device 7 is for the instruction processor 1 to notify the input / output processor 4 of the identification information (processor number). That is, when the instruction processor 1 activates a synchronous type input / output instruction, the identification information of the instruction processor is stored in the identification information storage area 10 and the input / output processor 4
Reads the identification information 10 of the instruction processor when the synchronous type input / output instruction is activated.

FIG. 2 is a diagram for explaining the flow of processing of a synchronous type input / output instruction according to the present invention. The operation of the present embodiment will be described assuming that n instruction processors simultaneously execute a synchronous type input / output instruction, as described in the conventional example.

As described above, the n instruction processors 1 first request acquisition of the synchronous input / output instruction start information storage area 8 on the storage device 7. For example, assuming that the instruction processor 1a has acquired the storage area 8, the instruction processor 1a stores command information and instruction information of a device to be activated as activation information for a synchronous input / output instruction in the storage area 8, and also stores identification information. The instruction processor number is stored in the storage area 10.

Thereafter, the instruction processor 1a issues a selection signal of the input / output processor 4 and an input / output activation 101 to the interface control device 2. The selector 3 of the interface control device 2 selects, for example, the input / output processor 4a and sends an input / output activation. The channel path control unit 5 of the input / output processor 4a returns an input / output activation response 102 to the instruction processor 1a via the interface control device 2, and then the channel path control unit 5 The channel 6 is selected by referring to the activation information, and the channel is activated.

The channel 6 reads the activation information directly from the activation information storage area 8 on the storage device 7 to obtain the identification information 10 of the instruction processor 1a. Alternatively, as another embodiment, the activation information is received from the channel path control unit 5 when the channel is activated, and the identification information 10 of the instruction processor 1a is obtained. When the channel 6 obtains the identification information of the instruction processor 1a, the identification information of the instruction processor 1a and the activated device information are stored in the storage unit 12 inside the channel 6.

When the channel 6 activates the designated device, the channel 6 reports success of activation to the channel path control unit 5, and the channel path control unit 5 reports an input / output interrupt 103 to the instruction processor 1 a via the interface control device 2. I do. The instruction processor 1 that has received the input / output interrupt 103
“a” starts polling 104 for the storage area 11a until the information of the end notification is stored in the storage area 11a corresponding to the instruction processor 1a. The activated device and channel start executing the process 105 of the synchronous type input / output instruction.

On the other hand, when the input / output interrupt 103 is reported from the channel path control unit 5 of the input / output processor 4,
The interface controller 2 between the instruction processor 1a and the input / output processor 4 and the channel path controller 5 are opened,
Input / output activation of a synchronous type input / output instruction from another instruction processor can be executed. For example, if the instruction processor 1b can acquire the storage area 8 in the same manner as described above, the instruction processor 1b
Then, the startup information (command information and device information) is written into the storage area 10 (overwriting the previous information), and the number of the instruction processor 1b is written into the storage area 10. Then, as described above, the selection signal of the input / output processor 4 and the input / output activation are output to the interface control device 2.

Therefore, while the activated device is executing the processing of the input / output instruction, the input / output activation of the synchronous type input / output instruction from another instruction processor is executed one after another.

When the processing in the device is completed, the channel 6 is stored in the storage area 11a corresponding to the instruction processor 1a on the basis of the identification information of the instruction processor corresponding to the device stored in the storage area 12. The notification information and the execution result information 106 are stored. The instruction processor 1a that has polled the storage area 11a reads the information of the end notification and the information of the execution result from the storage area 11a, and executes the end report 107 to the processor 9. Note that when access to the storage device conflicts between polling by the instruction processor and writing of activation information or the like by another instruction processor, the polling has priority.

Hereinafter, similarly, synchronous type input / output instructions issued from other instruction processors are multiplexed and executed in parallel. As a result, in the data processing system of the present invention,
It is possible to obtain almost the same processing power as n instruction processors executing one synchronous type input / output instruction at the same time.

[0029]

As described above, according to the present invention, synchronous type input / output instructions can be processed in a multiplex manner up to the number of instruction processors. Thus, it is not necessary to provide dedicated hardware, and processing can be efficiently performed at high speed with a small amount of hardware. In addition, the effect of one synchronous type input / output instruction becomes more remarkable as the processing execution time of the device is longer.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data processing system of the present invention.

FIG. 2 is a diagram illustrating the flow of processing of a synchronous type input / output instruction according to the present invention.

FIG. 3 shows a storage area assigned to each instruction processor.

FIG. 4 is a diagram showing a conventional data processing system.

FIG. 5 is a diagram illustrating a flow of processing of a conventional synchronous type input / output instruction.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 instruction processor 2 interface control device 3 selector 4 input / output processor 5 channel path control unit 6 channel 7 storage device 8 startup information storage region 9 program 10 instruction processor identification information storage region 11 storage region corresponding to instruction processor 12 instruction processor Area for storing device identification information and device information

Claims (2)

(57) [Claims] A plurality of instruction processors for executing a synchronous type input / output instruction (hereinafter, referred to as an input / output instruction) to the input / output processor and executing an end processing of the instruction; Channel path control means for returning a response to the instruction processor, selecting and activating a channel based on the activation information, and a plurality of channels for activating a device based on the activation information and executing the processing of the input / output instruction A plurality of input / output processors comprising: an instruction processor; an interface control means for connecting the input / output processor selected by the instruction processor; and the activation information stored therein; And a storage means accessed by the input / output processor of the plurality of instruction processors. A method of processing output instructions in a multiplex manner, wherein a first instruction processor which has written in the storage means the start information and the information for identifying the instruction processor is selected from the plurality of instruction processors. An input / output activation of the channel path control means in the input / output processor selected by the instruction processor is instructed. In response to the input / output activation, a response is returned to the first instruction processor, and a channel is set based on the activation information. And the device is activated, and in response to the activation of the device, an input / output interrupt is notified from the channel path control means to the first instruction processor. When the input / output interrupt is notified, the interface control means and the channel A multiprocessing method for synchronous type input / output instructions, wherein the path control means is opened to another instruction processor. 2. When the channel is activated, the identification information is read from the storage means and stored in the channel.
In response to the end of the processing in the device, information including an end notification is stored in an area in the storage unit designated by the identification information in the channel, and the first input / output interrupt is notified. 2. The synchronous type input / output instruction according to claim 1, wherein the instruction processor polls the area until the information including the end notification is stored in the area allocated to the instruction processor. Multiple processing method.