JPH09331064A - Quantum effect element and its manufacturing method, semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire the low power consumption element in the minimum exclusive element area by a method in which the element is provided with a quantum fine wire having an insular part made of silicon to be held by a pair of tunnel barrier parts as well as a gate electrode provided through the intermediary of a gate insulating film formed on the insular part. SOLUTION: A pair of tunnel barrier parts 12 are formed on a silicon made quantum fine wire 11 at a mutual interval in the extending direction of the quantum fine wire 11. Furthermore, a gate insulating film 13 is formed on the insular part 11a of the quantum fine wire 11 held by the pair of tunnel barrier parts 12 so as to form a gate electrode 14 on the opposite surface to the quantum fine wire 11 of the gate insulating film 13. For example, the width and the film thickness of the quantum fine wire 11 is specified to be about 10nm while the tunnel barrier parts 12 are formed by locally oxidizing the quantum fine wire 11 by 2nm-5nm in the film thickness direction. Furthermore, a potential controlling gate electrode 14 is provided on one side part of the silicon insular part 11a through the intermediary of the gate insulating film 13 made of a silicon oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, a quantum effect element and a method of manufacturing the same, and a binary decision graph circuit is formed by a single electron transistor using a semiconductor thin wire, and the circuit is simplified. Semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, LS for personal portable devices
There is a strong demand for low power consumption of I. Since lower power consumption of LSI brings lower power consumption of the entire mobile device,
This is because it is possible to extend the operation time in battery driving, and for this reason, reduction in power consumption of semiconductor elements has been steadily promoted.

CM, which has become the mainstream of semiconductor devices in recent years,
In an OS type semiconductor element, the power consumption P is P = f
・ Represented by C · V ² . Here, f is the operating frequency of the circuit, C is the equivalent capacitance of the entire circuit, and V is the operating power supply voltage. Therefore, when the operating frequencies f are the same and compared, in order to reduce the power consumption P, it is necessary to reduce the equivalent capacitance C of the entire circuit and reduce the operating power supply voltage V. Reducing the capacity and operating voltage corresponds to reducing the number of moving carriers.

Therefore, in order to reduce the power consumption of the semiconductor element, it is necessary to reduce the number of carriers transmitting signals. The single electronic element is its ultimate form,
Transmission of signal by one electron (Nakazato et al., IEDM
Tech. Digest, p487 (1992)). This single-electron device is attracting attention as the most promising candidate for post-Si-VLSI. With the recent progress in microfabrication technology, it has become possible to form microstructures of the same order as the wavelength of electrons, and bit information is represented by an element using several electrons. Attempts have been made to build single electronic devices with extensions.

A conventional four-terminal single electronic device will be described below with reference to the drawings.

FIG. 9A is a schematic circuit diagram showing a four-terminal single electronic device used in a conventional pseudo CMOS single electronic circuit (Tucker JR: J. Appl. Phys. 72, 4399 (1992)).
As shown in FIG. 9A, the conventional four-terminal single-electron element has a first tunnel junction 103 in which one electrode is connected to the common connection portion 101 and the other electrode is connected to the drain terminal 102. , A second tunnel junction 105 in which one electrode is connected to the common connection portion 101 and the other electrode is connected to the source terminal 104, and one electrode is connected to the common connection portion 101.
And a second capacitor 109 having one electrode connected to the common connection portion 101 and the other electrode connected to the power supply terminal 108. It consists of and.

The operation of the four-terminal single-electron element is performed, for example, by setting the power supply terminal 108 to the power supply voltage VDD and
If 6 is operated as a gate electrode, it becomes an n-type element,
If the power supply terminal 108 is grounded and the gate terminal 106 is operated as a gate electrode, a p-type element is obtained. Therefore, a circuit equivalent to a CMOS circuit can be constructed by combining these n-type and p-type 4-terminal single electronic elements one by one. FIG. 9B is a simulation result of the operation of the conventional four-terminal single electronic element, which is Vd− of the MOSFET.
It is predicted that a characteristic similar to the Id characteristic will be obtained.

[0008]

However, the above-mentioned conventional single-electron element transmits a signal by one electron and is considered to be one of the ultimate devices from the viewpoint of low power consumption. There are two problems as listed below.

The first problem lies in processing technology. Regarding the processing technique, when it is attempted to realize the device of FIG. 9A using silicon, which is excellent in mass productivity and material stability, as shown in FIG. It is necessary to set the capacity to an extremely small value of several aF (at farad: 10 ^-18 F), and nano-scale fine processing technology is indispensable. The conventional method for manufacturing a quantum effect device using electron beam lithography has a problem that drawing with a width of about 10 nm is the limit, and it is difficult to form a device with a size of several nm or less where a remarkable quantum effect can be expected. There is. Further, when an electron beam is used, the surface of the silicon substrate is damaged, which causes a problem of deteriorating the device characteristics.

The second problem lies in circuit technology. Regarding the circuit technology, the single electronic device has a different operation mechanism from the CMOS technology, which is the mainstream of the conventional VLSI, and the input voltage and the output voltage are extremely small in principle, so that it differs from the conventional circuit technology. It is necessary to apply the technology of logic circuits. On the other hand, a proposal has been made to construct a BDD circuit using a single electron transistor (Yoshihito Amemiya et al., Applied Physics, 64, No.8, 765-768 (1995)).

An object of the present invention is to solve the conventional problems described above and to realize a quantum effect device having an extremely small device-occupying area and low power consumption.

[0012]

To achieve the above object, the present invention is compatible with existing silicon semiconductor technology,
The structure uses a field-assisted oxidation process using a scanning probe microscope and a damage-free process to which crystal anisotropic etching is applied. The single electronic device is
Since the input voltage and the output voltage are very small in principle, it is necessary to combine them with other devices capable of handling a large voltage amplitude, and using the manufacturing method according to the present invention, it is easy to obtain Si-CMOS devices which are currently the mainstream. And can be reliably connected.

[0013] Specifically, in the solving means devised by the invention of claim 1, the quantum effect element is formed by a quantum wire made of silicon and formed on the quantum wire at intervals in a direction in which the quantum wire extends. A pair of tunnel barrier portions, a gate insulating film formed on an island portion of the quantum wire sandwiched by the pair of tunnel barrier portions, and a surface of the gate insulating film opposite to the quantum wire. A gate electrode is provided.

According to the structure of claim 1, a quantum wire made of silicon and having an island portion sandwiched between a pair of tunnel barrier portions, and a gate electrode provided via a gate insulating film formed on the island portion. Therefore, if one end of the quantum wire is used as the source electrode and the other end is used as the drain electrode, a single electronic element used in a pseudo CMOS single electronic circuit can be reliably realized. Furthermore, if another gate electrode is provided on the side of the island opposite to the gate electrode via an insulating film, a four-terminal single-electron device can be easily realized.

According to a second aspect of the present invention, the quantum effect device is manufactured by a method of manufacturing a quantum effect device, in which the main surface of the upper silicon layer of the SOI substrate is entirely etched to form a thin film of the upper silicon layer. A step of forming a silicon layer, and bringing a conductive probe needle close to the main surface of the thin film silicon layer, and scanning the conductive probe needle parallel to one side of the SOI substrate and along the main surface. Forming a first linear pattern of an electric field assisted oxide film on the surface of the thin film silicon layer by performing electric field assisted oxidation with the conductive thin film silicon layer, and bringing a conductive probe needle close to a predetermined region of the first linear pattern. At the same time, the conductive probe needle is scanned perpendicularly to the first linear pattern and along the main surface to perform electric field-assisted oxidation, whereby the thin film shield is formed. The surface of the con layer made of a field-assisted oxide film, first with crossed portion between the first linear pattern 2
Forming a straight line pattern, and anisotropically etching the thin film silicon layer using the first straight line pattern and the second straight line pattern as a mask, thereby forming a first cross-section made of silicon. Forming a quantum wire and a second quantum wire, and after removing the first straight line pattern and the second straight line pattern,
Field-assisted oxidation film is formed on the first region and the second region by sequentially approaching the conductive probe needles to the first region and the second region sandwiching the intersecting portion of the quantum wire and performing the field-assisted oxidation. By forming electric field assisted oxidation by sequentially making conductive probe needles approach the third region and the fourth region sandwiching the intersection in the second quantum wire, respectively. And a step of forming an insulating film made of an electric field assisting oxide film in the third region and the fourth region, respectively.

According to the structure of claim 2, after the upper silicon layer is thinned to form the thin film silicon layer, the conductive probe needle is brought close to the main surface of the thin film silicon layer and is scanned along the main surface. As a result, a first straight line pattern made of an electric field assisted oxide film and a second straight line pattern intersecting the first straight line pattern are formed, and then the first and second straight line patterns are used as masks to form a thin film silicon layer. Anisotropic etching is performed on the first and second quantum wires having intersecting portions that intersect each other,
Conductive probe needles are sequentially brought close to the first region and the second region sandwiching the intersection of the first quantum wires to form tunnel barriers made of an electric field assisting oxide film, respectively, and
The conductive probe needles are sequentially brought close to the third region and the fourth region sandwiching the intersection of the quantum wires to form the insulating film made of the electric field assisting oxide film, respectively. The end on the region side is the source electrode, the end on the second region side is the drain electrode, the end on the third region side of the second quantum wire is the first gate electrode, and the fourth region side. By using the end portion of the second gate electrode as the second gate electrode, it is possible to surely realize the 4-terminal single-electron element used in the pseudo CMOS single-electron circuit.

According to a third aspect of the present invention, there is provided a semiconductor device in which an island-shaped carrier transfer portion made of silicon formed on an SOI substrate and an end portion of the carrier transfer portion on the SOI substrate. A first quantum wire made of silicon formed via a first tunnel barrier, and a first quantum wire made of silicon formed on the SOI substrate and at the other end of the carrier transfer portion via a second tunnel barrier. 2 quantum wire, a third quantum wire made of silicon formed on the SOI substrate between the one end and the other end of the carrier transfer portion via a third tunnel barrier, and A first control electrode formed on the carrier transfer portion via an insulating film, a second control electrode formed on the second quantum wire via an insulating film, and an insulating film on the third quantum wire. Formed through It is an arrangement and a control electrode.

According to the structure of claim 3, the first quantum wire is used as an input terminal and the second quantum wire is used as a first output terminal.
The third quantum wire is used as the second output terminal, the first terminal is input to the input terminal and is formed in the carrier transfer portion via the insulating film.
Carriers transferred to the carrier transfer unit by applying a potential to the control electrode of the second control electrode formed on the second quantum thin wire via the insulating film or the third quantum wire of the insulating film. By applying a potential to the third control electrode formed through the, it is possible to surely realize the BDD circuit which outputs to the first output terminal or the second output terminal.

According to a fourth aspect of the present invention, in the structure of the third aspect, the first, second, and third tunnel barriers are formed of a quantum thin wire in which a part of the quantum thin wire has a smaller cross-sectional area than other portions. This is to add a configuration consisting of constriction.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor device, an island-shaped first carrier transfer portion formed of silicon, formed on an SOI substrate; A first quantum wire made of silicon is formed at one end of the transfer section through the first tunnel barrier, and a second tunnel barrier is provided on the SOI substrate and at the other end of the first carrier transfer section. And a second quantum thin line made of silicon formed on the SOI substrate and between the one end and the other end of the first carrier transfer unit via a third tunnel barrier. And an island-shaped second carrier transfer portion made of silicon and formed on the SOI substrate and on a side portion of the second carrier transfer portion on the side of the second quantum wire via a fourth tunnel barrier. No. 1 made of silicon And quantum wire, a first control electrode formed via an insulating film on the first carrier transfer portion,
A second control electrode formed on the second quantum wire and the third quantum wire via an insulating film; and a third control electrode formed on the second carrier transfer unit via an insulating film. Is provided.

According to the structure of claim 5, the first quantum wire is used as an input terminal and the second quantum wire is used as a first output terminal.
The third quantum thin wire is used as the second output terminal, the potential is applied to the first control electrode which is input to the input terminal and is formed in the first carrier transfer portion via the insulating film. The carrier transferred to the carrier transfer unit is transferred to the second quantum wire and the third quantum wire through the second insulating film formed via the insulating film.
A binary decision graph output to the first output terminal or the second output terminal by applying an electric potential to the control electrode of the second control electrode or the third control electrode formed on the second carrier transfer portion via the insulating film. The circuit can be reliably realized.

According to a sixth aspect of the present invention, in the structure of the fifth aspect, the first, second, third, and fourth tunnel barriers are formed such that a portion of the quantum wire has a smaller cross-sectional area than the other portions. In addition, a structure consisting of quantum wire constriction is added.

According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a main surface of an upper silicon layer of an SOI substrate is entirely etched to reduce the thickness of the upper silicon layer to form a thin film silicon. Forming a layer, bringing a conductive probe needle close to the main surface of the upper silicon layer, and scanning the conductive probe needle parallel to one side of the SOI substrate and along the main surface. Performing a field-assisted oxidation to form a first linear pattern of the field-assisted oxide film on the surface of the thin film silicon layer; and bringing a conductive probe needle close to a predetermined region of the first linear pattern. , The conductive probe needle is scanned perpendicularly to the first linear pattern and along the main surface to perform electric field-assisted oxidation, whereby the thin film silicon Forming a second straight line pattern, which is formed of an electric field assisted oxide film and is connected to the first straight line pattern by the first branch portion, on a surface of the conductive layer; and in a predetermined region of the second straight line pattern. The electric field assisted oxidation is performed by bringing the conductive probe needle close to the conductive probe needle and scanning the conductive probe needle perpendicularly to the second linear pattern and along the main surface to perform the electric field assisted oxidation. A step of forming a third straight line pattern made of an electric field assisting oxide film and connected to the second straight line pattern by the second branch portion; the first straight line pattern;
Anisotropic etching is performed on the thin film silicon layer using the linear pattern and the third linear pattern as a mask to form a first quantum wire and a first quantum wire made of silicon and connected to each other at the first branch portion. Forming a second quantum wire and a third quantum wire connected to the second quantum wire at a second branch; and the first quantum wire for the first branch in the first quantum wire. A step of forming a first tunnel barrier made of an electric field assisted oxide film in the first region by bringing a conductive probe needle close to the first region opposite to the quantum wire of No. 3 to perform electric field assisted oxidation. And a second region on the side of the third quantum wire with respect to the first branch of the first quantum wire by bringing the conductive probe needle close to perform electric field-assisted oxidation, thereby forming the second area. Forming a second tunnel barrier made of an electric field assisting oxide film, and bringing a conductive probe needle close to a third region of the second quantum wire on the side of the first branch with respect to the second branch. And performing field-assisted oxidation to form a third tunnel barrier made of an field-assisted oxide film in the third region, and a fourth branch on the second branch portion side of the third quantum wire. Forming a fourth tunnel barrier made of an electric field assisted oxide film in the fourth region by bringing a conductive probe needle close to the region to perform electric field assisted oxidation; and covering the entire surface of the SOI substrate with the fourth tunnel barrier. A step of depositing an interlayer insulating film; a step of forming a first control electrode on the interlayer insulating film and in a region above the first branch portion; On the first quantum wire Forming a second control electrode in a region above the third quantum wire side with respect to the second tunnel barrier and in a region above the third quantum wire, and on the interlayer insulating film, The second
And a step of forming a third control electrode in a region above the branch portion of the above.

According to the structure of claim 7, the end portion of the first quantum wire on the side of the first region is an input terminal, and the end portion of the first quantum wire on the side of the second region is a first output terminal. , The end of the third quantum wire is used as the second output terminal, the potential is applied to the input terminal, and the potential is applied to the first control electrode formed in the region above the first branch through the interlayer insulating film. The carriers transferred to the first branch portion by applying the third quantum wire and the region above the third quantum wire side with respect to the second tunnel barrier in the first quantum wire through the interlayer insulating film. To the second control electrode formed in the region above
Alternatively, by applying a potential to the third control electrode formed in the region above the second branch portion via the interlayer insulating film,
It is possible to reliably realize the BDD circuit which outputs to the first output terminal or the second output terminal.

According to an eighth aspect of the present invention, in the structure of the seventh aspect, the first, second, third and fourth tunnel barriers are formed by completely oxidizing the cross section of the quantum wire. The configuration is added.

According to a ninth aspect of the present invention, in the structure according to the seventh aspect, the first, second, third and fourth tunnel barriers are formed by oxidizing a part of a cross section of the quantum wire. The configuration is added.

According to a tenth aspect of the invention, in addition to the constitution of the eighth or ninth aspect, a constitution in which the film thickness of the thin film silicon layer in the SOI substrate is 50 nm or less is added.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a schematic perspective view showing a quantum effect element according to the first embodiment of the present invention. As shown in FIG. 1A, a quantum island 11 made of silicon is provided with a silicon island portion 11a sandwiched between a pair of tunnel barrier portions 12 made of a silicon oxide film. A gate electrode 14 for potential control is provided on one side of the silicon island 11a via a gate insulating film 13 made of a silicon oxide film, and an insulation made of a silicon oxide film is provided on the other side of the silicon island 11a. A control electrode 16 for controlling the potential is provided via the film 15.

The width and the film thickness of the quantum wire 11 are preferably about 10 nm so that the capacitance value of the tunnel barrier portion 12 is sufficiently small. The tunnel barrier portion 12 is formed by locally oxidizing the quantum wires 11 in the film thickness direction by 2 nm to 5 nm. The gate insulating film 13 and the insulating film 15 are both made of a silicon oxide film and have a width of 200 nm or less, preferably several tens of nm. The silicon island portion 11a has a width of 10 nm and a length of 200 nm or less, preferably several tens of nm. The gate electrode 14 and the control electrode 16 are single crystal silicon to which n-type impurities are added at a high concentration, but are not limited to this and may be metal or polycrystalline silicon.

In the quantum effect element according to this embodiment, each terminal corresponds to the terminal of the four-terminal single electronic element of the pseudo CMOS single electronic circuit shown in FIG. 9A. That is, one end 11b of the quantum wire 11 is connected to the source terminal 104,
The other end 11 c of the quantum wire 11 corresponds to the drain terminal 102, the gate electrode 14 corresponds to the gate terminal 106, and the control electrode 16 corresponds to the power supply terminal 108. Therefore, when the power supply potential VDD is applied to the control electrode 16, it functions as an n-channel transistor, and when the ground potential is applied to the control electrode 16, it functions as a p-channel transistor.

FIG. 1B is a sectional view in the source / drain direction shown in FIG. In the silicon island portion 11a, a pair of silicon oxide films 17 forming the tunnel barrier portion 12 are formed at intervals in the direction in which the quantum wires 11 extend. Here, each silicon oxide film 17 is a quantum wire 1.
It is formed from the surface of 1 to almost the center thereof, and does not reach the bottom of the quantum wire 11. This structure is called a quantum wire constriction (= constriction) structure. As a result, when the tunnel current flows, the driving force does not decrease and the carrier velocity also increases.

FIG. 1 (c) is a diagram showing the energy levels of the cross section in the source / drain direction shown in FIG. 1 (a). As shown in FIG. 1C, the energy band gap Eg2 of the tunnel barrier portion 12 becomes larger than the energy band gap Eg1 of the quantum wire 11 because of the quantum wire constriction structure formed by the silicon oxide film 17. You can see that Here, C.I. B. Is the conduction band,
V. B. Each represents a valence band.

As described above, according to the quantum effect element of this embodiment, bit information can be described by a few electrons and a pseudo CMOS structure can be formed, so that a power element with extremely low power consumption can be realized.

Further, in principle, the present quantum effect device can be made highly integrated because the device area of one side is several tens of nm even if the silicon island portion 11a is included.

The gate insulating film 13 and the gate electrode 1
4 and the insulating film 15 and the control electrode 16 are names for convenience, and since the corresponding members are the same, it is possible to treat the gate insulating film 13 side as the power supply terminal 108 and the control electrode 16 side as the gate terminal 106. Is clear.

The method of manufacturing the quantum effect device according to the first embodiment of the present invention will be described below with reference to the drawings.

2 (a) to 2 (c) and FIG. 3 are a perspective view and a sectional view in order of the steps, showing the method for manufacturing the quantum effect element according to the first embodiment of the present invention. First, as shown in FIG. 2A, a silicon substrate 21 having a plane orientation of (001), a buried oxide film 22 formed on the silicon substrate 21 and having a thickness of 100 nm, and the buried oxide film 22 are formed. The SOI substrate 20, which is formed on the upper silicon layer (not shown) having a thickness of 140 nm and is oxidized in an oxygen atmosphere at a temperature of 1000 ° C. for about 120 minutes, is oxidized on the upper silicon layer. By removing the formed oxide film in a hydrogen fluoride (HF) aqueous solution, the upper silicon layer is thinned,
A thin film silicon layer 23 having a film thickness of 10 nm is formed. Conductive probe needle whose surface is coated with gold (Au) etc. (Fig. 1
Reference numeral 18 in (b) shows only the tip portion. ), For example, using a scanning probe microscope such as an atomic force microscope (AFM) or a scanning tunneling microscope (STM), the conductive probe needle is applied to a predetermined region of the thinned thin film silicon layer 23. After they are brought close to each other, while applying a bias voltage of −10 V to the conductive probe needle, the electric field assisted oxidation is performed by scanning in a direction perpendicular to or parallel to the <110> crystal axis direction, thereby performing silicon oxidation as an electric field assisted oxide film. A first linear pattern 24A and a second linear pattern 24B made of a film and orthogonal to each other are formed at the intersection 24C.

Then, as shown in FIG. 2B, a mixed solution of 1000 ml of ethylenediamine, 144 g of pyrocatechol and 290 ml of pure water was used as an etching solution, and the etching solution was kept at a temperature of 80 ° C. The SOI crystal 20 is subjected to silicon crystal anisotropic etching for 1 minute. Silicon crystal anisotropic etching is (11
The etching rate of the 1) plane is about 8 nm / min, while the (100) and (110) directions are about 100 nm.
Has an etching rate of / min. As shown in FIG. 2C, which is a cross-sectional view taken along the line I-I in FIG. 2B, due to this characteristic and the etching resistance of the first and second linear patterns 24A and 24B made of a silicon oxide film. After the wet etching, on the buried oxide film 22,
A silicon microstructure including a first quantum wire 23a and a second quantum wire 23b made of silicon, having a (111) plane as a side surface and having intersections 23c with each other, is formed. Then, the first linear pattern 24A and the second linear pattern 24B are removed with hydrofluoric acid or the like.

Next, as shown in FIG. 3, by using a scanning probe microscope, the first oxide film on the buried oxide film 22 is removed.
The region including the quantum thin line 23a and the second quantum thin line 23b is subjected to step measurement to obtain alignment data for drawing in a subsequent process. After that, in the first region and the second region sandwiching the intersection portion 23c in the first quantum wire 23a, (-10)
Conductive probe needles to which a bias voltage of V is applied are sequentially brought close to each other to perform electric field assisted oxidation, thereby forming tunnel barriers 25a and 25a made of an electric field assisted oxide film in the first region and the second region, respectively. . The difference in the film thickness of silicon, which is a conductor, caused by the electric field assisted oxidation is reflected in the difference in the band gap, thereby forming a potential barrier. As a result, since the intersection 23c of the first quantum wire 23a is sandwiched between the two tunnel barriers 25a, a source terminal is formed at one end of the first quantum wire 23a and a drain terminal is formed at the other end thereof. .
Each tunnel barrier 25a can change the film thickness and the like of the electric field assisting oxide film by changing the bias voltage value and the like of the conductive probe needle of the microscope. Therefore, the capacitance value and the tunnel resistance can be changed according to the film thickness. The value can be changed.

Next, in the third and fourth regions sandwiching the intersection 23c in the second quantum wire 23b, (-3
0) Conductive probe needles to which a bias voltage of V is applied are sequentially approached to perform electric field assisted oxidation, and an insulating film 25b made of an electric field assisted oxide film is formed in the third region and the fourth region.
By forming 25b respectively, an intersection 23c as a silicon island portion surrounded by a pair of tunnel barriers 25a, 25a and a pair of insulating films 25b, 25b is formed. As a result, the second quantum wire 23b is insulated and separated by the two insulating films 25b and 25b, so that the gate electrode for potential control is formed at one end and the control electrode for potential control is formed at the other end. become.

As described above, according to the manufacturing method of this embodiment, since the scanning probe microscope is used for pattern drawing, fine processing at a level of several nm can be easily performed.

Further, by appropriately selecting the bias condition of the conductive probe needle in the electric field assisted oxidation process,
It is possible to optimize the capacitance value and the resistance value of the tunnel barrier, which are largely related to the device characteristics and the operating temperature, and the pair of tunnel barriers 25 sandwiching the intersection portion 23c forming the silicon island portion.
It is also possible to form a and 25a asymmetrically. By forming the pair of tunnel barriers 25a, 25a asymmetrically, the capacitance of the tunnel barrier on the output side is made smaller than the capacitance of the tunnel barrier on the input side in accordance with a desired circuit. The advantage is that you can increase the speed.

Further, since the electric field assisted oxidation process modifies only the silicon atom surface and the crystal anisotropic etching process is also a wet process, it is free from process damage, so that the interface level which causes malfunction of a single electron element is not affected. It is possible to suppress the offset charge such as the position to an extremely low level.

Since the crystal anisotropic etching is used, the side surface of the quantum wire is flat at the atomic level.
The width uniformity in the longitudinal direction and the linearity are extremely excellent. Therefore, since the electron mobility can be expected to be improved by the quantum mechanical effect, high-speed operation is possible.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4A is a partial plan view showing a semiconductor device according to the second embodiment of the present invention. In FIG. 4A, a carrier transfer section 30 made of silicon is provided on an SOI substrate, and a first transfer layer 30 made of silicon electrically connected to one end of the carrier transfer section 30 via a first tunnel barrier 41. 1 quantum wire 31, a second quantum wire 32 made of silicon electrically connected to the other end of the carrier transfer unit 30 via a second tunnel barrier 42, and the one end of the carrier transfer unit 30. A third quantum wire 33 made of silicon and electrically connected via a third tunnel barrier 43 is formed between the third quantum wire 33 and the other end.

Further, a first control electrode is formed on the carrier transfer portion 30 via an insulating film (not shown).
Gate electrode 51 and a second gate electrode 52 formed on the second quantum wire 32 via an insulating film (not shown).
And a third gate electrode 53 formed on the third quantum wire 33 via an insulating film (not shown).

The carrier transfer section 30 and the first to third quantum wires 31 to 33 may each have a width of 100 nm or less and have conductivity. First to third tunnel barriers 41
˜43 operates as an energy barrier, and the material is not limited as long as a tunnel current flows. The first to third gate electrodes 51 to 53 may be made of any material as long as they can transfer a potential.

The first quantum wire 31 is used as a signal input section, and its input voltage is A. The second quantum wire 32 is used as the first output detector, and its output voltage is Y0. The third quantum wire 33 is used as the second output detector, and its output voltage is Y1.
And The third gate electrode 53 is used as a signal control electrode,
The control potential is X0. The first gate electrode 51 and the second gate electrode 52 are used as clock control electrodes, and their control potentials are φ1 and φ2, respectively.

FIG. 4B is a partial plan view showing a semiconductor device according to a first modification of the second embodiment of the present invention. In FIG. 4B, a first carrier transfer section 30A made of silicon is electrically connected to an SOI substrate, and one end of the first carrier transfer section 30A is electrically connected via a first tunnel barrier 41. First quantum wire 3 made of doped silicon
1, the second quantum wire 32 made of silicon electrically connected to the other end of the first carrier transfer section 30A through the second tunnel barrier 42, and the first carrier transfer section 3
In the second carrier transfer portion 33A made of silicon electrically connected between the one end portion and the other end portion of 0A through the third tunnel barrier 43, and in the second carrier transfer portion 33A. A third quantum wire 34 made of silicon and electrically connected via a fourth tunnel barrier 44 is formed on the side of the second quantum wire 32 side.

Further, the first gate electrode 51 formed on the first carrier transfer portion 30A via an insulating film (not shown), the second quantum wire 32 and the third quantum wire 3 are formed.
Second gate electrode 52 formed on the fourth carrier via an insulating film (not shown), and a third gate electrode formed on the second carrier transfer portion 33A via an insulating film (not shown). Gate electrode 53 is formed.

First and second carrier transfer units 30A, 3
Each of 3A and the first to third quantum wires 31, 32, and 34 may have a width of 0.1 μm or less and have conductivity. The first to fourth tunnel barriers 41 to 44 operate as energetic barriers, and any material may be used as long as a tunnel current flows. In addition, the first to third gate electrodes 51 to 5
3 may be made of any material as long as it can transmit a potential.

The first quantum wire 31 is used as a signal input section, and its input voltage is A. The second quantum wire 32 is used as the first output detector Y0, and the third quantum wire 34 is used as the second output detector Y1. The third gate electrode 53 is used as a signal control electrode, and its control potential is X0. The first gate electrode 51 and the second gate electrode 52 are used as clock control electrodes, and their control potentials are φ1 and φ2, respectively.

FIG. 5 is an equivalent circuit diagram of a semiconductor device according to a first modification of the second embodiment of the present invention. The first carrier transfer unit 30A is surrounded by the first tunnel barrier 41, the second tunnel barrier 42, and the third tunnel barrier 43, and the second carrier transfer unit 33A is surrounded by the third tunnel barrier 43 and the third tunnel barrier 43. Since the electrons are stored in the first carrier transfer unit 30A or the second carrier transfer unit 33A because they are surrounded by the tunnel barrier 44 of No. 4, other electrons cannot be stored due to Coulomb interaction between the electrons. Also,
When an appropriate low potential is applied to the first gate electrode 51 or the third gate electrode 53, the first carrier transfer unit 3
Electrons do not flow out of 0A or the second carrier transfer unit 33A. When an appropriately high potential is applied to the first gate electrode 51 when electrons exist in the first quantum wire 31, the electrons in the first quantum wire 31 move to the first carrier transfer unit 30A. . At this time, when a higher potential is applied to the third gate electrode 53, the electrons that have moved to the first carrier transfer unit 30A further move to the second carrier transfer unit 33A.

FIG. 6 is a timing chart showing each control voltage in the semiconductor device according to the first modification of the second embodiment of the present invention. At the timings shown in FIG. 6, control potentials φ1 and φ corresponding to the first to third gate electrodes 51 to 53 are generated.
When 2 and X0 are applied, electric charges are exclusively output to the output voltage Y0 of the first output detector and the output voltage Y1 of the second output detector.

Thus, the circuit according to the present embodiment can transfer the charge of the input voltage A to the second output detector as the output voltage Y1 if the control potential X0 is H (high). If the control potential X0 is L (low), it can be transferred as the output voltage Y0 to the first output detector, so that a BDD circuit is constructed.

Therefore, according to the present embodiment, the BDD circuit can be easily and reliably formed by the single-electron transistor using the quantum wire.

Although silicon is used as the material forming the quantum wires, any material having conductivity may be used. It suffices that the tunnel barrier operates as an energy barrier and allows a tunnel current to flow. For example, a thin silicon oxide film or a quantum wire constriction structure by peripheral oxidation of the quantum wire may be used. As the material of the gate electrode, aluminum or the like is usually considered in order to achieve compatibility with the silicon multilayer wiring process, but any material capable of transmitting a potential may be used.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 is a partial plan view showing a semiconductor device according to the third embodiment of the present invention. 8A to 8F show a method of manufacturing a semiconductor device according to a third embodiment of the present invention, which is a sectional view taken along the line III-III in FIG.
First, as shown in FIG. 8A, a silicon substrate 61 and a buried oxide film 62 having a thickness of 80 nm formed on the silicon substrate 61 are formed by using, for example, the SIMOX method.
180 nm thick formed on the buried oxide film 62
The upper silicon layer 63 whose main surface has a plane orientation of <100>
An SOI substrate 60 composed of A and A is formed.

Next, as shown in FIG. 8B, the SOI substrate 60 is heated to about 120 ° C. in an oxygen atmosphere at a temperature of about 120 ° C.
The upper silicon layer 63A is thinned by oxidizing for 5 minutes and then removing the oxide film formed by oxidation on the upper silicon layer 63A in a hydrogen fluoride (HF) aqueous solution to form a thin silicon layer having a thickness of 50 nm. 63B is formed.

Next, as shown in FIG. 8C, for example, an atomic force microscope (AFM) or a scanning tunneling microscope (STM) having a conductive probe needle 90 whose surface is coated with gold (Au) or the like is used. ) Is used to bring the conductive probe needle 90 close to a predetermined region forming the first linear pattern on the main surface of the thinned thin film silicon layer 63B. After that, the conductive probe needle 90 is set to the ground potential, and while the bias voltage of +9 V is applied to the thin film silicon layer 63B, the conductive probe needle 90 is moved along the main surface of the thin film silicon layer 63B at a speed of about 0.25 μm per second. And linearly move it to perform electric field assisted oxidation by the electric field applied to the thin film silicon layer 63B, so that the line width is about 100 nm and the film thickness is 5 nm on the surface of the thin film silicon layer 63B.
Forming a silicon oxide film 65A as a first linear pattern, which is an electric field assisting oxide film. Then, a second straight line extending perpendicularly to the first straight line pattern in the main surface from the first branching portion (reference numeral 81 shown in FIG. 7) as the first carrier transfer portion in the first straight line pattern. The pattern is also formed using the electric field assisted oxidation method, and the second branch portion (reference numeral 82 shown in FIG. 7) as the second carrier transfer portion in the second linear pattern is used to form the second Oxide film 65C as a third linear pattern extending perpendicular to the linear pattern and extending parallel to the first linear pattern.
Are similarly formed.

Next, as shown in FIG. 8D, a mixed solution of 300 ml of ethylenediamine, 48 g of pyrocatechol and 98 ml of pure water was used as an etching solution, and the etching solution was kept at a temperature of 80 ° C. The SOI substrate 60 is anisotropically etched for 30 seconds. This etching solution etches silicon, but the etching rate is different depending on the plane orientation.
The> direction is very slow compared to other plane orientations. Therefore, since only the lower parts of the silicon oxide films 65A, 65C, etc. remain in the thin film silicon layer 63B after being immersed in this etching solution for 30 seconds, the first quantum wires 63a and the second quantum wires (see FIG. 7). Reference numeral 63b) and the third quantum wire 63c are formed, respectively. Each quantum wire 63a, 63b, 63
The side faces of c are <111> faces, respectively. Here, the upper surfaces of the quantum wires 63a, 63b, 63c are not etched because they are protected by the silicon oxide film 65A and the like.

Next, as shown in FIG. 8E, the conductive probe needle 90 is provided in the first region on the opposite side of the third quantum wire 63c to the first branch 81 in the first quantum wire 63a. And the conductive probe needle 90 is applied to the ground potential and +15 V is applied to the first quantum wire 63a.
Of the conductive probe needle 90 while applying the bias voltage of
About 0.25 per second perpendicular to the first quantum wire 63a.
It is moved along the surface of the first quantum wire 63a at a speed of μm. As a result, a barrier oxide film (reference numeral 66A shown in FIG. 7) as a first tunnel barrier having a line width and a film thickness of about 10 nm is formed in the first region by using the electric field assisted oxidation by the applied electric field. . Similarly, the first quantum wire 63a
The third quantum wire 63 for the first branch 81 in
By conducting the electric field assisted oxidation by bringing the conductive probe needle 90 close to the second region on the c side, a barrier oxide film 66B as a second tunnel barrier made of the electric field assisted oxide film is formed in the second region. To do. Subsequently, similarly, the conductive probe needle 90 is brought close to the third region on the first branch 81 side with respect to the second branch 82 in the second quantum wire 63b to perform electric field assisted oxidation, A barrier oxide film (reference numeral 66C shown in FIG. 7) as a third tunnel barrier made of an electric field assisted oxide film is formed in the third region, and
By conducting the electric field assisted oxidation by bringing the conductive probe needle 90 close to the fourth region of the third quantum wire 63c on the second branch portion 82 side, the fourth region formed of the electric field assisted oxide film is formed. A barrier oxide film (reference numeral 66D shown in FIG. 7) as a tunnel barrier of No. 4 is formed.

Next, as shown in FIG. 8 (f), for example,
After depositing a 100-nm-thick silicon oxide film 67 as an interlayer insulating film over the entire surface of the SOI substrate 60 by using the atmospheric pressure CVD method, the entire surface of the silicon oxide film 67 is formed by using the sputtering method. An aluminum thin film with a thickness of 500 nm is deposited. After that, the aluminum thin film is selectively etched by using photolithography, and the first gate electrode (reference numeral 68A shown in FIG. 7) and the first quantum wire are provided above the first branch portion 81. The third quantum wire 6 of the barrier oxide film 66B in 63a.
A second gate electrode (reference numeral 68B shown in FIG. 7) is formed above the 3c side and above the third quantum wire 63c, and a third gate electrode 68C is formed above the second branch portion 82.

As described above, according to this embodiment, the single electron transistor using the quantum wire having the same structure as the semiconductor device realizing the BDD circuit shown in the first modification of the second embodiment is used. The configured semiconductor device can be reliably manufactured.

Further, since the scanning probe microscope is used for pattern drawing, fine processing at a level of several nm can be easily performed, and by appropriately selecting the bias condition of the conductive probe needle in the electric field assisted oxidation process, It is possible to optimize the capacitance value and the resistance value of the tunnel barrier, which are largely related to the device characteristics and the operating temperature.

Further, since the electric field assisted oxidation process modifies only the silicon atom surface and the crystal anisotropic etching process is also a wet process, it is process damage-free, so that the interface level which causes malfunction of the single-electron element is not affected. It is possible to suppress the offset charge such as the position to an extremely low level.

Further, since the crystal anisotropic etching is used, the side surface of the quantum wire is flat at the atomic level.
The width uniformity in the longitudinal direction and the linearity are extremely excellent. Therefore, since the electron mobility can be expected to be improved by the quantum mechanical effect, high-speed operation is possible.

Although silicon is used as the material for the quantum wires, any material may be used as long as it has conductivity.

Although the barrier oxide film does not completely oxidize each quantum wire, that is, the barrier is formed by a so-called quantum wire constriction structure due to oxidation of the peripheral portion of the quantum wire, the line width of each quantum wire is further miniaturized. If possible, each quantum wire may be completely oxidized. In this way, the leakage current of the device can be suppressed and the cooling temperature of the device can be made relatively high. Each barrier oxide film may be made of any material as long as it operates as an energy barrier and allows a tunnel current to flow. For example,
It is preferable to use a thin silicon oxide film or a quantum wire constriction structure by peripheral oxidation of the quantum wires.

Although aluminum was used as the material of the gate electrode in order to achieve compatibility with the silicon multilayer wiring process, it goes without saying that any material may be used as long as it can transfer a potential.

In general, gold-coated silicon is used as the material of the conductive probe needle.
In addition to this, tungsten, impurity-diffused silicon, or the like may be used.

Although a mixed aqueous solution of ethylenediamine and procatechol was used for anisotropic etching, the etching rate differs depending on the plane orientation, and the etching rate of a specific plane orientation is much higher than the etching rates of other plane orientations. At a later time, another solution such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) may be used. In this case, needless to say, it is necessary to change the plane orientation of the main surface depending on the anisotropy of the solution.

[0076]

According to the quantum effect element of the first aspect of the present invention, a quantum wire having an island portion made of silicon and sandwiched by a pair of tunnel barrier portions, and a gate insulating film formed on the island portion. Since the quantum wire has one end as a source electrode and the other end as a drain electrode, a pseudo CMOS single electronic circuit in which bit information can be described by a few electrons is provided. The single electronic element to be used can be surely realized. Furthermore, if another gate electrode is connected to the side portion of the island portion opposite to the gate electrode via an insulating film, a four-terminal single electronic device can be easily and surely realized. As a result, an element with extremely low power consumption can be realized, and in principle, even if the island portion is included, the element area of one side is several tens of nm, so that ultra-high integration can be achieved.

According to the method of manufacturing a quantum effect element of the second aspect, the end of the first quantum wire on the side of the first region is used as the source electrode and the end on the side of the second region is used as the drain electrode. , A third terminal side of the second quantum wire as a first gate electrode and an end portion of the fourth area side as a second gate electrode are used for a pseudo CMOS single electronic circuit. One electronic element can be surely realized.

According to the semiconductor device of the third or fifth aspect of the invention, the first quantum wire is the input terminal, the second quantum wire is the first output terminal, and the third quantum wire is the second output. The carriers that are input to the input terminal and are transferred to the carrier transfer unit by applying a potential to the first control electrode formed on the carrier transfer unit via the insulating film,
By applying a potential to the second control electrode or the third control electrode, a BDD circuit for outputting to the first output terminal or the second output terminal can be easily and reliably realized.

According to the semiconductor device of the fourth or sixth aspect of the present invention, in each of the first to fourth tunnel barriers, a quantum thin wire constellation is formed in which a part of the quantum thin wire has a smaller cross-sectional area than the other portion. Since it has a junction structure, a tunnel barrier can be reliably formed for carriers and the carrier velocity can be increased.

According to the method of manufacturing a semiconductor device of the seventh aspect, the end of the first quantum wire on the side of the first tunnel barrier is used as an input terminal, and the first quantum wire on the side of the second tunnel barrier is formed. Of the third quantum wire as the second output terminal, and the first control terminal formed in the region above the first branch portion is input to the input terminal. Carriers transferred to the first branch portion by applying a potential to the electrode are transferred to the region above the third quantum wire side with respect to the second tunnel barrier in the first quantum wire and the third quantum wire.
The first output terminal by applying a potential to the second control electrode formed in the region above the quantum wire or in the region above the second branch. Alternatively, the BDD circuit for outputting to the second output terminal can be realized easily and reliably.

According to the method of manufacturing a semiconductor device of the present invention, since the tunnel barrier in each quantum wire is formed by completely oxidizing the cross section of the quantum wire, the leakage current is suppressed and the device is reduced. The cooling temperature of can be set to a relatively high temperature.

According to the method of manufacturing a semiconductor device of the ninth aspect, the tunnel barrier in each quantum wire is formed by oxidizing a part of the cross section of the quantum wire, so that the tunnel barrier is easily formed. The carrier speed can be increased.

According to the method of manufacturing a semiconductor device of the tenth aspect of the present invention, the thin film silicon layer on the SOI substrate has a film thickness of 50 nm or less, so that the quantum wires can be formed reliably.

Further, when the film thickness is 2 nm to 10 nm, the effect of the method for manufacturing a semiconductor device according to the present invention can be obtained, and when the film thickness is 10 nm to 50 nm, The effect of the method for manufacturing a semiconductor device according to the invention of claim 9 can be obtained.

[Brief description of drawings]

FIG. 1A is a schematic perspective view showing a quantum effect element according to a first embodiment of the present invention. (B) is a sectional view in the source / drain direction. (C) is a diagram showing an energy level in a cross section in the source / drain direction.

2A to 2C are perspective views and cross-sectional views in order of the steps, showing the method for manufacturing the quantum effect element according to the first embodiment of the present invention.

3A to 3C are perspective views in order of the steps, showing the method for manufacturing the quantum effect element according to the first embodiment of the present invention.

FIG. 4A is a partial plan view showing a semiconductor device according to a second embodiment of the present invention. FIG. 9B is a partial plan view showing a semiconductor device according to a first modification of the second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a semiconductor device according to a first modification of the second embodiment of the present invention.

FIG. 6 is a timing chart showing each control voltage in the semiconductor device according to the first modification of the second embodiment of the present invention.

FIG. 7 is a partial plan view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a process order cross-sectional view taken along the line III-III of FIG. 7, showing the method for manufacturing the semiconductor device according to the third embodiment of the invention.

FIG. 9A is a schematic circuit diagram showing a 4-terminal single electronic device used in a conventional pseudo CMOS single electronic circuit.
(B) is a graph showing the simulation result of the operation of the conventional 4-terminal single electronic device.

[Explanation of symbols]

 11 quantum wire 11a silicon island part 12 tunnel barrier part 13 gate insulating film 14 gate electrode 15 insulating film 16 control electrode 17 silicon oxide film 18 conductive probe needle 20 SOI substrate 21 silicon substrate 22 embedded oxide film 23 thin film silicon layer 23a 1st Quantum wire 23b second quantum wire 23c crossing portion 24A first straight line pattern 24B second straight line pattern 24C crossing portion 25a tunnel barrier 25b insulating film 30 carrier transfer portion 30A first carrier transfer portion 31 first quantum thin wire 32 2nd quantum wire 33 3rd quantum wire 33A 2nd carrier transfer part 41 1st tunnel barrier 42 2nd tunnel barrier 43 3rd tunnel barrier 44 4th tunnel barrier 51 1st gate electrode 52 Second gate electrode 53 Third gate electrode 6 SOI substrate 61 Silicon substrate 62 Embedded oxide film 63A Upper silicon layer 63B Thin film silicon layer 63a First quantum wire 63b Second quantum wire 63c Third quantum wire 65A Silicon oxide film (first linear pattern) 65C Silicon oxide film (Second linear pattern) 66A Barrier oxide film (first tunnel barrier) 66B Barrier oxide film (second tunnel barrier) 66C Barrier oxide film (third tunnel barrier) 66D Barrier oxide film (fourth tunnel barrier) ) 67 silicon oxide film (interlayer insulating film) 68A first gate electrode 68B second gate electrode 68C third gate electrode 81 first branch portion (first carrier transfer portion) 82 second branch portion (first 2 carrier transfer part) 90 probe needle

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiko Hirai 1006 Kadoma, Kadoma City, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (72) Koichiro Ko, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (10)

[Claims] 1. A quantum wire made of silicon, a pair of tunnel barrier portions formed in the quantum wire at intervals in a direction in which the quantum wire extends, and a pair of tunnel barrier portions in the quantum wire. A quantum effect element comprising: a gate insulating film formed on the sandwiched island portion; and a gate electrode formed on a surface of the gate insulating film opposite to the quantum wires. 2. A step of forming a thin film silicon layer by thinning the upper silicon layer by etching the entire main surface of the upper silicon layer of the SOI substrate, and forming a conductive film on the main surface of the thin film silicon layer. Electric field assist is performed on the surface of the thin film silicon layer by approaching the probe needle and scanning the conductive probe needle parallel to one side of the SOI substrate and along the main surface to perform electric field assisted oxidation. Forming a first linear pattern made of an oxide film, bringing a conductive probe needle close to a predetermined region of the first linear pattern, and making the conductive probe needle perpendicular to the first linear pattern. And performing electric field assisted oxidation by scanning along the main surface, the surface of the thin film silicon layer is formed of an electric field assisted oxide film, and the first linear pattern is formed. A step of forming a second linear pattern having an intersection with an edge, and performing anisotropic etching on the thin film silicon layer using the first linear pattern and the second linear pattern as a mask, Forming a first quantum wire and a second quantum wire made of silicon and having an intersecting portion; and removing the first straight line pattern and the second straight line pattern, and then forming an intersecting portion in the first quantum thin wire. First to sandwich
Forming a tunnel barrier made of an electric field assisted oxide film in each of the first region and the second region by performing electric field assisted oxidation by sequentially approaching the conductive probe needle to the region and the second region. , A third region and a fourth region sandwiching the intersection of the second quantum wire are sequentially brought closer to the third region and the fourth region to perform electric field assisted oxidation, thereby performing the third region and the fourth region.
And a step of forming an insulating film made of an electric field assisting oxide film in each region. 3. An island-shaped carrier transfer section made of silicon formed on an SOI substrate and a first carrier transfer section on the SOI substrate at one end of the carrier transfer section.
A first quantum wire made of silicon formed through the tunnel barrier of the second carrier, and a second quantum wire on the SOI substrate and at the other end of the carrier transfer part.
A second quantum wire made of silicon formed through the tunnel barrier of the above, and formed on the SOI substrate and between the one end and the other end of the carrier transfer unit through the third tunnel barrier. A third quantum wire made of silicon, a first control electrode formed on the carrier transfer portion via an insulating film, and a second control wire formed on the second quantum wire via an insulating film. A semiconductor device comprising: a control electrode; and a third control electrode formed on the third quantum wire via an insulating film. 4. The first, second, and third tunnel barriers are formed by a quantum wire constriction in which a part of the quantum wire has a smaller cross-sectional area than the other part. 3. The semiconductor device according to item 3. 5. An island-shaped first carrier transfer portion made of silicon formed on an SOI substrate, and on the SOI substrate and at one end of the first carrier transfer portion via a first tunnel barrier. A first quantum wire made of silicon and a second quantum wire made of silicon formed on the SOI substrate and at the other end of the first carrier transfer portion via a second tunnel barrier; An island-shaped second carrier transfer part made of silicon formed on the SOI substrate and between the one end and the other end of the first carrier transfer part via a third tunnel barrier; A third quantum wire made of silicon formed on the SOI substrate and on a side of the second carrier transfer section on the side of the second quantum wire via a fourth tunnel barrier; No carrier transfer A first control electrode formed via a film; a second control electrode formed on the second quantum wire and the third quantum wire via an insulating film; and a second carrier transfer unit. A semiconductor device, comprising: a third control electrode formed via an insulating film. 6. The first, second, third, and fourth tunnel barriers are formed by a quantum wire constriction in which a part of the quantum wire has a smaller cross-sectional area than the other part. The semiconductor device according to claim 5. 7. A step of forming a thin film silicon layer by thinning the upper silicon layer by etching the entire main surface of the upper silicon layer of an SOI substrate, and forming a thin film silicon layer on the main surface of the upper silicon layer with conductivity. Electric field assist is performed on the surface of the thin film silicon layer by approaching the probe needle and scanning the conductive probe needle parallel to one side of the SOI substrate and along the main surface to perform electric field assisted oxidation. Forming a first linear pattern made of an oxide film, bringing a conductive probe needle close to a predetermined region of the first linear pattern, and making the conductive probe needle perpendicular to the first linear pattern. And performing electric field assisted oxidation by scanning along the main surface, the surface of the thin film silicon layer is formed of an electric field assisted oxide film, and the first linear pattern is formed. Forming a second straight line pattern connected by the first branch portion to the conductive line, and bringing the conductive probe needle close to a predetermined region of the second straight line pattern, The electric field assisted oxidation is performed by scanning perpendicularly to the second linear pattern and along the main surface to form an electric field assisted oxide film on the surface of the thin film silicon layer. Forming a third straight line pattern connected by two branch portions, the first straight line pattern, the second straight line pattern and the third straight line pattern
Anisotropic etching is performed on the thin film silicon layer using the linear pattern as a mask, the first quantum wire and the second quantum wire made of silicon and connected to each other at the first branch portion; Forming a second quantum wire and a third quantum wire connected at a second branch, and opposing the third quantum wire to the first branch in the first quantum wire. By conducting the electric field assisted oxidation by bringing the conductive probe needle close to the first region on the side,
Forming a first tunnel barrier made of an electric field assisting oxide film in the first region, and forming a second tunnel barrier in the second region on the side of the third quantum wire with respect to the first branch portion of the first quantum wire. Forming a second tunnel barrier made of an electric field assisted oxide film in the second region by performing electric field assisted oxidation by bringing a conductive probe needle close to the second region; and the second tunnel wire in the second quantum wire. By conducting the electric field assisted oxidation by bringing the conductive probe needle close to the third region on the side of the first branch portion with respect to the branch portion, the third region is formed.
Forming a third tunnel barrier made of an electric field assisting oxide film in the region of 4), and forming a third tunnel barrier in the third quantum wire on the side of the second branch portion.
Forming a fourth tunnel barrier made of an electric field assisted oxide film in the fourth region by bringing a conductive probe needle close to the region to perform electric field assisted oxidation, and covering the entire surface of the SOI substrate. Depositing an interlayer insulating film, forming a first control electrode on the interlayer insulating film and in a region above the first branch portion, on the interlayer insulating film, Forming a second control electrode in a region above the third quantum wire side with respect to the second tunnel barrier in the first quantum wire and in a region above the third quantum wire; And a step of forming a third control electrode on the film and in a region above the second branch portion. 8. The semiconductor according to claim 7, wherein the first, second, third and fourth tunnel barriers are formed by completely oxidizing the cross section of the quantum wire. Device manufacturing method. 9. The method according to claim 7, wherein the first, second, third, and fourth tunnel barriers are formed by oxidizing a part of a cross section of the quantum wire. Manufacturing method of semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the film thickness of the thin film silicon layer on the SOI substrate is 50 nm or less.