JP2003078128A - Quantum effect element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide such a quantum effect element that is extremely small in element occupation area and low in power consumption. SOLUTION: A silicon island 11a is formed in a quantum thin line 11 made of silicon while it is pinched by a pair of tunnel barriers 12 made of silicon oxide film. A gate electrode 14 for controlling potential is provided on the side of the silicon island 11a with a gate insulation film 13 made of interposed silicon oxide film, and a control electrode 16 for controlling potential is provided on the other side thereof with an insulation film 15 made of interposed silicon oxide film. The tunnel barrier 12 has such a quantum thin line constriction structure that a silicon oxide film 17 as an electric boundary supporting oxide film formed using an interatomic force microscope or the like is formed by oxidizing the quantum thin line from its surface to its nearly central part.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its semiconductor device.
In particular, a quantum effect device and a method of manufacturing the same
Method and a single electron transistor using a semiconductor wire.
A semi-conductor that forms a binary decision diagram circuit and simplifies the circuit.
The present invention relates to a body device and a method of manufacturing the same. [0002] In recent years, LS for personal portable equipment has been developed.
There is a strong demand for low power consumption of I. Low power consumption of LSI
Powering will reduce the overall power consumption of mobile devices,
It is possible to extend the operating time in battery operation.
As a result, semiconductor devices are steadily reducing power consumption.
Have been In recent years, CMs that have become the mainstream of semiconductor devices
In the case of the OS type semiconductor element, the power consumption P is P = f
・ C ・ V ^Two Is represented by Where f is the operating frequency of the circuit
Number, C is the equivalent capacitance of the entire circuit, and V is the operating power supply voltage.
You. As a result, when the operating frequency f is compared with the same value,
In order to reduce the power consumption P, the equivalent capacitance of the entire circuit
It is necessary to reduce the operating power supply voltage V by reducing C
Become. Reducing capacitance and operating voltage is immediate.
In other words, reducing the number of moving carriers
You. Accordingly, the power consumption of the semiconductor device is reduced.
To reduce the number of carriers carrying signals.
Is necessary. A single electronic device is its ultimate form,
Signal is transmitted by one electron (Nakazato et al., IEDM
Tech. Digest, p487 (1992)). This single electronic device is
Attention as a leading candidate for Si-VLSI
You. With the recent development of microfabrication technology, the wavelength of electrons and
It is possible to form microstructures of the same degree, and several
Today's semiconductors use electronic elements to represent bit information
Attempts to build a single electronic device as an extension of the device concept
Has been done. Hereinafter, a conventional four-terminal single-electron element will be described with reference to the drawings.
It will be described with reference to FIG. FIG. 9A shows a conventional pseudo CMOS single electron.
FIG. 2 is a schematic circuit diagram showing a four-terminal single electronic element used in a circuit.
(Tucker JR: J. Appl. Phys. 72, 4399 (1992)).
As shown in FIG. 9A, a conventional four-terminal single-electron element
Has one electrode connected to the common connection portion 101 and the other
First tunnel with electrode connected to drain terminal 102
The junction 103 and one electrode are connected to the common connection portion 101.
And the second electrode whose other electrode is connected to the source terminal 104.
The tunnel junction 105 and one electrode are connected to the common connection portion 101
And the other electrode is connected to the gate terminal 106.
The first capacitor 107 and one electrode are connected to a common connection portion.
101, the other electrode is connected to the power terminal 108
And the second capacitor 109 formed. [0007] The operation of a four-terminal single-electron element can be, for example,
The source terminal 108 is set to the power supply voltage VDD, and the gate terminal 10
By operating 6 as a gate electrode, it becomes an n-type element,
The power terminal 108 is grounded, and the gate terminal 106 is
When operated as a pole, it becomes a p-type element. So this
Combine n-type and p-type four-terminal single-electron elements one by one
In other words, it is possible to construct a circuit equivalent to a CMOS circuit.
it can. FIG. 9B shows the operation of the conventional four-terminal single-electron element.
Are the simulation results, and the MOSFET Vd−
It is expected that characteristics similar to the Id characteristics will be obtained.
You. SUMMARY OF THE INVENTION
Conventional single electronic devices transmit signals with one electron
This is one of the ultimate devices from the perspective of lower power consumption.
Although it is considered one, there are two problems as listed below
have. The first problem is in the processing technology. Processing technology
Use silicon with excellent mass productivity and material stability.
In order to realize the device of FIG.
As shown in FIG. 9 (b), the capacitance of the tunnel junction is
Number aF (Atfarad: 10 ^-18 F) and extremely small
Value must be set, and nano-level fine processing technology cannot be used.
Will be missing. Amount using conventional electron beam lithography technology
In the manufacturing method of the child effect element, drawing with a width of about 10 nm is limited.
Element and a few nanometers or less in which a remarkable quantum effect can be expected.
The problem is that the formation of particles is difficult. In addition,
When using a strand, process
The problem of deterioration of device characteristics due to image formation
have. The second problem is in circuit technology. Circuit technology
Regarding single electronic devices, the mainstream of conventional VLSI
The operation mechanism is different from CMOS technology, and the principle
Input voltage and output voltage are extremely small,
It is necessary to apply a logic circuit technology different from the circuit technology.
You. On the other hand, a binary decision was made using a single-electron transistor.
There has been a proposal to build a constant graph circuit (Yoshi Amamiya
Jin et al., Applied Physics, 64, No. 8, 765-768 (1995)). The present invention solves the above-mentioned conventional problems and provides an element.
Extremely small occupied area and low power consumption quantum effect
An object is to realize an element. [0012] In order to achieve the above object,
Therefore, the present invention is compatible with existing silicon semiconductor technology,
Field-Assisted Oxidation Process Using Scanning Probe Microscope
Damage-free pro using crystal and crystal anisotropic etching
This is a configuration using a process. A single electronic device
In principle, the input and output voltages are very small,
Must be combined with other devices that can handle large pressure amplitudes
Yes, using the manufacturing method using the present invention
Easy and secure coupling to certain Si-CMOS devices
Can be made. Means for solving the problems specifically taken by the invention of claim 1
Describes a quantum effect device that is made up of a silicon quantum wire and a quantum wire.
The quantum wires are spaced from each other in the direction in which the quantum wires extend.
A pair of tunnel barrier portions formed in
Line between the pair of tunnel barriers.
A gate insulating film formed on the island portion, and the gate insulating film
Formed on the surface opposite to the quantum wire of
And an electrode. According to the first aspect of the present invention, the semiconductor device is made of silicon.
Has an island part sandwiched between a pair of tunnel barrier parts
Via the quantum wire and the gate insulating film formed on the island
And the provided gate electrode,
One end is the source electrode and the other end is the drain electrode
And a single electronic device used for a pseudo CMOS single electronic circuit.
Can be reliably realized. Furthermore, for the gate electrode in the island,
Another gate electrode is provided on the opposite side via an insulating film.
For example, a four-terminal single electronic device can be easily realized.
You. (First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings. FIG. 1A relates to a first embodiment of the present invention.
1 is a schematic perspective view showing a quantum effect device. In FIG. 1 (a)
As shown in FIG.
Sandwiched between a pair of tunnel barrier portions 12 made of an oxide film.
A silicon island portion 11a is formed. Silicon Island
A gate made of a silicon oxide film is provided on one side of the portion 11a.
A gate electrode 14 for potential control is provided through the insulating film 13.
The other side of the silicon island 11a
Control electrode for controlling electric potential via an insulating film 15 made of an oxide film
16 are provided. The width and thickness of the quantum wires 11 are not
About 10 nm so that the capacitance value of the wall portion 12 becomes sufficiently small.
Degrees are preferred. The tunnel barrier section 12 forms the quantum wire 11
By locally oxidizing 2 nm to 5 nm in the film thickness direction
Is formed. The gate insulating film 13 and the insulating film 15
Both are made of silicon oxide and have a width of 200 nm or less
And preferably several tens nm. Also silicon
The island 11a has a width of 10 nm and a length of 200 nm or less.
Below and several tens of nm are preferred. The gate electrode 14 and
The control electrode 16 is a single crystal to which an n-type impurity is added at a high concentration.
Silicon, but not limited to metal
It may be silicon. The quantum effect device according to the present embodiment has terminals
Are the four terminals of the pseudo CMOS single electronic circuit shown in FIG.
Each corresponds to a terminal of a single electronic element. Sandals
One end 11b of the quantum wire 11 is connected to the source terminal 104,
The other end 11 c of the quantum wire 11 is connected to the drain terminal 102.
The gate electrode 14 is connected to the gate terminal 106, and the control electrode 16 is connected to the gate terminal 106.
Each corresponds to a source terminal 108. Therefore, the control
When the power supply potential VDD is applied to the pole 16, the n-channel transistor
It functions as a transistor and applies a ground potential to the control electrode 16.
Then, it functions as a p-channel transistor. FIG. 1B is a diagram showing the source / destination shown in FIG.
It is sectional drawing of a rain direction. Silicon island 11a is ton
A pair of silicon oxide films 17 forming the tunnel barrier 12
They are formed at intervals in the direction in which the quantum wires 11 extend.
Have been. Here, each silicon oxide film 17 is formed of the quantum wire 1
1 is formed from the surface to almost the center thereof.
It does not reach the bottom of the fine wire 11. Quantify this structure
It is referred to as a fine wire constriction structure. So
As a result, when tunnel current flows,
In addition, the speed of the carrier increases. FIG. 1 (c) shows the source / destination shown in FIG. 1 (a).
It is a figure which shows the energy level of the cross section of a rain direction. Figure
As shown in FIG. 1 (c), the quantum
Because of the fine wire construction structure,
The energy band gap Eg2 of the barrier region 12 is
Greater than the energy band gap Eg1 of line 11.
You can see that it is. Here, C.I. B. Is the conduction band,
V. B. Represents a valence band. As described above, the quantum effect device of the present embodiment
According to this, bit information can be described with several electrons and
Extremely low power consumption because a CMOS structure can be formed
Power element can be realized. Further, the present quantum effect device has a silicon island portion.
Element area of several tens nm on one side in principle even when 11a is included
It is possible to achieve ultra-high integration. The gate insulating film 13 and the gate electrode 1
4 and the insulating film 15 and the control electrode 16 are named for convenience.
And the corresponding members are the same,
The edge film 13 side is a power supply terminal 108 and the control electrode 16 side is a gate terminal.
Obviously, it can be handled as the port terminal 106. Hereinafter, the quantum device according to the first embodiment of the present invention will be described.
A method for manufacturing the effect element will be described with reference to the drawings. FIGS. 2A to 2C and FIG. 3 show a second embodiment of the present invention.
Step showing a method for manufacturing a quantum effect device according to one embodiment
It is a forward perspective view and a sectional view. First, as shown in FIG.
Thus, a silicon substrate 21 having a plane orientation of (001) and the silicon
A 100 nm thick buried layer formed on the recon substrate 21
Embedded film 22 and a buried oxide film 22
Or an upper silicon layer (not shown) with a thickness of 140 nm
The SOI substrate 20 made of
Oxidation for about 120 minutes in an atmosphere, on top of the upper silicon layer
Oxidized film formed by oxidation is converted to a hydrogen fluoride (HF) aqueous solution
Thinning the upper silicon layer by removing it in
A thin film silicon layer 23 having a thickness of 10 nm is formed. surface
Conductive probe needle coated with gold (Au) etc.
Reference numeral 18 in (b) shows only the tip. Have)
For example, an atomic force microscope (AFM) or a scanning tunnel
Use a scanning probe microscope such as a scanning microscope (STM)
And the conductive probe needle is formed into a thin film silicon.
After approaching the predetermined area of the layer 23, the conductive probe needle
<110> crystal while applying a bias voltage of -10V
Scan vertically or parallel to the axial direction to perform field-assisted oxidation.
The silicon oxide film as an electric field assisted oxide film
And a first straight line perpendicular to each other at the intersection 24C.
Forming a turn 24A and a second linear pattern 24B;
You. Next, as shown in FIG.
Diamine 1000ml, Pyrocatechol 144g
And a mixed solution of pure water of 290 ml is used as an etching solution.
While maintaining the etchant at a temperature of 80 ° C.,
1 minute silicon crystal anisotropic etching on plate 20
Perform The silicon crystal anisotropic etching is (11
1) The etching rate of the surface is about 8 nm / min.
On the other hand, the (100) and (110) directions are about 100 nm.
/ Min etching rate. In FIG. 2 (b)
As shown in FIG.
Characteristics and the first and second linear patterns made of a silicon oxide film.
Due to the etching resistance of the turns 24A and 24B,
After the etching, on the buried oxide film 22,
It has a (111) plane on the side and has an intersection 23c with each other
A first quantum wire 23a made of silicon and a second quantum wire
A silicon microstructure consisting of line 23b is formed. this
After that, the first linear pattern 24A and the second linear pattern
24B is removed with hydrofluoric acid or the like. Next, as shown in FIG.
Using a microscope, the first on the buried oxide film 22
Region including the first quantum wire 23a and the second quantum wire 23b
To measure the level difference,
Ask. Then, the intersection at the first quantum wire 23a
(-10) in the first region and the second region sandwiching 23c.
The conductive probe needle to which the bias voltage of V is applied is sequentially
By performing electric field assisted oxidation in close proximity,
Barrier composed of an electric field assisted oxide film in the first region and the second region
The walls 25a, 25a are respectively formed. For electric field assisted oxidation
The difference in the film thickness of silicon, which is the conductor,
This is reflected in gap differences,
A wall will be formed. As a result, the first quantum wire
23a is that the intersection 23c has two tunnel barriers 25a.
The source is connected to one end of the first quantum wire 23a
A terminal is formed at the other end, and a drain terminal is formed at the other end.
Each tunnel barrier 25a is provided with a conductive probe needle of a microscope.
By changing the bias voltage value, etc.,
The thickness of the passivation film can be changed.
Capacitance value and tunnel resistance value can be changed according to
You. Next, the intersection at the second quantum wire 23b
The third region and the fourth region sandwiching the portion 23c have (-3)
0) Connect the conductive probe needle to which a bias voltage of V was applied.
The electric field assisted oxidation is performed by sequentially approaching the third region and
And an insulating film 25b made of an electric field assist oxide film in the fourth region,
By forming each of the tunnels 25b, a pair of tunnels is formed.
Barriers 25a, 25a and a pair of insulating films 25b, 25b
Intersection 23c is formed as an enclosed silicon island
Is done. As a result, the second quantum wire 23b has two discontinuities.
Because it is insulated and separated by the edge films 25b, 25b,
A gate electrode for potential control is formed, and the other end for potential control
Will be formed. As described above, in the manufacturing method according to this embodiment,
According to the report, using a scanning probe microscope for pattern drawing
Therefore, fine processing on the order of several nm can be easily performed. Also, the conductivity in the electric field assisted oxidation process
By appropriately selecting the bias conditions of the probe needle,
Tunnel barrier capacity greatly related to device characteristics and operating temperature
The amount and resistance can be optimized and the silicon island
A pair of tunnel barriers 25 sandwiching the intersection 23c to be formed
It is also possible to form a and 25a asymmetrically. this
A pair of tunnel barriers 25a, 25a are formed asymmetrically
Thus, for example, the output side
The capacity of the tunnel barrier is greater than the capacity of the tunnel barrier on the input side.
To increase output speed.
There is an advantage that it can be cut. Further, the electric field assisted oxidation process is performed on silicon.
Crystal anisotropic etching process that only modifies the atomic surface
Is also a wet process, so process damage free
Interface interface, which can cause malfunction of a single electronic device.
To minimize offset charges such as
Can be. Further, the crystal anisotropic etching is used.
Therefore, the side surface of the quantum wire is flat at the atomic level,
Excellent in width uniformity and linearity in the longitudinal direction.
Expected to improve electron mobility due to quantum mechanical effects
As a result, high-speed operation is possible. (Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. FIG. 4A shows a second embodiment of the present invention.
FIG. 2 is a partial plan view showing a semiconductor device according to the first embodiment. FIG. 4 (a)
And a carrier transfer made of silicon on an SOI substrate.
Transmitting section 30 and one end of the carrier transfer section 30
Silicon electrically connected through the channel barrier 41
The first quantum wire 31 and the carrier transfer unit 30
The end is electrically connected through a second tunnel barrier 42.
Quantum wire 32 made of doped silicon and carrier
A third token is provided between the one end and the other end of the transfer unit 30.
Silicon electrically connected through the channel barrier 43
A third quantum wire 33 is formed. Further, an insulating film is formed on the carrier transfer section 30.
(Not shown) as a control electrode formed through
Gate electrode 51 and an insulating film on the second quantum wire 32
Second gate electrode 52 formed via (not shown)
And an insulating film (not shown) on the third quantum wire 33
And a third gate electrode 53 formed by
You. The carrier transfer unit 30 and the first to third quantum units
Each of the thin wires 31 to 33 has a width of 100 nm or less and is conductive.
What is necessary is just to have the property. First to third tunnel barriers 41
43 operate as energy barriers, and
Any material can be used as long as the current flows. In addition, the first to third
If the gate electrodes 51 to 53 can transmit a potential,
Regardless of the material. The first quantum wire 31 is used as a signal input part, and
Is A. The second quantum wire 32 is connected to the first
The output voltage is defined as Y0. Third quantum
The thin line 33 is used as a second output detector, and its output voltage is represented by Y1
And The third gate electrode 53 is used as a signal control electrode,
The control potential is X0. A first gate electrode 51 and
The second gate electrode 52 is used as a clock control electrode.
The control potentials are φ1 and φ2, respectively. FIG. 4B shows a second embodiment of the present invention.
FIG. 14 is a partial plan view showing a semiconductor device according to a modification. Figure
In FIG. 4 (b), on the SOI substrate,
A first carrier transfer section 30A, and the first carrier transfer section 30A.
A first tunnel barrier 41 is provided at one end of the sending section 30A.
First quantum wire 3 made of electrically connected silicon
1 and a second token at the other end of the first carrier transfer section 30A.
Silicon electrically connected through the channel barrier 42
A second quantum wire 32 and a first carrier transfer unit 3
A third tunnel between said one end of said OA and said other end
Made of silicon electrically connected via the barrier 43
A second carrier transfer section 33A and the second carrier transfer
A fourth portion is provided on a side portion of the portion 33A on the side of the second quantum wire 32.
Silicon electrically connected through a tunnel barrier 44
A third quantum wire 34 is formed. Further, on the first carrier transfer section 30A,
Gate formed through an insulating film (not shown)
The electrode 51 and the second and third quantum wires 32 and 3
4 formed on an insulating film (not shown)
On the gate electrode 52 and the second carrier transfer section 33A
A third gate electrode formed via an insulating film (not shown)
A pole 53 is formed. The first and second carrier transfer units 30A, 30
3A and the first to third quantum wires 31, 32, 34
It is only necessary that each width is 0.1 μm or less and it has conductivity.
No. The first to fourth tunnel barriers 41 to 44 are energy
Works as a physical barrier, and if a tunnel current flows, the material
Regardless of the fee. Also, the first to third gate electrodes 51 to 5
3 is not limited as long as it can transmit electric potential.
No. The first quantum wire 31 is used as a signal input section, and
Is A. The second quantum wire 32 is connected to the first
The third quantum wire 34 is used as a second output detector.
It is assumed that the sensing unit is Y1. The third gate electrode 53 is connected to a signal control
And its control potential is X0. First gate electrode
51 and the second gate electrode 52 as clock control electrodes.
The control potentials are φ1 and φ2, respectively. FIG. 5 shows a first modification of the second embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram of a semiconductor device according to an example. The first carry
The transfer unit 30A includes a first tunnel barrier 41 and a second tunnel
Surrounded by a tunnel barrier 42 and a third tunnel barrier 43.
The second carrier transfer unit 33A is in the third tunnel
Surrounded by a barrier 43 and a fourth tunnel barrier 44.
Therefore, the first carrier transfer unit 30A or the second carrier
A) When electrons are stored in the transfer unit 33A, the cool
Other electrons cannot be stored due to the interaction. Also,
Suitable for the first gate electrode 51 or the third gate electrode 53
When a very low potential is applied, the first carrier transfer unit 3
0A or electrons leak from the second carrier transfer unit 33A
Never even. When electrons exist in the first quantum wire 31
In this case, an appropriate high potential is applied to the first gate electrode 51.
Then, the electrons in the first quantum wire 31 become the first carrier
Move to transfer section 30A. At this time, the third gate electrode
When a higher potential is applied to 53, the first carrier
The electrons that have moved to the transmission unit 30A are further transferred to the second carrier.
Move to sending section 33A. FIG. 6 shows a first modification of the second embodiment of the present invention.
Timing indicating each control voltage in a semiconductor device according to an example
It is a chart. At the timing shown in FIG.
Control potentials φ1, φ corresponding to the three gate electrodes 51 to 53
When X0 and X0 are respectively applied, the output of the first output
The output voltage Y0 and the output voltage Y1 of the second output detection unit
The charge is exclusively output. As a result, the circuit according to this embodiment is
If the control potential X0 is H (high), the input voltage A
Transfer the load to the second output detector as an output voltage Y1.
On the other hand, if the control potential X0 is L (low)
If so, the output is transferred to the first output detector as the output voltage Y0.
So that a BDD circuit is constructed.
Will be. Therefore, according to the present embodiment, the quantum wire is
Binary decision diagram circuit by single electron transistor used
Are easily and reliably formed. The material constituting the quantum wires is silicon.
Was used, but any material having conductivity may be used. Tonne
The barrier acts as an energy barrier,
It is only necessary for the flow to flow, for example, a thin silicon oxide film,
Quantum Wire Constriction Structure by Edge Oxidation of Wire
It is preferable to use a structure or the like. As a material for the gate electrode,
Always for consistency with the silicon multilayer wiring process
Aluminum etc. can be considered, but it can transmit electric potential
Any material that can be used may be used. (Third Embodiment) Hereinafter, a third embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. FIG. 7 shows a semiconductor device according to a third embodiment of the present invention.
It is a partial plan view showing a body device. 8 (a) to 8 (f)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described.
FIG. 8 is a sectional view taken along line III-III in FIG.
First, for example, as shown in FIG.
Using a silicon substrate 61 and the silicon substrate 61
A buried oxide film 62 formed thereon and having a thickness of 80 nm;
180 nm thick formed on the buried oxide film 62
And the upper silicon layer 63 whose main surface has a plane orientation of <100>
A SOI substrate 60 made of A is formed. Next, as shown in FIG.
The plate 60 is kept in an oxygen atmosphere at a temperature of 1000 ° C. for about 120 minutes.
Oxidation during formation, formed by oxidation on the upper silicon layer 63A
Oxide film removed in an aqueous solution of hydrogen fluoride (HF)
This makes the upper silicon layer 63A thinner,
A 50 nm thin film silicon layer 63B is formed. Next, as shown in FIG.
It has a conductive probe needle 90 coated with (Au) or the like.
For example, an atomic force microscope (AFM) or a scanning tunnel
Use a scanning probe microscope such as a scanning microscope (STM)
Then, the conductive probe needle 90 is
Where the first linear pattern on the main surface of the cone layer 63B is formed
Approach the fixed area. Then, the conductive probe needle 90 is
A ground potential, and a + 9V via in the thin film silicon layer 63B
While the probe voltage is applied, the conductive probe needle 90 is moved every second.
At a speed of about 0.25 μm on the main surface of the thin silicon layer 63B.
Move linearly along the line and apply it to the thin silicon layer 63B
Field-assisted oxidation by the applied electric field
On the surface of the layer 63B, the line width is about 100 nm and the film thickness is 5 nm.
Field-assisted oxide film of
A silicon oxide film 65A is formed. Then, the first straight line
The first as a first carrier transfer unit in the pattern
From the branch portion (reference numeral 81 shown in FIG. 7), the first
Same as the second straight line pattern extending perpendicular to the straight line pattern
Formed using an electric field assisted oxidation method,
The second as a second carrier transfer unit in the pattern
From the branch portion (reference numeral 82 shown in FIG. 7), the second
Extending perpendicular to the straight line pattern and parallel to the first straight line pattern
Silicon oxide film 65C as a third linear pattern
Are similarly formed. Next, as shown in FIG.
Diamine 300ml, Pyrocatechol 48g and pure
Using a mixed solution of 98 ml of water as an etching solution,
While maintaining the etching liquid at a temperature of 80 ° C., the SOI substrate 60
Then, anisotropic etching is performed for 30 seconds. This edge
The etching solution etches silicon,
The pitching speed differs depending on the plane orientation, and <111
> Direction is very slow compared to other plane orientations. Therefore,
Thin silicon layer after immersion in the etching solution for 30 seconds
63B is a lower portion of the silicon oxide films 65A, 65C and the like.
Only the first quantum wire 63a, the second quantum wire
(Reference numeral 63b shown in FIG. 7) and the third quantum wire 63c
Each is formed. Each quantum wire 63a, 63b, 63
The side surfaces of c are <111> surfaces. here
The upper surface of each quantum wire 63a, 63b, 63c is made of silicon.
Etchin because it is protected by oxide film 65A etc.
Not be logged. Next, as shown in FIG.
The third with respect to the first branch portion 81 in the fine wire 63a
A conductive probe is provided in a first region opposite to the quantum wire 63c.
With the needle 90 approaching, the conductive probe needle 90 is
+15 V applied to the ground potential and to the first quantum wire 63a
Of the conductive probe needle 90 while applying a bias voltage of
Is approximately 0.25 per second perpendicular to the first quantum wire 63a.
Moves along the surface of the first quantum wire 63a at a speed of μm
Let it. This allows electric field assisted oxidation by the applied electric field
The first region has a line width and a film thickness of about 10 nm.
A barrier oxide film as a first tunnel barrier (reference numeral shown in FIG. 7)
No. 66A). Similarly, the first quantum wire 63a
Of the third quantum wire 63 for the first branch portion 81 in FIG.
By bringing the conductive probe needle 90 close to the second region on the c side
By performing the electric field assisted oxidation, an electric field is applied to the second region.
Barrier acid as second tunnel barrier comprising assisted oxide
An oxide film 66B is formed. Subsequently, the second quantum fine
First branch to second branch 82 at line 63b
Approach the conductive probe needle 90 to the third area on the part 81 side.
To perform the electric field assisted oxidation,
Obstacle as Third Tunnel Barrier Made of Field-Assisted Oxide Film
While forming a wall oxide film (66C shown in FIG. 7),
The third quantum wire 63c on the second branch 82 side
Electric field assist by bringing conductive probe needle 90 close to area 4
By performing oxidation, an electric field assisted oxidation is applied to the fourth region.
Barrier oxide film as a fourth tunnel barrier made of
No. 66D) shown in FIG. Next, for example, as shown in FIG.
A normal pressure CVD method is used to cover the entire surface of the SOI substrate 60.
Silicon as a 100-nm-thick interlayer insulating film
After depositing the oxide film 67, the silicon
500 nm thick over the entire surface of the oxide film 67
Deposit an aluminum thin film. After that, photolithography
The aluminum thin film selectively using
Is performed, and the first branch 81
The gate electrode (reference numeral 68A shown in FIG. 7) and the first quantum
Third quantum wire 6 of barrier oxide film 66B at line 63a
2c above the 3c side and above the third quantum wire 63c.
A gate electrode (reference numeral 68B shown in FIG. 7) and a second branch portion
A third gate electrode 68C is formed above 82.
I do. As described above, according to the present embodiment, the second
The binary decision diagram circuit shown in the first modification of the embodiment
A single device using quantum wires with the same configuration as the semiconductor device to be realized.
Reliable semiconductor devices composed of electronic transistors
Can be manufactured. Further, a scanning probe microscope was used for pattern drawing.
Because it is used for images, fine processing on the order of several nanometers is easy.
And conductivity in the field assisted oxidation process
By properly selecting the probe needle bias conditions,
Tunnel barrier capacitance greatly related to element characteristics and operating temperature
Value and resistance can be optimized. Further, the electric field assisted oxidation process is performed on silicon.
Crystal anisotropic etching process that only modifies the atomic surface
Is also a wet process, so process damage free
Interface interface, which can cause malfunction of a single electronic device.
To minimize offset charges such as
Can be. Further, crystal anisotropic etching is used.
Therefore, the side surface of the quantum wire is flat at the atomic level,
Excellent in width uniformity and linearity in the longitudinal direction.
Expected to improve electron mobility due to quantum mechanical effects
As a result, high-speed operation is possible. Note that silicon was used as the material of the quantum wires.
However, any material may be used as long as it has conductivity. The barrier oxide film completely oxidizes each quantum wire.
Quantum due to oxidation at the periphery of quantum wires
Barrier formed by fine wire constriction structure
However, if the line width of each quantum wire can be further reduced,
The fine wire may be completely oxidized. In this way, the device
Leakage current is suppressed and the cooling temperature of the
It can be relatively hot. Note that each barrier oxide film is
It acts as an energy barrier and can pass tunnel current.
Any material can be used as long as the material can be used. For example,
Quantum thinning due to peripheral oxidation of thin silicon oxide films and quantum wires
A line concentration structure or the like may be used. The material of the gate electrode is silicon
Aluminum for compatibility with multi-layer wiring process
Was used, but if the potential could be transmitted, the material was
It goes without saying that it does not matter. The material of the conductive probe needle is generally
In addition, gold-coated silicon is used.
Tungsten and silicon with impurity diffusion
May be used. Further, ethylene diamine is used for anisotropic etching.
Used a mixed aqueous solution of
The etching speed differs depending on the plane orientation.
Etching speed is much slower than other
If available, use potassium hydroxide (KOH) or tetramethylan
Other solutions such as monium hydroxide (TMAH)
May be used. In this case, the plane orientation of the main surface is
Needless to say, it needs to be changed by anisotropy.
No. According to the quantum effect device according to the first aspect of the present invention,
Is made of silicon and sandwiched between a pair of tunnel barriers.
A quantum wire having an island formed by
And a gate electrode provided via a gate insulating film.
Therefore, one end of the quantum wire is used as the source electrode,
Is the drain electrode, bit information is described by several electrons
Single electronic device for use in a possible pseudo CMOS single electronic circuit
Can be reliably realized. Furthermore, the gate electrode on the island
Connect another gate electrode to the opposite side via an insulating film
In this way, a four-terminal single electronic device can be easily and reliably realized.
Can be This enables extremely low power consumption devices
Can be realized, and in principle even if islands are included,
Ultra-high integration is possible because the side can be accommodated in an element area of several tens of nanometers.
It becomes possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic perspective view showing a quantum effect device according to a first embodiment of the present invention. (B) is a sectional view in the source / drain direction. (C) is a diagram showing an energy level of a cross section in the source / drain direction. 2A and 2B are a perspective view and a cross-sectional view illustrating a method of manufacturing the quantum effect device according to the first embodiment of the present invention in the order of steps. FIG. 3 is a perspective view illustrating a method of manufacturing the quantum effect element according to the first embodiment of the present invention in the order of steps. FIG. 4A is a partial plan view showing a semiconductor device according to a second embodiment of the present invention. (B) is a partial plan view showing a semiconductor device according to a first modification of the second embodiment of the present invention. FIG. 5 is an equivalent circuit diagram of a semiconductor device according to a first modification of the second embodiment of the present invention. FIG. 6 is a timing chart showing control voltages in a semiconductor device according to a first modification of the second embodiment of the present invention. FIG. 7 is a partial plan view showing a semiconductor device according to a third embodiment of the present invention. FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention, in the order of steps along line III-III in FIG. 7; FIG. 9A is a schematic circuit diagram showing a four-terminal single-electron element used in a conventional pseudo CMOS single-electronic circuit.
(B) is a graph showing a simulation result of the operation of the conventional four-terminal single-electron element. DESCRIPTION OF SYMBOLS 11 Quantum wire 11 a Silicon island part 12 Tunnel barrier part 13 Gate insulating film 14 Gate electrode 15 Insulating film 16 Control electrode 17 Silicon oxide film 18 Conductive probe needle 20 SOI substrate 21 Silicon substrate 22 Embedded oxide film 23 Thin film Silicon layer 23a First quantum wire 23b Second quantum wire 23c Intersection 24A First linear pattern 24B Second linear pattern 24C Intersection 25a Tunnel barrier 25b Insulating film 30 Carrier transfer unit 30A First carrier transfer unit 31 First quantum wire 32 Second quantum wire 33 Third quantum wire 33A Second carrier transfer section 41 First tunnel barrier 42 Second tunnel barrier 43 Third tunnel barrier 44 Fourth tunnel barrier 51 1st gate electrode 52 2nd gate electrode 53 3rd gate electrode 60 SOI Plate 61 Silicon substrate 62 Embedded oxide film 63A Upper silicon layer 63B Thin film silicon layer 63a First quantum wire 63b Second quantum wire 63c Third quantum wire 65A Silicon oxide film (first linear pattern) 65C Silicon oxide film (first linear pattern) 66A Barrier oxide film (first tunnel barrier) 66B Barrier oxide film (second tunnel barrier) 66C Barrier oxide film (third tunnel barrier) 66D Barrier oxide film (fourth tunnel barrier) 67 silicon oxide film (interlayer insulating film) 68A first gate electrode 68B second gate electrode 68C third gate electrode 81 first branch portion (first carrier transfer portion) 82 second branch portion (second Carrier transfer section) 90 Probe needle

────────────────────────────────────────────────── ───
[Procedure amendment] [Date of submission] December 11, 2002 (2002.12.
11) [Procedure amendment 1] [Document name to be amended] Description [Item name to be amended] Claims [Correction method] Change [Contents of amendment] [Claims] 1. Quantum wire made of silicon A pair of tunnel barrier portions formed on the quantum wire at a distance from each other in a direction in which the quantum wire extends; and an island portion sandwiched between the pair of tunnel barrier portions in the quantum wire. A quantum effect, comprising: a gate insulating film; and a gate electrode formed on a surface of the gate insulating film opposite to the quantum wires, wherein the quantum wires and the gate electrode are present in the same plane. element. 2. A quantum wire made of silicon, a pair of tunnel barriers formed on the quantum wire at intervals in a direction in which the quantum wire extends, and a pair of tunnel barriers in the quantum wire. A gate insulating film formed on an island portion sandwiched between the gate insulating film, a gate electrode formed on a surface of the gate insulating film opposite to the quantum wire, and the quantum wire sandwiched between the gate electrodes. And a control electrode formed with an insulating film interposed therebetween. 3. The transistor functions as an n-channel transistor when a power supply potential is applied to the control electrode, and functions as a p-channel transistor when a ground potential is applied to the control electrode. The quantum effect device according to 1.

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court II (Reference) H01L 29/78 H01L 29/78 622 29/786 (72) Inventor Seiji Araki 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Inside (72) Inventor Yoshihiko Hirai 1006 Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Inside (72) Koichiro Sachi 1006 Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F-term (reference) 5F048 AA01 AC03 AC10 BA01 BA16 BB01 BD01 5F110 AA01 AA06 AA09 BB13 CC10 DD05 DD13 EE03 EE08 EE09 EE30 EE44 FF02 FF09 FF22 FF29 GG02 GG12 GG17 GG24 GG28 GG29 HM12 QQ01 BA13A13 AC14 A13A14 BC BE07 BF01 BF05 BF45 BG37 BH09 BH10 BK09 CC03 CE00

Claims (1)

Claims: 1. A quantum wire made of silicon, a pair of tunnel barrier portions formed on the quantum wire at a distance from each other in a direction in which the quantum wire extends, and A gate insulating film formed on an island portion sandwiched between a pair of tunnel barrier portions, and a gate electrode formed on a surface of the gate insulating film opposite to the quantum wires. Quantum effect device.