JPH09331015A - Semiconductor package and its manufacture - Google Patents
Semiconductor package and its manufactureInfo
- Publication number
- JPH09331015A JPH09331015A JP14888196A JP14888196A JPH09331015A JP H09331015 A JPH09331015 A JP H09331015A JP 14888196 A JP14888196 A JP 14888196A JP 14888196 A JP14888196 A JP 14888196A JP H09331015 A JPH09331015 A JP H09331015A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- copper
- plating
- lead frame
- copper alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は集積回路等の半導体
素子のパッケージに係わり、特に銅合金からなるリード
フレームを用いた半導体パッケージ及びその製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element package such as an integrated circuit, and more particularly to a semiconductor package using a lead frame made of a copper alloy and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、リードフレーム素材としてはＦｅ
−Ｎｉ系合金が用いられていたが、熱伝導率が良く、値
段の安い銅合金が近年使用されつつある。しかし銅合金
は従来材に比べ腐食しやすく、表面にＣｕ2Ｏ ，ＣｕＯ
などの酸化物相を形成しやすいという欠点がある。この
ような酸化物相は、素材との密着性が悪く工程中に剥離
して、リード間の接触を起こすなどの問題がある。これ
を解決するため、特開昭60−183758号公報には、リード
フレームの全面に１.０μｍ 以上の銅めっきを施した
後、ダイボンディング，ワイヤボンディング等の加熱工
程を行って半導体パッケージを製造する方法が開示され
ている。2. Description of the Related Art Conventionally, Fe is used as a lead frame material.
-Ni-based alloys have been used, but copper alloys, which have good thermal conductivity and are inexpensive, are being used in recent years. However, copper alloys are more susceptible to corrosion than conventional materials, and Cu 2 O, CuO
However, it has a drawback that it easily forms an oxide phase. Such an oxide phase has a problem in that it has poor adhesion to the material and peels off during the process to cause contact between the leads. In order to solve this, Japanese Patent Laid-Open No. 60-183758 discloses that a semiconductor package is manufactured by applying a copper plating of 1.0 μm or more on the entire surface of a lead frame and then performing a heating step such as die bonding or wire bonding. A method of doing so is disclosed.
【０００３】[0003]
【発明が解決しようとする課題】近年、電子機器の小型
化の要請に伴いＩＣ（半導体集積回路）の高密度化，寸
法の小型化及び薄型化が要求されるようになり、樹脂封
止型半導体パッケージもリードフレームのピン数の増加
及びピンの狭幅化が求められている。例えばピン数は８
０ピンから１６０ピンへ、さらに３００ピンへと増加し
ており、ピン幅も０.６５mmから０.５mmさらには０.３m
m へと狭幅化している。ところで、半導体パッケージを
回路基板に半田を用いて実装する際には、リードフレー
ムのアウターリード部に半田めっきをして、半田のぬれ
性を向上させた後、半田付けを行う。発明者らは、従来
のＦｅ−Ｎｉ系合金リードフレームと同様に、析出強化
型銅合金製のリードフレームに半田めっきを施した場
合、半田が異常成長して、隣り合うピン間でブリッジを
形成し、ショートすることがあるという事実を新たに見
い出した。ピン間の距離が大きい場合は、ブリッジは生
じにくく、ショートの問題はそれほど深刻ではなかった
が、ピンの狭幅化に伴い、ショートする可能性が大きく
なってきた。In recent years, along with the demand for miniaturization of electronic equipment, there has been a demand for higher density of ICs (semiconductor integrated circuits), miniaturization and thinning of dimensions. Semiconductor packages are also required to have an increased number of lead frame pins and a narrower pin width. For example, the number of pins is 8
The number of pins has increased from 0 pins to 160 pins, and further to 300 pins, and the pin width has increased from 0.65 mm to 0.5 mm and 0.3 m.
It narrows to m. By the way, when a semiconductor package is mounted on a circuit board using solder, soldering is performed after solder plating is applied to the outer lead portions of the lead frame to improve the wettability of the solder. Similar to the conventional Fe-Ni alloy lead frame, the inventors have found that when a lead frame made of a precipitation-strengthened copper alloy is subjected to solder plating, the solder abnormally grows to form a bridge between adjacent pins. Then, I found a new fact that there is a short circuit. When the distance between the pins is large, bridging is unlikely to occur, and the problem of short-circuiting was not so serious, but the possibility of short-circuiting has increased with the narrowing of the pins.
【０００４】本発明の目的は、銅合金製のリードフレー
ムを用いた半導体パッケージにおいて、半田めっき時に
ピン間にブリッジが発生しにくい半導体パッケージ及び
その製造方法を提供することにある。It is an object of the present invention to provide a semiconductor package using a lead frame made of a copper alloy, in which a bridge is less likely to occur between pins during solder plating, and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明の第１の発明によれば、半導体素子と該半導
体素子の電気信号を外部に導き出すリードフレームと、
前記半導体素子を外部環境より遮断する半導体封止手段
とを備えた半導体パッケージにおいて、前記リードフレ
ームが銅合金からなり、かつ該リードフレームのアウタ
ーリード部のみに、基材の銅合金表面に銅めっき膜が形
成され、更に該銅めっき膜は半田めっき膜により被覆さ
れている半導体パッケージが提供される。半導体封止手
段とは、例えば、樹脂，セラミックなどからなる封止材
料で半導体素子を封止するものである。アウターリード
部とは半導体封止手段の外側に出ているリードフレーム
の部分の名称であり、この部分のみに銅めっき膜が形成
される。半田めっき膜はこの銅めっき膜を覆うように施
される。上記構成により、銅めっき膜が半田めっき膜の
異常成長の起点となる酸化物粒子を覆うため、半田めっ
きの異常成長によるピン間のブリッジがなくなる。すな
わち、ピン間のショートが少なくなる。また、半田めっ
き膜がアウターリード部を覆っているので、銅合金リー
ド部の酸化防止効果により、半導体の信頼性向上が図れ
る。In order to achieve the above object, according to a first aspect of the present invention, a semiconductor element and a lead frame for guiding an electric signal of the semiconductor element to the outside,
In a semiconductor package provided with a semiconductor encapsulation means for shielding the semiconductor element from the external environment, the lead frame is made of a copper alloy, and only the outer lead portion of the lead frame is copper-plated on the copper alloy surface of the base material. A semiconductor package is provided in which a film is formed, and the copper plating film is covered with a solder plating film. The semiconductor encapsulation means encapsulates a semiconductor element with an encapsulating material such as resin or ceramic. The outer lead portion is the name of the portion of the lead frame protruding outside the semiconductor sealing means, and the copper plating film is formed only on this portion. The solder plating film is applied so as to cover the copper plating film. With the above configuration, since the copper plating film covers the oxide particles that are the origin of the abnormal growth of the solder plating film, there is no bridge between the pins due to the abnormal growth of the solder plating. That is, shorts between pins are reduced. Further, since the solder plating film covers the outer lead portion, the reliability of the semiconductor can be improved due to the oxidation preventing effect of the copper alloy lead portion.
【０００６】本発明の第２の発明によれば、第１の発明
において銅めっき膜の膜厚が０.５〜３μｍである半導
体パッケージが提供される。半田めっき膜の異常成長の
起点になる酸化物粒子は銅めっきを０.５ 〜３μｍの厚
さで施すことにより被覆され、半田の異常成長を抑制す
る効果が十分であることが後述の実施例で述べるように
確認された。上記膜厚の範囲より大きい、または小さい
場合でも、半田の異常成長を抑制する効果はあるが、よ
り好ましい範囲として上記範囲を規定するものである。
上記構成により、より効果的に半田の異常成長を抑制す
ることができ、半導体パッケージの信頼性を向上するこ
とができる。According to a second aspect of the present invention, there is provided a semiconductor package according to the first aspect, wherein the copper plating film has a thickness of 0.5 to 3 μm. The oxide particles, which are the origin of abnormal growth of the solder plating film, are coated by applying copper plating to a thickness of 0.5 to 3 μm, and the effect of suppressing the abnormal growth of solder is sufficient. Confirmed as described in. Even if the film thickness is larger or smaller than the above range, the abnormal growth of the solder can be suppressed, but the above range is defined as a more preferable range.
With the above configuration, abnormal growth of solder can be suppressed more effectively, and the reliability of the semiconductor package can be improved.
【０００７】本発明の第３の発明によれば、第１または
第２の発明において、銅合金が、Ｃｕ−Ｎｉ−Ｓｉ系、
またはＣｕ−Ｚｒ−Ｃｒ系の析出強化型銅合金である半
導体パッケージが提供される。銅合金は酸化物が生成し
やすい性質をもつが、それらは膜状の銅酸化物皮膜から
なる。しかし、上記析出強化型銅合金は、Ｓｉ，Ｚｒの
粒子状の酸化物が銅合金基材から析出するように生成す
る。このような粒子状の酸化物が特に半田の異常成長の
起点となりやすい。したがって、本発明は特に、上記析
出強化型合金からなるリードフレームに対して効果が高
い。一方、析出強化型合金は、熱伝導を低下させること
なく、強度を向上させた銅合金であるので、リードフレ
ーム素材としては、最も望ましいものである。したがっ
て、上記構成により、強度，熱伝導率の大きいリードフ
レームを有し、かつ半田めっき時にピン間にショート等
の不具合が生じない半導体パッケージが提供される。本
発明の第４の発明によれば、銅合金からなる薄板からリ
ードフレームの形状パターンを抜き出す工程と、抜き出
されたリードフレームに半導体素子を電気的に接続する
工程と、該半導体素子を外部雰囲気と遮断するための容
器に封止する工程と、前記リードフレームのアウターリ
ード部に銅めっきを施す工程と、該銅めっき上に半田め
っきを施す工程からなる半導体パッケージの製造方法が
提供される。半田めっき工程の直前に銅めっきを行うこ
とにより、リードフレーム基材上に生成する酸化物を効
果的に被覆できる。銅めっき工程と半田めっき工程の間
に、ワイヤボンディング等の工程が入ると、その間に酸
化物の生成，成長が起こる可能性がある。したがって、
半田めっきが半田めっき工程は銅めっき工程の直後に行
うことが好ましい。上記構成により、半田の異常成長の
発生を抑制でき、信頼性の高い半導体パッケージが提供
できる。According to a third invention of the present invention, in the first or second invention, the copper alloy is a Cu--Ni--Si system,
Alternatively, a semiconductor package which is a Cu—Zr—Cr-based precipitation-strengthened copper alloy is provided. Copper alloys have the property of easily forming oxides, but they consist of a film of copper oxide film. However, the above precipitation-strengthened copper alloy is produced so that particulate oxides of Si and Zr are precipitated from the copper alloy base material. Such a particulate oxide is particularly likely to be a starting point for abnormal growth of solder. Therefore, the present invention is particularly effective for a lead frame made of the above precipitation strengthening alloy. On the other hand, the precipitation-strengthened alloy is a copper alloy having improved strength without lowering thermal conductivity, and is therefore the most desirable lead frame material. Therefore, with the above structure, it is possible to provide a semiconductor package which has a lead frame having high strength and high thermal conductivity and which does not cause a defect such as a short circuit between pins during solder plating. According to a fourth aspect of the present invention, a step of extracting a lead frame shape pattern from a thin plate made of a copper alloy, a step of electrically connecting a semiconductor element to the extracted lead frame, and a step of externally connecting the semiconductor element Provided is a method for manufacturing a semiconductor package, which includes a step of sealing in a container for shielding from an atmosphere, a step of plating an outer lead portion of the lead frame, and a step of plating a solder on the copper plating. . By performing copper plating immediately before the solder plating step, the oxide generated on the lead frame base material can be effectively covered. If a wire bonding process or the like is performed between the copper plating process and the solder plating process, the formation and growth of oxides may occur during the process. Therefore,
The solder plating is preferably performed immediately after the copper plating step in the solder plating step. With the above configuration, it is possible to suppress abnormal growth of solder and provide a highly reliable semiconductor package.
【０００８】[0008]
【発明の実施の形態】銅めっきと半田の関係を銅合金と
してＣｕ−Ｎｉ−Ｓｉ系合金を使用したときを例とし
て、図１，図２を用いて説明する。図２に示すように半
田めっきの前処理としてのエッチングにより偏析した素
材成分のＳｉが表面に露出し、酸化されて銅合金表面上
にＳｉ酸化物が生成される。次に電気半田めっき工程に
おいて、その酸化物の近傍に接触電位差あるいは絶縁抵
抗により局所的な電荷の集中が起こり、半田めっき膜に
突起が発生する。さらに突起部に電気めっきの電流集中
が生じ、半田が成長するものと考えられる。図１に示す
ようにエッチング後の銅合金表面上に銅めっき膜を０.
５ 〜３μｍの厚さで施し、半田めっきするとＳｉ酸化
物は被覆され半田の成長は生じない。ここで、銅めっき
膜厚を規定したのは０.５μｍ 以下ではＳｉ酸化物を被
覆するのに十分でなく、３μｍ以上では銅合金と半田の
界面にボイドが多数集まり、剥離が生じるためである。
また、半田の成長の起点となる酸化物はＳｉ以外にＺｒ
及びＡｇなどであり、これらの酸化物上に規定の厚さの
銅めっき膜を形成し、その上に半田めっきを施すことで
半田の成長を抑制できる。BEST MODE FOR CARRYING OUT THE INVENTION The relationship between copper plating and solder will be described with reference to FIGS. 1 and 2, taking as an example the case where a Cu—Ni—Si alloy is used as the copper alloy. As shown in FIG. 2, the material component Si segregated by etching as a pretreatment for solder plating is exposed on the surface and is oxidized to produce Si oxide on the surface of the copper alloy. Next, in the electric solder plating step, local concentration of electric charges occurs due to a contact potential difference or insulation resistance in the vicinity of the oxide, and a protrusion is generated on the solder plating film. Further, it is considered that the electric current concentration of the electroplating occurs on the protrusion and the solder grows. As shown in Fig. 1, a copper plating film was formed on the surface of the copper alloy after the etching.
When applied with a thickness of 5 to 3 μm and solder-plated, the Si oxide is covered and solder growth does not occur. Here, the copper plating film thickness is specified because if it is 0.5 μm or less, it is not enough to cover the Si oxide, and if it is 3 μm or more, many voids are collected at the interface between the copper alloy and the solder, and peeling occurs. .
In addition to Si, the oxide that becomes the starting point of solder growth is Zr.
It is possible to suppress the growth of solder by forming a copper plating film of a prescribed thickness on these oxides and Ag and solder plating on the copper plating film.
【０００９】以上のように、銅合金、特に析出強化型銅
合金と半田めっきの間に酸化物を被覆する規定の厚さの
銅めっき膜を設けることが本発明の基本的概念である
が、酸化物の被覆に必要な膜厚は対象物の条件によって
異なる。本発明において、銅めっきの膜厚が銅合金上に
析出したＳｉ，Ｚｒ及びＡｇ酸化物の粒径を１μｍ以下
に抑制できる膜厚であれば半田めっきの成長は抑制でき
ることを確認した。As described above, it is a basic concept of the present invention to provide a copper plating film having a specified thickness for coating an oxide between the copper alloy, particularly the precipitation strengthening copper alloy and the solder plating. The film thickness required for the oxide coating depends on the conditions of the object. In the present invention, it was confirmed that the growth of solder plating can be suppressed as long as the thickness of the copper plating is such that the grain size of Si, Zr and Ag oxides deposited on the copper alloy can be suppressed to 1 μm or less.
【００１０】次に本発明を実施例により、説明する。Next, the present invention will be described with reference to examples.
【００１１】（実施例１）半導体装置のリードフレーム
素材（Ｃｕ−Ｎｉ−Ｓｉ系銅合金）に半田めっき前処理
として通常のエッチング条件（常温、１０％硫酸溶液中
で３０秒浸漬→１０％過酸化水素と１０％硝酸の混合液
中で６０秒浸漬）でエッチングを行い、その後、表１に
示す条件で電気銅めっきを施し、その上にＳｎ／５Ｐｂ
半田をめっき条件（常温、電流密度１Ａ／cm2 ）で、リ
ードフレームとして所定の厚さになるまで電気半田めっ
きした。その後、半田めっきの状況を目視観察し、結果
を表１に○×で示す。(Example 1) As a solder plating pretreatment for a lead frame material (Cu-Ni-Si-based copper alloy) of a semiconductor device, a usual etching condition (normal temperature, 10% dipping in a 10% sulfuric acid solution for 30 seconds → 10% excess) was used. Etching is performed in a mixed solution of hydrogen oxide and 10% nitric acid for 60 seconds), and then electrolytic copper plating is performed under the conditions shown in Table 1, and Sn / 5Pb is applied on the copper plating.
The solder was electro-solder plated under the plating conditions (normal temperature, current density 1 A / cm 2 ) to a predetermined thickness as a lead frame. Then, the condition of solder plating was visually observed, and the results are shown in Table 1 by ◯ ×.
【００１２】[0012]
【表１】 [Table 1]
【００１３】表１には半田の剥離試験の結果も併記し
た。この結果で示されるように、半田の成長の生じない
銅めっきの膜厚は０.５μｍ 以上であった。また、銅め
っきの膜厚が３μｍを超えると銅合金素材と半田の界面
から剥離した。したがって、半田めっきの成長を防止で
き、かつ界面の密着強度の低下しない銅めっきの膜厚は
０.５ 〜３μｍの範囲であると判断した。なお、銅めっ
きの膜厚の測定はサンプルを樹脂に埋め込み断面研摩
後、走査型電子顕微鏡写真により判定した。図３は本発
明の１実施例になる半導体装置の断面図（ａ）と斜視図
（ｂ）である。Ｃｕ−Ｎｉ−Ｓｉ系銅合金のアウターリ
ード部６に前述の銅めっき膜２が形成され、更にその上
に半田めっき膜３が形成されている。リードフレーム１
の半導体素子搭載部４に半田８で半導体素子７を半田付
けし、半導体素子上のＡｌ電極とインナーリード部５に
部分Ａｇめっき１１を施し、その間をＡｕワイヤ９でボ
ンディングしてエポキシ樹脂１０で封止した。Ａｇめっ
きはマスキングしてボンディング部分のみに形成するよ
うにした。また、このＡｇめっきを施さないでボンディ
ングしたものも行った。アウターリード部に銅めっき膜
を介在させて半田めっきすることにより、これらの半田
の成長は抑制された。Table 1 also shows the results of the solder peeling test. As shown in this result, the film thickness of the copper plating in which solder growth did not occur was 0.5 μm or more. Moreover, when the film thickness of the copper plating exceeded 3 μm, it was peeled from the interface between the copper alloy material and the solder. Therefore, it was judged that the film thickness of the copper plating that can prevent the growth of the solder plating and that does not reduce the adhesion strength at the interface is in the range of 0.5 to 3 μm. The film thickness of the copper plating was measured by embedding the sample in a resin, polishing the cross section, and then determining the film thickness with a scanning electron microscope photograph. FIG. 3 is a sectional view (a) and a perspective view (b) of a semiconductor device according to an embodiment of the present invention. The above-mentioned copper plating film 2 is formed on the outer lead portion 6 of the Cu-Ni-Si-based copper alloy, and the solder plating film 3 is further formed thereon. Lead frame 1
The semiconductor element 7 is soldered to the semiconductor element mounting portion 4 with the solder 8 and the Ag electrode 11 on the semiconductor element and the inner lead portion 5 are partially Ag-plated 11, and the portion between them is bonded with the Au wire 9 and the epoxy resin 10. Sealed. The Ag plating was masked so that it was formed only on the bonding portion. Further, the bonding without the Ag plating was also performed. The growth of these solders was suppressed by solder-plating the outer lead portion with a copper plating film interposed.
【００１４】表２はＣｕ−Ｚｒ−Ｃｒ系銅合金につい
て、前述と同様にエッチング，銅めっき及び半田めっき
を行い、半田めっきの状況を目視観察した結果である。Table 2 shows the results of visually observing the state of the solder plating by performing etching, copper plating and solder plating on the Cu-Zr-Cr type copper alloy in the same manner as described above.
【００１５】[0015]
【表２】 [Table 2]
【００１６】Ｃｕ−Ｎｉ−Ｓｉ系銅合金と同じように、
半田めっきの成長を防止でき、かつ界面の密着強度の低
下しない銅めっきの膜厚は０.５ 〜３μｍの範囲であ
る。図４はＣｕ−Ｚｒ−Ｃｒ系銅合金のアウターリード
部６に本発明の銅めっき膜２を形成して更にその上に半
田めっき膜３を形成した半導体装置の断面図である。半
導体素子７をリードフレーム１の半導体素子搭載部４に
半田付けし、インナーリード部５と半導体素子搭載部４
のみに部分的にＡｇめっき１１を施した後、金属ワイヤ
９でワイヤボンディングしエポキシ樹脂１０で封止し
た。また、このＡｇめっきを施さないでボンディングし
たものも行った。アウターリード部に銅めっきを介在さ
せて半田めっきすることにより、これらの半田の成長は
抑制された。なお、半田が成長したリードフレームを解
析した結果、Ｃｕ−Ｎｉ−Ｓｉ系及びＣｕ−Ｚｒ−Ｃｒ
系とも成長の起点部にＳｉ酸化物及びＺｒ酸化物が存在
することを確認した。また、部分Ａｇめっきが施された
リードフレームでは、脱Ａｇ処理（洗浄）が不十分でア
ウターリード部にＡｇが残ったものには半田の成長が起
こり、Ａｇ酸化物から半田が成長していることをもわか
った。以上のことから、アウターリード部に銅めっきを
介在させて半田めっきすることにより、半田の成長が防
止できる。Like the Cu-Ni-Si-based copper alloy,
The film thickness of the copper plating that can prevent the growth of the solder plating and does not reduce the adhesion strength at the interface is in the range of 0.5 to 3 μm. FIG. 4 is a sectional view of a semiconductor device in which a copper plating film 2 of the present invention is formed on an outer lead portion 6 of a Cu—Zr—Cr-based copper alloy, and a solder plating film 3 is further formed thereon. The semiconductor element 7 is soldered to the semiconductor element mounting portion 4 of the lead frame 1, and the inner lead portion 5 and the semiconductor element mounting portion 4 are soldered.
After the Ag plating 11 was partially applied to only the part, wire bonding was performed with the metal wire 9 and the epoxy resin 10 was used for sealing. Further, the bonding without the Ag plating was also performed. The growth of these solders was suppressed by solder-plating the outer lead portion with copper plating interposed. As a result of analyzing the lead frame on which the solder has grown, Cu-Ni-Si system and Cu-Zr-Cr
It was confirmed that Si oxide and Zr oxide were present at the starting point of growth in both systems. Further, in the lead frame which is partially Ag-plated, solder growth occurs in the lead frame where Ag removal (cleaning) is insufficient and Ag remains in the outer lead portion, and solder is grown from Ag oxide. I also understood that. From the above, solder growth can be prevented by solder plating with copper plating interposed in the outer lead portion.
【００１７】（実施例２）図５は実施例１と同様に実験
し、Ｃｕ−Ｎｉ−Ｓｉ系銅合金に生じたＳｉ酸化物の粒
径と半田めっきの不良発生率の関係を調べた結果であ
る。図から、Ｓｉ酸化物の粒径が１μｍを超えると不良
が発生することがわかる。このことは、リードフレーム
上のＳｉ酸化物の粒径を１μｍ以下に抑えれば半田の成
長は抑制できることを示している。この結果はＣｕ−Ｚ
ｒ−Ｃｕ系銅合金でも同様であった。すなわち、半導体
パッケージ用リードフレームとしてアウターリード部に
銅めっき膜を有し、リードフレームの表面上に露出する
酸化物の粒径を１μｍ以下とする膜厚であれば半田の成
長は抑制できる。図６は本発明のリードフレームの一例
を示す平面図である。本実施例のリードフレームは実施
例１と同じＣｕ−Ｎｉ−Ｓｉ系の銅合金で０.３mm の厚
さを有するものである。このリードフレームは複数のチ
ップを搭載できるように形成され、チップ搭載，ワイヤ
ボンディング等自動的に行えるよう送り機構１３が設け
られている。本実施例は半導体素子搭載部４，インナー
リード部５に部分Ａｇめっきを有するものであり、樹脂
封止後に脱Ａｇ処理を行ったものである。アウターリー
ド部に残存したＡｇ酸化物の粒径を１μｍ以下とする銅
めっき膜を介在させて半田めっきすることにより、半田
の成長は抑制された。(Embodiment 2) FIG. 5 is a result of conducting an experiment in the same manner as in Embodiment 1 and examining the relationship between the grain size of the Si oxide generated in the Cu-Ni-Si-based copper alloy and the defective rate of solder plating. Is. From the figure, it can be seen that defects occur when the particle diameter of the Si oxide exceeds 1 μm. This indicates that the growth of solder can be suppressed if the particle size of the Si oxide on the lead frame is suppressed to 1 μm or less. This result is Cu-Z
The same was true for the r-Cu-based copper alloy. That is, the growth of solder can be suppressed as long as the outer lead portion has a copper plating film as a lead frame for a semiconductor package and the thickness of the oxide exposed on the surface of the lead frame is 1 μm or less. FIG. 6 is a plan view showing an example of the lead frame of the present invention. The lead frame of this embodiment is the same Cu-Ni-Si-based copper alloy as in Embodiment 1 and has a thickness of 0.3 mm. This lead frame is formed so that a plurality of chips can be mounted, and a feed mechanism 13 is provided so that chip mounting and wire bonding can be automatically performed. In this embodiment, the semiconductor element mounting portion 4 and the inner lead portion 5 have a partial Ag plating, and the Ag removal treatment is performed after the resin sealing. The growth of solder was suppressed by solder plating with a copper plating film having a particle diameter of Ag oxide remaining in the outer lead portion of 1 μm or less interposed.
【００１８】（実施例３）図７は本発明の実施例の工程
を説明するフローチャートである。本図に示すように通
常の半導体パッケージ製造工程にしたがって、半導体素
子と銅合金リードフレームとを樹脂封止する樹脂封止工
程及びリードフレームのアウターリード部をエッチング
する前処理工程を経た後、アウターリード部に０.５ 〜
３μｍの厚さの銅めっき膜を形成するめっき工程を設け
る。その後、アウターリード部を半田めっきする工程に
進み、半導体製品となる。さらに、本発明の他の実施例
としてリードフレームのアウターリード部をエッチング
する前処理工程において、エッチング量をアウターリー
ド部の表面上に析出する各種酸化物の粒径を１μｍ以下
とするエッチング条件とする半導体パッケージの製造工
程である。本実施例では銅めっき膜を形成せずに半田の
成長を抑制できる。(Embodiment 3) FIG. 7 is a flow chart for explaining the steps of the embodiment of the present invention. As shown in the figure, according to a normal semiconductor package manufacturing process, after undergoing a resin sealing process of resin-sealing a semiconductor element and a copper alloy lead frame and a pretreatment process of etching outer lead portions of the lead frame, the outer 0.5 to the lead
A plating step for forming a copper plating film having a thickness of 3 μm is provided. After that, the process proceeds to the step of solder-plating the outer lead portion, and a semiconductor product is obtained. Further, as another embodiment of the present invention, in the pretreatment step of etching the outer lead portion of the lead frame, the etching amount is such that the particle size of various oxides deposited on the surface of the outer lead portion is 1 μm or less. Is a semiconductor package manufacturing process. In this embodiment, the growth of solder can be suppressed without forming a copper plating film.
【００１９】なお、本実施例以外の銅合金に本発明を適
用しても、同等の効果を得ることができる。Even if the present invention is applied to a copper alloy other than this embodiment, the same effect can be obtained.
【００２０】[0020]
【発明の効果】本発明の第１の発明によれば、半田めっ
きの異常成長によるピン間のブリッジがなくなる。すな
わち、ピン間のショートが少なくなる。また、半田めっ
き膜がアウターリード部を覆っているので、銅合金リー
ド部の酸化防止効果により、半導体の信頼性向上が図れ
る。According to the first aspect of the present invention, there is no bridge between pins due to abnormal growth of solder plating. That is, shorts between pins are reduced. Further, since the solder plating film covers the outer lead portion, the reliability of the semiconductor can be improved due to the oxidation preventing effect of the copper alloy lead portion.
【００２１】本発明の第２の発明によれば、より効果的
に半田の異常成長を抑制することができ、半導体パッケ
ージの信頼性を向上することができる。According to the second aspect of the present invention, abnormal growth of solder can be suppressed more effectively, and the reliability of the semiconductor package can be improved.
【００２２】本発明の第３の発明によれば、強度，熱伝
導率の大きいリードフレームを有し、かつ半田めっき時
にピン間にショート等の不具合が生じない半導体パッケ
ージが提供される。According to the third aspect of the present invention, there is provided a semiconductor package which has a lead frame having high strength and high thermal conductivity and which does not cause a short-circuit between pins during solder plating.
【００２３】本発明の第４の発明によれば、半田の異常
成長の発生を抑制でき、信頼性の高い半導体パッケージ
が提供できる。According to the fourth aspect of the present invention, it is possible to provide a highly reliable semiconductor package which can suppress the abnormal growth of solder.
【図１】本発明の素材上のめっき構成の一例を示す説明
図。FIG. 1 is an explanatory diagram showing an example of a plating configuration on a material of the present invention.
【図２】従来の電気半田めっきでの半田成長状態を推定
したモデル図。FIG. 2 is a model diagram in which a solder growth state in conventional electric solder plating is estimated.
【図３】本発明の半導体パッケージの断面図（ａ）及び
斜視図（ｂ）。FIG. 3 is a sectional view (a) and a perspective view (b) of a semiconductor package of the present invention.
【図４】本発明の半導体パッケージの断面図。FIG. 4 is a sectional view of a semiconductor package of the present invention.
【図５】本発明の実施例のリードフレーム上のＳｉ酸化
物粒径と半田めっき不良率との関係を表わす図。FIG. 5 is a diagram showing a relationship between a particle size of Si oxide on a lead frame and a defective rate of solder plating according to an example of the present invention.
【図６】本発明のリードフレーム板の斜視図。FIG. 6 is a perspective view of a lead frame plate of the present invention.
【図７】本発明の実施例の製造工程を説明するフローチ
ャート。FIG. 7 is a flowchart illustrating a manufacturing process according to an embodiment of the present invention.
１…リードフレーム、２…銅めっき膜、３…半田めっき
膜、４…半導体素子搭載部、５…インナーリード部、６
…アウターリード部、７…半導体素子、８…半田、９…
金属ワイヤ、１０…樹脂、１１…Ａｇめっき、１２…リ
ードフレーム、１３…送り機構。DESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... Copper plating film, 3 ... Solder plating film, 4 ... Semiconductor element mounting part, 5 ... Inner lead part, 6
... outer lead part, 7 ... semiconductor element, 8 ... solder, 9 ...
Metal wire, 10 ... Resin, 11 ... Ag plating, 12 ... Lead frame, 13 ... Feed mechanism.
Claims (4)
部に導き出すリードフレームと、前記半導体素子と外部
環境より遮断する半導体封止手段とを備えた半導体パッ
ケージにおいて、 前記リードフレームが銅合金からなり、かつ該リードフ
レームのアウターリード部のみに、基材の銅合金表面に
銅めっき膜が形成され、更に該銅めっき膜は半田めっき
膜により被覆されていることを特徴とする半導体パッケ
ージ。1. A semiconductor package comprising a semiconductor element, a lead frame for guiding an electric signal of the semiconductor element to the outside, and a semiconductor encapsulation means for shielding the semiconductor element from the external environment, wherein the lead frame is made of a copper alloy. And a copper plating film is formed on the copper alloy surface of the base material only on the outer lead portions of the lead frame, and the copper plating film is covered with a solder plating film.
〜３μｍであることを特徴とする半導体パッケージ。2. The film thickness of the copper plating film according to claim 1 is 0.5.
A semiconductor package having a thickness of 3 μm.
Ｎｉ−Ｓｉ系、またはＣｕ−Ｚｒ−Ｃｒ系の析出強化型
銅合金であることを特徴とする半導体パッケージ。3. The copper alloy according to claim 1 is Cu-
A semiconductor package, which is a precipitation-strengthened copper alloy of Ni-Si system or Cu-Zr-Cr system.
形状パターンを抜き出す工程と、抜き出されたリードフ
レームに半導体素子を電気的に接続する工程と、該半導
体素子を外部雰囲気と遮断するための容器に封止する工
程と、前記リードフレームのアウターリード部に銅めっ
きを施す工程と、該銅めっき上に半田めっきを施す工程
からなることを特徴とする半導体パッケージの製造方
法。4. A step of extracting a shape pattern of a lead frame from a thin plate made of a copper alloy, a step of electrically connecting a semiconductor element to the extracted lead frame, and a step of isolating the semiconductor element from an external atmosphere. A method of manufacturing a semiconductor package, comprising: a step of sealing in a container; a step of plating the outer lead portion of the lead frame with copper; and a step of plating solder on the copper plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14888196A JPH09331015A (en) | 1996-06-11 | 1996-06-11 | Semiconductor package and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14888196A JPH09331015A (en) | 1996-06-11 | 1996-06-11 | Semiconductor package and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09331015A true JPH09331015A (en) | 1997-12-22 |
Family
ID=15462813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14888196A Pending JPH09331015A (en) | 1996-06-11 | 1996-06-11 | Semiconductor package and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09331015A (en) |
-
1996
- 1996-06-11 JP JP14888196A patent/JPH09331015A/en active Pending
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