JPS62150754A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS62150754A JPS62150754A JP60290509A JP29050985A JPS62150754A JP S62150754 A JPS62150754 A JP S62150754A JP 60290509 A JP60290509 A JP 60290509A JP 29050985 A JP29050985 A JP 29050985A JP S62150754 A JPS62150754 A JP S62150754A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- post
- plating film
- compressed
- plated copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、電子装置、特に、その基板になるリードフレ
ームの改良に関し、例えば、ミニ・樹脂封止型パッケー
ジを備えているトランジスタ（以下、ミニモールド型ト
ランジスタという。）に利用して有効なものに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an electronic device, and particularly to an improvement in a lead frame serving as a substrate thereof. (referred to as transistors).
金銀の消費を節約しつつ導電性を確保するミニモールド
型トランジスタとして、４２７０イの素材全面に銅（Ｃ
ｕ）めっき被膜を被着されているリードフレームを使用
したものが考えられる。As a mini-mold type transistor that saves gold and silver consumption while ensuring conductivity, copper (C) is used on the entire surface of the 4270I material.
u) One that uses a lead frame covered with a plating film can be considered.
しかし、このようなミニモールド型トランジスタにおい
ては、パッケージの外縁部におけるアウタリードとパッ
ケージとの界面の接着強度が弱いため、環境試験におい
て耐湿性の弱いものが発見されるという問題点があるこ
とが、本発明者によって明らかにされた。However, in such mini-mold type transistors, the adhesive strength at the interface between the outer lead and the package at the outer edge of the package is weak, so there is a problem that some transistors with weak moisture resistance are found in environmental tests. revealed by the inventor.
なお、樹脂封止技術を述べである例としては、株式会社
工業調査会発行ｒｌｃ化実装技術」昭和５５年１１月１
５日発行 Ｐ１３５〜Ｐ１５０、がある。An example of resin encapsulation technology is "RLC Mounting Technology" published by Kogyo Kenkyukai Co., Ltd., November 1, 1980.
Issued on the 5th, prices range from P135 to P150.
本発明の目的は、耐湿性を向上することができる電子装
置を提供することにある。An object of the present invention is to provide an electronic device that can improve moisture resistance.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
リードフレーム上に金属としての銅をめっき処理等によ
り被着した後、この被膜の少なくともパッケージの外縁
部に対応する部分を圧縮することにより、パンケージの
外縁部におけるアウタリードとパッケージとの界面の接
着強度を高めるようにして耐湿性を向上させるようにし
たものである。After depositing copper as a metal on the lead frame by plating, etc., by compressing at least the portion of this coating that corresponds to the outer edge of the package, the adhesive strength of the interface between the outer lead and the package at the outer edge of the pancage is increased. The moisture resistance is improved by increasing the moisture resistance.
〔実施例１〕
第１図は本発明の一実施例であるミニモールド型トラン
ジスタを示す幡断面図、第２図はそれに使用されるリー
ドフレームを示す斜視図、第３図は作用を説明するため
の他のミニモールド型トランジスタを示す縦断面図であ
る。[Embodiment 1] Fig. 1 is a cross-sectional view showing a mini-mold type transistor which is an embodiment of the present invention, Fig. 2 is a perspective view showing a lead frame used therein, and Fig. 3 explains the operation. FIG. 4 is a vertical cross-sectional view showing another mini-mold type transistor for use in the present invention.
本実施例において、電子装置としてのミニモールド型ト
ランジスタｌには第２図に示されているようなリードフ
レーム２が使用されている。リードフレーム２は外枠３
と、外枠３に交互に配されて内向きにそれぞれ突設され
ている３本のアウタリード４Ａ、４Ｂ、４Ｃと、各アウ
タリードの先端部にそれぞれ一体的に形成されているコ
レクタポスト５Ａ、エミッタポスト５Ｂ、ベースポスト
５Ｃとを備えている、図示は省略するが、リードフレー
ム２はその原形において３本のアウタリードを一単位と
して一方向に連続した形態に形成されている。In this embodiment, a lead frame 2 as shown in FIG. 2 is used for a mini-mold transistor l as an electronic device. Lead frame 2 is outer frame 3
, three outer leads 4A, 4B, and 4C that are alternately arranged on the outer frame 3 and protrude inward, and a collector post 5A and an emitter that are integrally formed at the tip of each outer lead. Although not shown in the drawings, the lead frame 2 includes a post 5B and a base post 5C, but in its original form, the lead frame 2 is formed so as to be continuous in one direction with three outer leads as one unit.
このリードフレーム２は薄板に打ち抜きプレス加工等を
実施して一体成形されており、その母材６としては４２
７０イの薄板が使用されている。This lead frame 2 is integrally formed by punching and pressing a thin plate, and the base material 6 is 42 mm.
A thin plate of 70 i is used.
母材６の表面上には金属被膜としての銅めっき被膜７が
全体的に被着されているとともに、銅めっき被膜７を圧
縮加工されてなる被圧縮部８が各アウタリード４Ａ、ｊ
Ｂ、４Ｃに形成されている。A copper plating film 7 as a metal film is entirely deposited on the surface of the base material 6, and a compressed portion 8 formed by compressing the copper plating film 7 is attached to each outer lead 4A, j.
It is formed in B and 4C.
コレクタボスト５Ａには銅めっき被膜７上にペレット９
がボンディングされており、エミッタポスト５Ｂおよび
ベースポスト５Ｃには銅めっき被膜７上に、ボンディン
グワイヤ１０の一端がそれぞれボンディングされている
。そして、ペレット９は電極パッドにワイヤ１０の他端
をそれぞれボンディングされることによりアウタリード
４Ｂ。The collector post 5A has pellets 9 on the copper plating film 7.
are bonded to each other, and one end of a bonding wire 10 is bonded to the copper plating film 7 on the emitter post 5B and the base post 5C, respectively. The pellet 9 forms an outer lead 4B by bonding the other end of the wire 10 to the electrode pad.
４Ｃに電気的に接続されている。各ポスト５Ａ。It is electrically connected to 4C. Each post 5A.
５Ｂ、５Ｃにペレット９およびワイヤ１０の一端がそれ
ぞれボンディングされる際、各ポストには銅めっき被膜
７の表面が残されて露出されているため、そのボンダビ
リティ−は良好になり、優れたボンディング状態が得ら
れることになる。When the pellet 9 and one end of the wire 10 are bonded to 5B and 5C, the surface of the copper plating film 7 is left exposed on each post, resulting in good bondability and excellent bonding. The state will be obtained.
リードフレーム２に搭載されたペレット９およびこれに
接続されたボンディングワイヤ１０は樹脂を」いてトラ
ンスファ成形法等のような適当な手段によって一体成形
されてなるパッケージ１１により、非気密封止される。The pellet 9 mounted on the lead frame 2 and the bonding wire 10 connected thereto are non-hermetically sealed by a package 11 which is formed integrally with resin by a suitable means such as transfer molding.
この状態において、各ポスト５Ａ、５Ｂ、５Ｃ上に被着
された銅めっき被膜７の被圧縮部８との境界である段差
部７ａはパッケージ１１の外縁よりも十分に内側に入っ
た位置にある。バフケージ１１から外へ突出したアウタ
リード４Ａ、４Ｂ、４Ｃはパッケージ１１の近傍位置に
おいて略直角下向きに屈曲されるとともに、その下端に
おいて外枠３から切り離される。In this state, the stepped portion 7a, which is the boundary between the copper plating film 7 deposited on each post 5A, 5B, and 5C and the compressed portion 8, is located sufficiently inside the outer edge of the package 11. . The outer leads 4A, 4B, and 4C protruding outward from the buff cage 11 are bent downward at a substantially right angle at a position near the package 11, and are separated from the outer frame 3 at their lower ends.
ここで、前記構成にかかるリードフレームの製造方法の
一実施例を説明する。Here, one embodiment of a method for manufacturing a lead frame according to the above structure will be described.
まず、母材である４２アロイの薄板に導体金属被膜とし
ての銅めっき被膜が銅を用いて電解めっき処理等のよう
な適当な手段により被着される。First, a copper plating film as a conductive metal film is applied to a thin plate of 42 alloy, which is a base material, using copper by an appropriate means such as electrolytic plating.
続いて、銅めっき被膜が被着された薄板につき、一部を
残して圧延加工が実施され、所定の部分には銅めっき処
理されたままの表面が残される。Subsequently, the thin plate coated with the copper plating film is rolled, leaving only a portion of the thin plate, leaving the copper-plated surface in a predetermined portion.
その後、銅めっき処理され、かつ、圧延加工された薄板
は打ち抜きプレス加工によりリードフレ−ムの形態に一
体成形される。このとき、薄板の上面に圧延し残された
洞めっき被膜自体の表面にコレクタボスト、エミッタボ
ストおよびヘースボストが整合するように、打ら凄きプ
レス加工が実施される。Thereafter, the copper-plated and rolled thin plate is integrally formed into a lead frame by punching and pressing. At this time, deep pressing is performed so that the collector post, emitter post, and heath post are aligned with the surface of the hollow plating film itself left after rolling on the upper surface of the thin plate.
このようにして成形されたリードフレームはトリクロー
ル溶剤等のような有機溶剤により洗浄されて脂肪等の汚
染物が除去される。The lead frame formed in this manner is cleaned with an organic solvent such as trichlorosolvent to remove contaminants such as fat.
次に作用を説明する。Next, the effect will be explained.
前記構成にかかるミニモールド型トランジスタは品質保
証のため出荷前に抜き取り検査を実施される。この抜き
炊り検査としては、熱衝撃試験やプレノシャクソカ試験
等のような環境試験が実施される。 ところで、第３図
に示されているように、銅のめっき被膜２３を全面に被
着されているリードフレーム２２を用いたミニモールド
型トランジスタ２１は、溶融はんだを熱媒に用いたｐ！
術ａ！試験を実施した後、プレッシャクソカ試験を実施
すると、耐湿性不良が発見される。これは次のｉｌ、
） １’ ｊ’ｌ；’山によると考えられる。The mini-mold type transistor according to the above configuration is subjected to a sampling inspection before shipping for quality assurance. As this surprise inspection, an environmental test such as a thermal shock test or a pre-no-shock test is conducted. By the way, as shown in FIG. 3, a mini-mold type transistor 21 using a lead frame 22 whose entire surface is coated with a copper plating film 23 is a p!
Jutsu a! After conducting the test, when a pressure crack test is performed, poor moisture resistance is discovered. This is the next il,
) 1'j'l;'It is thought that it depends on the mountain.
すなわち、銅めっき被膜は酸化され易く、かつ、この酸
化物はもろ＜ ！ＩＩＩがれ易いため、樹脂パッケージ
２４の外縁部における銅めっき被膜２３とパッケージ２
４との接着強度は銅めっき被膜２３の表面の銅酸化物の
存在により弱くなっている。さらに、銅の酸化物は塩酸
Ｄｌｃｌ）等のような強酸によりイオン化され易いため
、はんだ浸漬前における塩酸による前処理時において、
銅めっき被膜２３表面の銅酸化物は溶け、パッケージ２
４との接着強度は一層弱くなる。In other words, the copper plating film is easily oxidized, and this oxide is easily oxidized. III Because it is easy to peel off, the copper plating film 23 on the outer edge of the resin package 24 and the package 2
4 is weakened by the presence of copper oxide on the surface of the copper plating film 23. Furthermore, since copper oxides are easily ionized by strong acids such as hydrochloric acid (Dlcl), during pretreatment with hydrochloric acid before soldering,
The copper oxide on the surface of the copper plating film 23 melts and the package 2
The adhesive strength with 4 becomes even weaker.
このような状態において、溶融はんだ中に浸漬されると
、熱衝撃により、銅のめっき被膜２３とパッケージ２４
との界面に隙間が発生する。In such a state, when immersed in molten solder, the copper plating film 23 and the package 24 will be damaged due to thermal shock.
A gap occurs at the interface with the
その後、プレッシャクソ力試験が実施されると、銅めっ
き被膜２３とパンケージ２４との界面に発生した隙間か
ら水分が浸入するため、耐湿性不良が発生する。また、
ＰＡｒｙ！処理時に発生した銅イオンが銅めっき被膜２
３表面を通じてペレット９に達し、ペレットにおけるア
ルミニューム配線を腐食させるため、断線、短絡、絶縁
不良等のような電気的不良が招来されることになる。After that, when a pressure force test is performed, moisture infiltrates through the gap created at the interface between the copper plating film 23 and the pan cage 24, resulting in poor moisture resistance. Also,
PAry! Copper ions generated during processing form copper plating film 2.
The aluminum wires reach the pellet 9 through the surface of the pellet 9 and corrode the aluminum wiring in the pellet, resulting in electrical defects such as disconnections, short circuits, and poor insulation.
しかし、本実施例においては、パッケージ１１の外縁部
においては銅めっき被膜７を圧延されて被圧縮部８が形
成されており、銅めっき被膜７の表面はリードフレーム
のパッケージの内側部分においてのみ部分的に形成され
ているため、耐湿性不良は発生しない。However, in this embodiment, the copper plating film 7 is rolled at the outer edge of the package 11 to form the compressed part 8, and the surface of the copper plating film 7 is partially formed only at the inner part of the package of the lead frame. Since it is formed in a uniform manner, moisture resistance defects will not occur.
すなわち、銅めっき被膜７の表面はパフケージ１１の内
部に封止されており、ノｉソケージ１１の外縁部に対応
する各アろタリード４Ａ、４Ｂ、４Ｃにおいては被圧縮
部８の表面のみが樹脂と接触している。そして、この被
圧縮部８は酸化されにくいし、酸化されても剥がれに＜
＜、かつ、塩酸による前処理時において熔けにくい。こ
れは次のような理由によると考えられる。That is, the surface of the copper plating film 7 is sealed inside the puff cage 11, and only the surface of the compressed portion 8 of each of the rotary leads 4A, 4B, and 4C corresponding to the outer edge of the insulation cage 11 is sealed with resin. is in contact with. This compressed part 8 is not easily oxidized, and even if it is oxidized, it will not peel off.
< and is difficult to melt during pretreatment with hydrochloric acid. This is thought to be due to the following reasons.
めっき処理されたままの銅めっき被膜は表面が粗く表面
積が無限大になり、かつ、結晶粒の密度が粗で活性程度
が強い。これに対して、銅めっき被膜７を圧延された被
圧縮部８は表面が押し潰さた、結晶粒の配列が整えられ
るため、活性程度は弱まる。The copper plating film that has been plated has a rough surface and an infinite surface area, and the density of crystal grains is coarse and the degree of activity is high. On the other hand, since the surface of the compressed part 8 where the copper plating film 7 is rolled is crushed and the crystal grains are arranged, the degree of activity is weakened.
したがって、各アウタリード４Ａ、４Ｂ、４Ｃのパッケ
ージ１１の外縁部に対する接着強度は所期の強さが維持
されることになる。その結果、このミニモールド型トラ
ンジスタ１が溶融はんだ中に？’ｘ ？Ｒされて熱衝撃
が加えられても、アウタリード４Ａ、４Ｂ、４Ｃとパッ
ケージ９との界面に隙間が発生することはない。Therefore, the adhesive strength of each outer lead 4A, 4B, 4C to the outer edge of the package 11 is maintained at the desired strength. As a result, this mini-mold type transistor 1 is placed in molten solder? 'x? Even if thermal shock is applied to the outer leads 4A, 4B, and 4C, no gaps will be generated at the interfaces between the outer leads 4A, 4B, and 4C and the package 9.
かくして、その後のプレッソヤクッカ試験において隙間
から水分が浸入してしまうという現象は回避されるため
、耐湿性不良が発生することはない。万一、アウタリー
ドに沿って水分が浸入したとしても、水は銅めっき被膜
７の外縁における被圧縮部８と境目である段差部７ａで
せき止められることにより、ないしは、浸入経路を長く
されることにより、それ以上内部に浸入されることを抑
止ないしは抑制されるため、ペレット９が９に９を受け
ることはない。In this way, the phenomenon of moisture infiltrating through the gaps in the subsequent presso yacooker test is avoided, so that moisture resistance failure does not occur. Even if moisture infiltrates along the outer lead, the water will be dammed up at the stepped portion 7a that borders the compressed portion 8 at the outer edge of the copper plating film 7, or the infiltration path will be lengthened. Since the pellets 9 are prevented from being penetrated further into the inside, the pellets 9 are not affected by the pellets 9.
：＃ト９０熟−さ）両■凸７ｒ十富】口１、アいＲいト
め、塩酸処理時に銅イオンが発生することはなく、ペレ
ットのアルミニューム配線について銅イオン番こよる腐
食現象も未然に回避される。：#g90ripe-sa）both ■convex7rjutomi】mouth 1, A R, no copper ions are generated during hydrochloric acid treatment, and corrosion caused by copper ions occurs in the aluminum wiring of the pellet. is also avoided.
〔実施例２〕 第４図は本発明の他の実施例を示す縦断面図である。[Example 2] FIG. 4 is a longitudinal sectional view showing another embodiment of the present invention.
本実施例２が前記実施例１と異なる点は、被圧縮部８Ａ
が銅めっき被膜７Ａの全体について形成されている点に
あり、その作用効果は前記実施例１と略同様である。The difference between the second embodiment and the first embodiment is that the compressed portion 8A
is formed over the entire copper plating film 7A, and its effects are substantially the same as those of the first embodiment.
〔実施例３〕
第５図は本発明の別の他の実施例を示す縦断面図である
。[Embodiment 3] FIG. 5 is a longitudinal sectional view showing another embodiment of the present invention.
本実施例３が前記実施例１と異なる点は、被圧縮部８Ａ
が銅めっき被膜７Ａの全体について形成されるとともに
、リードフレームにおける各ポストに対応する部分に銅
めっき被膜７Ｂが被圧縮部８Ａ上にさらに被着されてい
る点にあり、その作用効果は前記実施例１と略同様であ
る。The difference between the third embodiment and the first embodiment is that the compressed portion 8A
is formed on the entire copper plating film 7A, and a copper plating film 7B is further deposited on the compressed portion 8A at a portion corresponding to each post in the lead frame, and its effect is that of the above-mentioned implementation. This is substantially the same as Example 1.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
例えば、被膜を構成する金属は銅に限らず、金、銀、ア
ルミニューム等の導体やその他の金属を使用してもよい
。For example, the metal constituting the coating is not limited to copper, and conductors such as gold, silver, aluminum, and other metals may also be used.
金属被膜の被着手段は電解めっき処理に限らず、茎着等
を使用してもよい。The means for applying the metal film is not limited to electrolytic plating, but a method such as sintering may also be used.
圧縮手段としては圧延加工（ｒｏｌｌｉｎｇ）に限らず
、鍛造加工（ｆｏｒｇｉｎｇ）、圧印加工（ｃｏｉｎｉ
ｎｇ）等を使用することができる。The compression means is not limited to rolling, but also forging, coining, etc.
ng) etc. can be used.
＋１１ リードフレーム上に被着された金属被膜を圧
縮させることにより、金属被膜を酸化、剥離および熔融
しにくく改質させることができるため、当該被圧縮部に
対応するリードフレームのパンケージとの界面の接着強
度を高めることができる。+11 By compressing the metal coating deposited on the lead frame, it is possible to modify the metal coating to make it difficult to oxidize, peel off, and melt. Adhesive strength can be increased.
（２） リードフレームのアウタリードに被着された
金属被膜に被圧縮部を形成することにより、パッケージ
の外縁部におけるアウタリードとパ、７ケージとの界面
の接着強度を高めることができるため、耐湿性を向上さ
せることができる。(2) By forming a compressed part in the metal coating attached to the outer lead of the lead frame, it is possible to increase the adhesive strength at the interface between the outer lead and the cage at the outer edge of the package, resulting in moisture resistance. can be improved.
（３） 金属被膜として銅を使用することにより、高
価な金銀を使用せずに良好な導電性を確保することがで
きるため、コストを低減化させることができる。(3) By using copper as the metal coating, good conductivity can be ensured without using expensive gold and silver, so costs can be reduced.
（４） リードフレームの被ボンディング部に銅めっ
き被膜の表面を残すことにより、その表面に良好なボン
ダビリティ−を発揮させることができるため、良好なボ
ンディング状態を得ることができ、製品の品質および信
頼性を高めることができる。(4) By leaving the surface of the copper plating film on the bonding target part of the lead frame, it is possible to exhibit good bondability on the surface, so it is possible to obtain a good bonding condition, and improve the quality and quality of the product. Reliability can be increased.
（５） リードフレームにおけるパッケージの外縁に
被圧縮部を形成して、パッケージの内側部分に金属被膜
を残すことにより、被ボンディング部の外方に段差部を
形成することができるため、水分の浸入をせき止め、耐
湿性を一層向上させることができる。(5) By forming a compressed part on the outer edge of the package in the lead frame and leaving a metal coating on the inner part of the package, it is possible to form a stepped part outside the bonded part, which prevents moisture from entering. This can further improve moisture resistance.
Ｃ利用分野〕
以上の説明ではギとして本発明者によってなされた発明
をその背景となった利用分野であるミニモールド型トラ
ンジスタに適用した場合について説明したが、それに限
定されるものではなく、デュアル・イン・ライン・樹脂
封止型半導体装置等、特に、リードフレームにペレット
を搭載されるものであって樹脂封止型パッケージを備え
ている電子装置全般に適用することができる。C Field of Application] In the above explanation, the invention made by the present inventor is applied to a mini-mold type transistor, which is the field of application that formed the background of the invention. The present invention can be applied to in-line resin-sealed semiconductor devices, and in particular to electronic devices in general that have a resin-sealed package in which a pellet is mounted on a lead frame.
第１図は本発明の一実施例であるミニモールド型トラン
ジスタを示す縦断面図、
第２図はそれに使用されるリードフレームを示す斜視図
、
第３図は作用を説明するための他のミニモールド型トラ
ンジスタを示す縦断面図、
第４図は本発明の他の実施例を示す縦断面図、第５図は
本発明の別の他の実施例を示す縦断面図である。
ｌ・・・ミニモールド型トランジスタ（電子装置）、２
・・・リードフレーム、３・・・外枠、４Ａ、４Ｂ、４
Ｃ・・・アウタリード、５Ａ・・・コレクタボスト、５
Ｂ・・・エミッタポスト、５Ｃ・・・ヘースポスト、６
・・・母材、７．７Ａ、７Ｂ・・・銅めっき被膜（金属
被膜）、８．８Ａ・・・被圧縮部、９・・・ペレット、
ｌＯ・・・ボンディングワイヤ、１１・・・パッケージ
。
代理人 弁理士 小 川 勝 男 ・、第 １
図
第 ２ 図Fig. 1 is a longitudinal sectional view showing a mini-mold type transistor which is an embodiment of the present invention, Fig. 2 is a perspective view showing a lead frame used therein, and Fig. 3 is another mini-mold transistor for explaining the operation. FIG. 4 is a vertical cross-sectional view showing another embodiment of the present invention, and FIG. 5 is a vertical cross-sectional view showing another embodiment of the present invention. l...Mini mold type transistor (electronic device), 2
...Lead frame, 3...Outer frame, 4A, 4B, 4
C...Outer lead, 5A...Collector boss, 5
B... Emitter post, 5C... Heath post, 6
...Base material, 7.7A, 7B...Copper plating film (metal film), 8.8A...Compressed part, 9...Pellet,
lO...Bonding wire, 11...Package. Agent: Patent Attorney Katsuo Ogawa, 1st
Figure 2
Claims (1)
、この金属被膜が圧縮されてなる被圧縮部がリードフレ
ームの少なくとも一部に形成されている電子装置。 ２、金属被膜が、銅めっき被膜であることを特徴とする
特許請求の範囲第１項記載の電子装置。 ３、被圧縮部が、リードフレームの樹脂パッケージの外
縁部に対応する部分に形成されていることを特徴とする
特許請求の範囲第１項記載の電子装置。 ４、金属被膜の表面が、リードフレームの被ボンディン
グ部で露出されていることを特徴とする特許請求の範囲
第１項記載の電子装置。 ５、被圧縮部が、リードフレームの全体に形成されてい
ることを特徴とする特許請求の範囲第１項記載の電子装
置。 ６、金属被膜が、被圧縮部の上にさらに被着されて形成
されていることを特徴とする特許請求の範囲第１項記載
の電子装置。[Scope of Claims] 1. An electronic device in which a metal coating is deposited on a lead frame, and a compressed portion formed by compressing the metal coating is formed on at least a portion of the lead frame. 2. The electronic device according to claim 1, wherein the metal coating is a copper plating coating. 3. The electronic device according to claim 1, wherein the compressed portion is formed in a portion of the lead frame corresponding to the outer edge of the resin package. 4. The electronic device according to claim 1, wherein the surface of the metal coating is exposed at the bonding target portion of the lead frame. 5. The electronic device according to claim 1, wherein the compressed portion is formed over the entire lead frame. 6. The electronic device according to claim 1, wherein a metal coating is further formed on the compressed portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60290509A JPS62150754A (en) | 1985-12-25 | 1985-12-25 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60290509A JPS62150754A (en) | 1985-12-25 | 1985-12-25 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62150754A true JPS62150754A (en) | 1987-07-04 |
Family
ID=17756935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60290509A Pending JPS62150754A (en) | 1985-12-25 | 1985-12-25 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62150754A (en) |
-
1985
- 1985-12-25 JP JP60290509A patent/JPS62150754A/en active Pending
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