JPH09326700A - Multi-channel d/a converter - Google Patents

Multi-channel d/a converter

Info

Publication number
JPH09326700A
JPH09326700A JP14241396A JP14241396A JPH09326700A JP H09326700 A JPH09326700 A JP H09326700A JP 14241396 A JP14241396 A JP 14241396A JP 14241396 A JP14241396 A JP 14241396A JP H09326700 A JPH09326700 A JP H09326700A
Authority
JP
Japan
Prior art keywords
channel
signal
circuit
converter
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14241396A
Other languages
Japanese (ja)
Inventor
Kaname Kawaguchi
要 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP14241396A priority Critical patent/JPH09326700A/en
Publication of JPH09326700A publication Critical patent/JPH09326700A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PROBLEM TO BE SOLVED: To simplify circuit constitution and to perform a high-speed processing. SOLUTION: This D/A converter is composed of D/A conversion parts 11 -1n to which digital amount inputs D1-Dn are successively updated by an arithmetic cycle and inputted and a signal selection circuit 2 for successively outputting digital amount selection inputs DS1-DSn successively turned ON by the arithmetic cycle respectively to the conversion parts 11 -1n as channel selection signals and data write signals. Since a channel is selected and the timing of successive data write to the conversion parts 11 -1n is managed in the signal selection circuit 2, the need of a conventionally required external timing circuit is eliminated, the timings of channel selection and write are matched and thus, troubles by the timing are not generated and the arithmetic cycle is changed from conventional 60ms to be equal to or less than 20ms.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、計測,制御信号に
おける数点のディジタル量をアナログ量に変換する多チ
ャンネルのD−A変換装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel D / A converter for converting digital quantities of several points in measurement and control signals into analog quantities.

【0002】[0002]

【従来の技術】プログラマブルコントローラ(PC)で
は、PC内のディジタル量を数点のアナログ量に変換し
て出力する多チャンネルのD/A変換ユニットがある。
この変換ユニットは図3のように複数のD/A変換部1
1〜1nを備えており、PC内データアドレス1〜nのデ
ィジタル量をそれぞれD/A変換部11〜1nでアナログ
量に変換してアナログ出力A1〜Anを出力するように
なっている。
2. Description of the Related Art In programmable controllers (PC), there is a multi-channel D / A conversion unit that converts a digital quantity in the PC into several analog quantities and outputs the analog quantity.
This conversion unit includes a plurality of D / A conversion units 1 as shown in FIG.
1 to 1 n are provided, and the digital amounts of the data addresses 1 to n in the PC are converted into analog amounts by the D / A converters 1 1 to 1 n , and the analog outputs A1 to An are output. There is.

【0003】[0003]

【発明が解決しようとする課題】従来多チャンネルD−
A変換装置(ユニット)のデータ変換方式は、図4に示
すように、演算周期TS(=60ms)でデータ更新し
て各D/A変換部(チップ)11〜1n(図3)に入力
し、チャンネル切換回路,外部タイミング処理回路(図
示省略)によりチップセレクト信号CS1〜CSn及び
ライト信号WRを図示のタイミングでD/A変換部11
〜1nに入力してチャンネルの切換及びデータの書込を
行い、更新されるデータD1〜Dnを順次選択されたチ
ャンネルのD/A変換部11〜1nで変換し、アナログ出
力A1〜Anをするようになっているが、このタイミン
グ処理回路は繁雑で、高速化,小型化,ローコスト化の
障害となっている。
[Problems to be Solved by the Invention] Conventional multi-channel D-
As shown in FIG. 4, the data conversion method of the A conversion device (unit) is such that the data is updated at a calculation cycle T S (= 60 ms) and each D / A conversion unit (chip) 1 1 to 1 n (FIG. 3). type in the channel switching circuit, external timing processing circuit (not shown) by the timing shown a chip select signal CS1~CSn and the write signal WR D / a converter section 1 1
To 1 n to switch channels and write data, and the updated data D1 to Dn are sequentially converted by the D / A converters 1 1 to 1 n of the selected channels to output analog outputs A1 to However, the timing processing circuit is complicated, which is an obstacle to speeding up, downsizing, and cost reduction.

【0004】本発明は、従来のこのような問題点に鑑み
てなされたものであり、その目的とするところは、各D
/A変換部にディジタル値を書き込むタイミング機能を
簡単にし高速化,小型化を可能とした多チャンネルA−
D変換装置を提供することにある。
The present invention has been made in view of the above-mentioned problems of the prior art, and the purpose thereof is to provide each D
A multi-channel A- that simplifies the timing function for writing digital values to the A / A converter and enables high speed and downsizing.
It is to provide a D conversion device.

【0005】[0005]

【課題を解決するための手段】本発明の多チャンネルD
−A変換装置は、ディジタル量入力が演算周期で更新さ
れて入力する複数のD−A変換部と、演算周期で順次オ
ンする複数のディジタル量選択入力をそれぞれ前記複数
のD−A変換部へチャンネル選択信号及びデータ書込信
号として順次出力する信号選択回路とを有し、信号選択
回路にて各D−A変換部へのデータ書込のタイミングを
管理するものである。
Multichannel D of the present invention
The -A converter includes a plurality of D-A conversion units that receive digital amount inputs updated in the calculation cycle and a plurality of digital-amount selection inputs that sequentially turn on in the calculation period to the plurality of D-A conversion units. A signal selection circuit that sequentially outputs as a channel selection signal and a data write signal is provided, and the signal selection circuit manages the timing of writing data to each DA converter.

【0006】[0006]

【発明の実施の形態】図1に多チャンネルD/A変換装
置の回路構成を、図2にD/A変換タイムチャートを示
す。図1において、11〜1nはD/A変換部、2は内部
処理によるディジタル量選択入力DS1〜DSnの各D
/A変換部11〜1nに対する信号選択回路、3はD/A
変換部11〜1nにアナログの基準電圧を与える基準電圧
回路、S1〜Snは回路3からの基準電圧と外部アナログ
信号AEX1〜AEXnを切り換えてD/A変換部11〜1n
に入力するスイッチで、常時は基準電圧側に入ってい
る。
1 shows a circuit configuration of a multi-channel D / A conversion device, and FIG. 2 shows a D / A conversion time chart. In FIG. 1, 1 1 to 1 n are D / A converters, 2 is each D of digital amount selection inputs DS1 to DSn by internal processing
A / A converters 1 1 to 1 n are signal selection circuits, 3 is D / A
A reference voltage circuit for giving an analog reference voltage to the converters 1 1 to 1 n , S 1 to S n are D / A converters 1 by switching the reference voltage from the circuit 3 and the external analog signals A EX 1 to A EX n. 1 to 1 n
It is a switch to input to, and is always on the reference voltage side.

【0007】D/A変換部11〜1nの各入力端子には図
2(a)のように演算周期TSで更新されるディジタル
量D1〜Dnが入力する。信号選択回路2には図2
(b)のように周期TSで順次ONするディジタル量選
択入力DS1〜DSnが入力し、該回路で順次選択され
た信号がチップセレクト信号CS及びライト信号WRと
して順次D/A変換部11〜1nに入力する。
Digital quantities D1 to Dn updated at the operation cycle T S as shown in FIG. 2A are input to the input terminals of the D / A converters 1 1 to 1 n . The signal selection circuit 2 is shown in FIG.
As shown in (b), the digital amount selection inputs DS1 to DSn which are sequentially turned on in the cycle T S are input, and the signals sequentially selected by the circuit are sequentially selected as the chip select signal CS and the write signal WR in the D / A conversion unit 1 1 Type in ~ 1 n .

【0008】しかして、D/A変換部11〜1nは信号選
択回路2から順次出力されるディジタル量選択入力DS
1〜DSnにより順次チャンネル選択されると共にデー
タの書き込みがなされ、選択されデータ書込されたD/
A変換部11〜1nによって入力ディジタル量D1〜Dn
がD/A変換されて図2(c)のようにアナログ出力A
1〜Anを順次出力する。
Therefore, the D / A converters 1 1 to 1 n are connected to the digital quantity selection input DS sequentially output from the signal selection circuit 2.
Channels are sequentially selected by 1 to DSn, data is written, and the selected and written D /
Input digital quantities D1 to Dn by the A converters 1 1 to 1 n
Is D / A converted to analog output A as shown in FIG. 2 (c).
1 to An are sequentially output.

【0009】また、スイッチS1〜Snを外部アナログ信
号AEX1〜AEXn側に切り換えれば、D/A変換部11
〜1nの基準値がAEX1〜AEXn倍されたことになり、
D/A変換部11〜1nからディジタル量入力D1〜Dn
と外部アナログ信号AEX1〜AEXnを掛算したアナログ
出力A1〜Anが得られる。
If the switches S 1 to S n are switched to the external analog signals A EX 1 to A EX n side, the D / A converter 11
It means that the standard value of ~ 1 n is multiplied by A EX 1 ~ A EX n,
Digital quantity inputs D1 to Dn from D / A converters 1 1 to 1 n
Analog output A1~An is obtained by multiplying the external analog signal A EX 1 to A EX n and.

【0010】このD/A変換装置によれば、タイミング
処理回路の必要がなく、タイミングによるトラブルの発
生の恐れもないので、演算周期TSを従来の60msか
ら20ms以下にした高速処理が可能となった。
According to this D / A converter, a timing processing circuit is not required, and there is no fear of occurrence of a trouble due to timing. Therefore, it is possible to perform high-speed processing with the operation cycle T S set to 20 ms or less from the conventional 60 ms. became.

【0011】[0011]

【発明の効果】本発明は、上述のとおり構成されている
ので、次に記載する効果を奏する。
Since the present invention is configured as described above, it has the following effects.

【0012】(1)ディジタル量入力とディジタル量選
択入力を同期して更新するだけで、各チャンネルのD/
A変換ができる。
(1) Only by updating the digital quantity input and the digital quantity selection input in synchronization, the D /
A conversion is possible.

【0013】(2)複雑な書込の外部タイミング処理回
路を必要とせず、しかもタイミングによるトラブルの発
生の恐れがなくなるので、多チャンネルA/D変換ユニ
ットとして使いやすいユニットが得られる。
(2) Since an external timing processing circuit for complicated writing is not required and there is no fear of occurrence of trouble due to timing, a unit which is easy to use as a multi-channel A / D conversion unit can be obtained.

【0014】(3)このため高速処理,小型化,ローコ
スト化ができる。
(3) Therefore, high speed processing, downsizing and cost reduction can be achieved.

【0015】(4)外部アナログ信号を入力すること
で、D/A変換掛算演算器として使用できる。
(4) By inputting an external analog signal, it can be used as a D / A conversion multiplication calculator.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかるA/D変換装置の回路構成図。FIG. 1 is a circuit configuration diagram of an A / D conversion device according to the present invention.

【図2】D/A変換のタイムチャート。FIG. 2 is a time chart of D / A conversion.

【図3】従来PC内D/A変換ユニットのD/A変換方
式説明図。
FIG. 3 is an explanatory diagram of a D / A conversion method of a conventional PC D / A conversion unit.

【図4】従来D/A変換のタイムチャート。FIG. 4 is a time chart of conventional D / A conversion.

【符号の説明】[Explanation of symbols]

1〜1n…D/A変換部 2…信号選択回路 3…基準電圧回路 TS…演算周期1 1 to 1 n ... D / A converter 2 ... Signal selection circuit 3 ... Reference voltage circuit T S ... Calculation cycle

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ディジタル量入力が演算周期で更新され
て入力する複数のD−A変換部と、 演算周期で順次オンする複数のディジタル量選択入力を
それぞれ前記複数のD−A変換部へチャンネル選択信号
及びデータ書込信号として順次出力する信号選択回路
と、を有し、信号選択回路にて各D−A変換部へのデー
タ書込のタイミングを管理することを特徴とした多チャ
ンネルD−A変換装置。
1. A plurality of D-A converters for inputting digital quantity inputs updated in a calculation cycle, and a plurality of digital quantity selection inputs sequentially turned on in a calculation cycle are channeled to the plurality of DA converters, respectively. A multi-channel D-, characterized in that it has a selection signal and a signal selection circuit for sequentially outputting as a data writing signal, and the signal selection circuit manages the timing of data writing to each DA converter. A converter.
【請求項2】 請求項1において、各D−A変換部へ基
準電圧と外部アナログ信号を切り換えて入力する切換手
段を設け、ディジタル量と外部アナログ信号との積のア
ナログ信号を出力しうるようにしたことを特徴とする多
チャンネルD−A変換装置。
2. A switching means for switching and inputting a reference voltage and an external analog signal to each DA conversion section according to claim 1, so that an analog signal of a product of a digital amount and an external analog signal can be output. A multi-channel D / A conversion device characterized in that
JP14241396A 1996-06-05 1996-06-05 Multi-channel d/a converter Pending JPH09326700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14241396A JPH09326700A (en) 1996-06-05 1996-06-05 Multi-channel d/a converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14241396A JPH09326700A (en) 1996-06-05 1996-06-05 Multi-channel d/a converter

Publications (1)

Publication Number Publication Date
JPH09326700A true JPH09326700A (en) 1997-12-16

Family

ID=15314764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14241396A Pending JPH09326700A (en) 1996-06-05 1996-06-05 Multi-channel d/a converter

Country Status (1)

Country Link
JP (1) JPH09326700A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014082592A (en) * 2012-10-15 2014-05-08 Sumitomo Electric Ind Ltd Optical module for optical communication system and method of updating firmware of optical module for optical communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014082592A (en) * 2012-10-15 2014-05-08 Sumitomo Electric Ind Ltd Optical module for optical communication system and method of updating firmware of optical module for optical communication system

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