JPH09325803A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the processing time required for comparison and judgement, to attain high speed scanning and to improve the real time-controllability. SOLUTION: At the end of one scanning control operation, each processor 1 writes its operation result in a dual port memory 2 in the ascending order of addresses. In this case, respective writing addresses are inputted to each reading means 4, the smallest address value is selected, the operation result written in the memory 2 is immediately read out based on the selected address and a judging means 5 compares the read operation result with an operation result similarly read out from another programmable controller to judge the result and outputs one operation result to execute the writing, reading and comparison/judgement of plural operation results in parallel. Program control is executed based on the judged operation result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly reliable programmable controller in which a plurality of controllers execute the same control program and compare and judge the respective operation results with each other for control.

[0002]

2. Description of the Related Art Programmable controllers are
It is widely used for control of industrial systems such as machine control for assembly and the like, control for production lines, plant control for steel and paper manufacturing, water and sewerage, building management, and so on. Especially when reliability is required for public systems and transportation systems, the same control program is executed using multiple controllers, the results of each operation are compared with each other, and the correct operation results are determined to perform control. A highly reliable programmable controller is used.

An example of a highly reliable programmable controller of this type is shown in FIG. In this example, three programmable controllers are used, and the programmable controllers 1, 2, and 3 execute the same program and mutually compare the respective operation results, and judge the correct operation result by the majority logic and execute the program. Take control.

Each programmable controller 1, 2, 3
Is a processor 1-1, 2-1, 3-1 that performs control calculation
And the processor of the programmable controller itself writes the operation result, and each processor of the other two programmable controllers writes the operation result 2
Two dual-port memories 1-2 and 1-3, 2-2 and 2
-3, 3-2 and 3-3.

The processor 1-1 is connected to the dual port memories 1-2 and 1-3 and the dual port memories 2-2 and 3-2 via the bus 1-12. The processor 2-1 is connected to the dual port memories 2-2 and 2-3 and the dual port memories 1-2 and 3-3 via the bus 2-12. The processor 3-1 is connected to the dual port memories 3-2 and 3-3 via the bus 3-12, and is also connected to the dual port memories 1-3 and 2-3. Therefore, the processor 1-1 outputs the operation result to the dual port memories 1-2, 1
-3 while writing to the dual port memory 2-2,
3-2, the processor 2-1 can write the calculation result to the dual-port memories 2-2 and 2-3 and the dual-port memories 1-2 and 3-3, and the processor 3- 1 can write the calculation result to the dual port memories 3-2 and 3-3 and the dual port memories 1-3 and 2-3.

Each of the processors 1-1, 2-1, 3-1 is
A control calculation (scan) of the program is performed based on a control program stored in a program memory (not shown), and each time the scan is performed, the calculation results are collated with each other and the program control is executed with the calculation result determined by the majority vote.

FIG. 5 shows the verification process of the processor 1-1. When the control operation (process 10) for one scan is completed, the operation result is written (transferred) to the dual port memories 2-2 and 3-2. (Processing 11) is performed, and the calculation result of the processor 2-1 written in the dual port memory 1-2 and the calculation result of the processor 3-1 written in the dual port memory 1-3 are read (processes 12 and 13). , Comparison (comparison) with the calculation result of the processor 1-1 itself (Process 1
4) is performed, when all the operation results of the three programmable controllers are equal, it is determined that the operation result is normally performed, and when two operation results out of the three operation results are equal and only one operation result is different, The calculation result is discarded, two equal calculation results are adopted, and one calculation result is decided by majority vote. The processors 2-1 and 3-1 also perform the same matching process as the processor 1-1.

FIG. 6 shows the timing of the progress of the scan execution of each processor. When the control operation of one scan is completed, the operation results are transferred to each other. Comparison (judgment)
Processing is performed, one operation result is determined by majority, and program control is executed based on the determined operation result. As described above, program control is performed by majority voting of the calculation results of the three programmable controllers.

[0009]

As described above, in the conventional programmable controller, after the control operation for one scan is completed, the operation results are transferred to each other,
After that, since the comparison and determination processing of the calculation result is performed, the scanning time becomes long, and there is a problem that the real-time controllability is impaired.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable controller which shortens the processing time required for comparison and determination, enables high-speed scanning, and has improved real-time controllability. Especially.

[0011]

In order to achieve the above object, the programmable controller of the present invention is a programmable controller including a processor that scans a control program and repeats a control operation. In the dual port memory, the plurality of calculation results obtained by the control calculation are written in the ascending order of addresses, and the addresses output from the processor are compared with the addresses output in the same manner from other programmable controllers to calculate the values. Reading means for selecting the smaller address and reading out the operation result written in the selected address of the dual port memory, and the operation result read out and the operation result similarly read from another programmable controller If they are equal, it is judged as normal operation Comprising a determination unit, two programmable controller performs control calculation based on the same control program, to synchronize the start of the scan is performed in parallel with writing and reading and the comparison determination of the plurality of operation results. According to another aspect of the present invention, in a programmable controller including a processor that scans a control program and repeats a control operation, the processor obtains a plurality of operation results obtained by the control operation each time the control operation ends, in ascending order of address. Write to a dual port memory, compare the address output from the processor with a plurality of addresses output from other programmable controllers in the same manner, and select the smallest value address. The reading means for reading out the operation result written at the selected address and the read operation result and the plurality of operation results similarly read out from the other plurality of programmable controllers are compared, and the result is 1 by the majority logic. Equipped with a determination means that determines one calculation result, Also, three programmable controllers perform control calculation based on the same control program, synchronize the start time of scanning, and perform writing and reading of a plurality of calculation results and comparison determination in parallel. (Claim 2) Furthermore, the reading means uses an address bus and a control bus for the processor to write an operation result in the dual port memory on the input side and a similar address bus and control bus drawn from another programmable controller. Connected, the output side is connected to the address bus and the control bus for reading the operation result from the dual port memory, compares the plurality of input addresses, selectively outputs the minimum value address, and outputs the read command. An address / command generating means is provided. (Claim 3) Further, the determination means is connected to a data bus for reading out the operation result from the dual port memory and a similar data bus drawn from another programmable controller, and a plurality of operation results read out. And a data comparison means for determining one calculation result. (Claim 4) Further, when the processor ends the control operation and writes a plurality of operation results to the dual port memory, when the write start is earlier than the write start of the other programmable controller, the other programmable controller An arbitration unit that waits for the reading of the calculation result until the address is given is provided, and the reading of the calculation result is synchronized. (Claim 5) Further, when the determination means compares a plurality of operation results and determines that the operation results are different, a read address of the dual port memory, each operation result, and a programmable controller which outputs the operation result A maintenance memory for storing the type data to be distinguished is provided. (Claim 6)

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the programmable controller of the present invention is shown in FIG. This embodiment is an example using three programmable controllers 1, 2, and 3.
Each programmable controller 1, 2, 3 includes a processor 1-1, 2-1, 3-1 and a dual port memory 1
-2, 2-2, 3-2, address / command generation circuit (reading means) 1-4, 2-4, 3-4, and data comparison circuit (determination means) 1-5, 2-5, 3 Each processor 1 is provided with -5, and each processor 1 scans the same control program stored in a program memory (not shown) to perform a control operation, and writes the operation result to each dual port memory 2 each time the scan is performed. . Each address
The command generation circuit 4 receives three write commands via the control buses 1-6, 2-6, and 3-6 when each processor 1 writes the operation result, and also receives the address bus 1-7, Three addresses are input via 2-7 and 3-7, the address of the smallest value is output via address buses 1-10, 2-10, 3-10, and control buses 1-9, 2 A read command is output via -9 and 3-9 to read the operation result written in the dual port memory 2. Each data comparison circuit 5
The operation result of each processor read from each dual port memory 2 is the data bus 1-11, 2-11, 3-1.
1 is input via 1 and one operation result is determined from the three operation results by the majority logic.

In the above structure, each processor 1 scans based on the same control program stored in a program memory (not shown), and executes the control calculation of the program. In this case, synchronize the start time of the scan,
Each time scanning is performed, as shown in FIG. 2, the operation results are collated with each other, and the program control is executed with the operation result determined by the majority vote. That is, when the control calculation (process 20) in one scan is completed, each processor 1 outputs the plurality of calculation results obtained by the control calculation to each data bus 1-8, 2-.
Writing is performed to each dual port memory 2 via 8 and 3-8 (process 21). At this time, writing is performed in ascending order of the address of each dual port memory. Also,
The write command and address for writing output from each processor 1 are control buses 1-6, 2-6, 3-6.
And address bus 1-7, 2-7, 3-7 to each address command generation circuit 4, each address command generation circuit 4 compares each address and selects the smallest address, Bus 1-10, 2-10, 3
-10, and at the same time control buses 1-9, 2-
The read command is output via 9, 3-9. Therefore, the operation result written in each dual port memory 2 is read out to the data buses 1-11, 2-11, 3-11. (Processing 24). In this case, if the timings at the start of writing of the respective processors 1 are all the same, all the addresses input to the respective address / command generating circuits 4 are the same, and immediately after the writing of the operation result, the reading is performed and the writing Reading is performed in parallel.

However, when there is a time difference in the timing of the writing start time of each processor 1 for some reason, each address / command generation circuit 4 stops its function until addresses are given from all the processors (process 2).
3), the preceding processor only writes the calculation result. When an address is given from the processor that started writing last, each address / command generation circuit 4 selects the smallest address, outputs the address given from the processor that started writing last, and reads the operation result. . When the preceding processor finishes writing, the address / command generation circuit 4 holds the last address until all the addresses match. Therefore, in this case, after writing the calculation result, reading is performed with a delay of several steps, and writing and reading are performed in parallel. FIG. 3 shows a timing chart in this case.

Each time the calculation results read from the dual port memories 2 of the programmable controllers 1, 2 and 3 are input to the data comparison circuit 5, each data comparison circuit 5 outputs a plurality of calculations. The results are compared and one operation result is determined by majority logic (process 2
5). When writing and reading of all calculation results are completed, the next scan can be started (process 27).

As described above, according to the present embodiment, by synchronizing only the scan start points of the control programs of the plurality of programmable controllers, the clocks of the instruction execution levels of the processors are not completely synchronized. The calculation results of the programmable controllers can be compared with each other, and the determination processing time can be performed within substantially the transfer (write) processing time.

When the data comparison circuits 5 compare a plurality of operation results and determine that the operation results are different, the read address of the dual port memory 2, each operation result, and the programmable controller that outputs the operation result. By providing the maintenance memory for storing the type data for distinguishing between the two types and monitoring the stored data, it is possible to easily find the programmable controller having the abnormal operation and improve the maintainability.

In the above description, an example in which three programmable controllers are used has been described, but three or more programmable controllers can be used. Further, the data comparison circuits 1-5 and 2-
5 and 3-5 are compared with each other by comparing the two calculation results, and when they match, it is determined to be normal, and when they do not match, processing such as referring to past calculation results is performed and one calculation result is output. It is also possible to implement by using two programmable controllers.

[0019]

According to the present invention, when a plurality of programmable controllers are scanned by the same control program and the operation results are compared with each other to execute program control,
By synchronizing only the scan start point of the control program, it becomes possible to perform writing and reading of a plurality of calculation results and comparison judgment in parallel without completely synchronizing the instruction execution level clocks of the processor. It is possible to provide a programmable controller that can compare the calculation results simultaneously in the background that transfers the calculation results, shorten the processing time for mutual comparison, enable high-speed scan execution, and improve real-time controllability. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a programmable controller according to the present invention.

FIG. 2 is a flow chart for explaining the operation of the above embodiment.

FIG. 3 is a timing chart for explaining the operation of the above embodiment.

FIG. 4 is a block diagram of a conventional programmable controller.

FIG. 5 is a flowchart for explaining the operation of the conventional device.

FIG. 6 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

1, 2, 3, ... Programmable controller 1-1, 2-1, 3-1 ... Processor 1-2, 2-2, 3-2 ... Dual port memory 1-4, 2-4, 3-4 ... Address Command generation circuit (reading means) 1-5, 2-5, 3-5 ... Data comparison circuit (determination means) 1-6, 2-6, 3-6 ... Control bus (write command) 1-7, 2- 7, 3-7 ... Address bus (write) 1-8, 2-8, 3-8 ... Data bus (write) 1-9, 2-9, 3-9 ... Control bus (read command) 1-10, 2-10, 3-10 ... Address bus (read) 1-11, 2-11, 3-11 ... Data bus (read)

Claims (6)

[Claims] 1. A programmable controller including a processor that scans a control program and repeats a control operation, wherein the processor is a dual-port processor that outputs a plurality of operation results obtained by the control operation each time the control operation ends. Write to the memory, compare the address output from the processor with the address similarly output from another programmable controller, select the address with the smaller value, and select the selected address of the dual port memory. Two programmable controllers are provided with a reading means for reading out the written operation result and a determining means for judging a normal operation when the read operation result and the operation result similarly read from another programmable controller are equal. Are based on the same control program Performs control operation, synchronizing the start time point of the scan, the programmable controller and performing in parallel a plurality of operation results in writing and reading and comparison determination. 2. A programmable controller having a processor for scanning a control program and repeating control operations, wherein said processor is a dual port processor which outputs a plurality of operation results obtained by the control operation each time the control operation is completed. Writing to the memory, comparing the address output from the processor with a plurality of addresses similarly output from a plurality of other programmable controllers, selecting the address having the smallest value, and selecting the address of the dual port memory. Read out means for reading out the operation result written in the address, and the operation result read out is compared with a plurality of operation results similarly read out from a plurality of other programmable controllers to perform one operation by the majority logic. At least 3 units equipped with judgment means to determine the result Programmable controller programmable controller performs control calculation based on the same control program, to synchronize the start of the scan, and performs in parallel a plurality of writing and reading and comparison and determination of the calculation results. 3. The programmable controller according to claim 1, wherein the read means has an address bus and a control bus for inputting an arithmetic result to the dual port memory by the processor on the input side, and another programmable controller. Connected to the same address bus and control bus derived from the output side, the output side is connected to the address bus and the control bus for reading the operation result from the dual port memory, and a plurality of input addresses are compared to determine the minimum value. A programmable controller characterized by comprising address / command generating means for selectively outputting an address and outputting a read command. 4. The programmable controller according to claim 1 or 2, wherein the determination means is a data bus for reading out an operation result from the dual port memory and a similar data bus derived from another programmable controller. A programmable controller comprising: a data comparison unit connected to the CPU, and comparing and determining a plurality of read operation results to determine one operation result. 5. The programmable controller according to claim 1 or 2, wherein when the processor finishes a control operation and writes a plurality of operation results to the dual port memory, the start of writing is another programmable controller. A programmable controller characterized by comprising arbitration means for putting the reading of the operation result in a waiting state until an address is given from another programmable controller when the writing of the operation result is started, and synchronizing the reading of the operation result. 6. The programmable controller according to claim 1 or 2, wherein the determination means compares a plurality of operation results and determines that the operation results are different from each other.
A programmable controller comprising: a read address of a dual-port memory, a maintenance memory for storing each operation result, and type data for distinguishing a programmable controller outputting the operation result.