JPH09321585A - Method and device for generating pseudo-random binary sequence pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pseudo-random binary sequence pattern generation method on a device easy to realize easily its circuit by halving the speed of a clock required for the circuit operation. SOLUTION: A timing conversion circuit 1 applies serial conversion to an 8-bit timing signal 1a in the unit of 2 bits and provides an output to a loop register 2 and a pattern alignment circuit 3. The loop register 2 generates a pseudo-random binary sequence pattern by one or two bits each based on a received 2-bit signal and provides an output to the pattern alignment circuit 3. Furthermore, the pattern alignment circuit 3 rearranges a pattern outputted from the loop register 2 based on the 2-bit signal outputted from the timing conversion circuit 1 and provides an output.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to SDH (Synch
The present invention relates to a pseudo random binary sequence (hereinafter, referred to as PRBS) pattern generation method and generation apparatus used when conducting a continuity test or a line quality test for a digital communication network such as ronous digital hierarchy) and its equipment.

[0002]

2. Description of the Related Art First, PRBS (Pseudo Random Binar)
As an example of the data frame carrying the y Sequence) pattern, the SDH frame of 155.52 Mbit / s is shown in FIG.
264 Kbit / s PDH (Plesiochronous Digital H
ierarchy) A frame structure diagram when a frame is asynchronously mapped is shown. The frame structure shown in this figure will be described in detail later, but the PDH frame has 139264 Kb.
Other than it / s, 44736Kbit / s, 34368Kbit
/ S, 6312Kbit / s, 2048Kbit / s, 1544Kb
There is a speed of it / s.

These PDH frames have been conventionally used as an interface of a digital communication network, and SDH, which is a backbone communication network, converts these PDH frame signals into information bits (I bit) shown in the frame configuration diagram of FIG. ) Can be carried. In this regard,
ITU-T (International Telecommunication Union, Telecommunication Standardization Sector)
It is defined in G.708 and G.709 of the above, and it is called mapping that puts another type of data frame on one data frame according to such a rule. In addition, a measuring device for measuring the line quality of SDH and the continuity of data (hereinafter referred to as SD
H measuring device) uses PR instead of information bits when the PDH frame signal is mapped to the SDH frame.
By transmitting the BS pattern and measuring the bit error, the continuity of the PDH frame signal and the line quality are confirmed.

Next, as an example of a basic PRBS pattern generator, a configuration diagram of a PRBS pattern generator having a (2 ¹⁵ -1) bit length will be described with reference to FIG. This PRBS pattern generator is defined in ITU-T O.151.
First, the 15 flip-flops 31a to 31o form a 15-bit shift register 21, and the output of the flip-flop of each bit is input to the flip-flop of the next bit. Here, in FIG. 6, the illustration of the flip-flops 31d to 31m is omitted, and regarding the illustrated flip-flop, the bit number of the flip-flop is described. For example, "FF1" illustrated in the flip-flop 31a
Means that it is the first bit flip-flop.

The 14th bit flip-flop 3
1n and the output of the 15th bit flip-flop 31o are input to the exclusive OR 22, and the output of the exclusive OR 22 is input to the 1st bit flip-flop 31a. Table 1 shows a truth table of the exclusive OR 22.

[Table 1]

When the pattern of the shift register 21 is shifted bit by bit in accordance with a clock signal (not shown), P of (2 ¹⁵ -1) bit length is stored in the shift register 21.
An RBS pattern is generated. Since the 15 flip-flops 31a to 31o operate as a shift register, each flip-flop outputs the same pattern only with a different bit phase. In FIG.
The pattern from the 15th bit flip-flop 31o is used as an output, and the output pattern is inverted by the inverter 23 according to the regulations of ITU-T O.151 to output a PRBS pattern of (2 ¹⁵ -1) bit length. .

The SDH frame is divided into 8-bit units in the payload to facilitate parallel processing.
If the interface speed is 155.52 Mbit / s, normally, parallel processing is performed in units of 8 bits with a 19.44 MHz clock having a speed of 1/8. This is because it is difficult to realize a circuit that operates at 155.52 MHz with a low power consumption device such as CMOS or TTL. When data is loaded in 8-bit units, the PRBS pattern is also generated in 8-bit units. In that case, a circuit that generates a PRBS pattern in 8-fold speed, that is, 8-bit units can be used.

Next, an 8x PRBS pattern generator will be described with reference to FIG. In the PRBS pattern generator in this figure, each flip-flop is connected so that the shift in the shift register advances by 8 bits in one clock operation. That is, 15 flip-flops 41
55 to 55, the output of the flip-flop 41 of the 1st bit is connected to the input of the flip-flop 49 of the 9th bit, and similarly, the outputs of the flip-flops 42 to 47 of the 2nd to 7th bits correspond respectively. It is connected to the inputs of the 10th to 15th bit flip-flops 50 to 55.

The output signals from the corresponding exclusive ORs 56 to 63 are input to the first to eighth bit flip-flops 41 to 48, respectively. Then, the outputs of the 7th and 8th bit flip-flops 47 and 48 are input to the exclusive OR 56, and hereinafter, 8 to the exclusive OR 57.
The outputs of the 9th bit flip-flops 48 and 49 are input to the exclusive OR 58, and the outputs of the 9th and 10th bit flip-flops 49 and 50 are input.
In the exclusive ORs 56 to 63, the outputs of the continuous 2-bit flip-flops after the 7th bit are sequentially set to 1
Connected bit by bit. Further, eight inverters 64 to 64 that invert the outputs of the flip-flops 48 to 55
71 is provided, and the output from these inverters is output as an 8-bit PRBS pattern.

As described with reference to FIG. 6, this PRBS pattern generator generates 1 bit of the PRBS pattern by shifting the shift register by 1 bit, and if the PRBS pattern of 8 bits is required, 8
It depends on the idea that bit shifting should be done. In the case of a circuit that generates one bit at a time, as shown in FIG.
The flop 31o of the fifth bit is input to the exclusive OR 22, and the output signal is input to the flip-flop 31a of the first bit of the shift register.

On the other hand, as shown in FIG. 7, in order to shift the PRBS pattern by 8 bits, the outputs of the 14th and 15th bit flip-flops 54 and 55 of the shift register are input to the exclusive OR 63. The output is input to the 8th bit flip-flop 48, which is a bit position 7 bits ahead of the 1st bit flip-flop 41. Then, the 7th bit flip-flop 47 is
Since it is 1 bit slower than the 8th bit flip-flop 48, another exclusive OR 62 is prepared and the exclusive OR 62
The signals input to 62 may be connected to the outputs of the 13th and 14th bit flip-flops 53 and 54 which are delayed by 1 bit. Similarly, in the flip-flops 46 to 41 of the 6th bit to the 1st bit, the exclusive ORs 61 to 56 are exclusively prepared, and the output signals from the two shift registers which are delayed by 1 bit for each exclusive OR are provided. input.

As for the flip-flops 49 to 55, the flip-flops 41 to 41 8 bits before are provided.
Input the output from 47. As a result, one clock operation shifts by 8 bits, that is, an 8x PRBS.
A pattern generator can be constructed. However, since this circuit is fixed at 8 times speed, that is, a new 8-bit PRBS pattern is always output in one clock operation. Therefore, for example, a pattern is output only to an arbitrary number of bits out of the 8-bit output number. It is not possible to output.
The structure of the PDH frame placed on the SDH frame is not considered for parallel processing, so parallel processing is extremely difficult. That is, the PRBS described in FIG.
It is necessary to output the PRBS pattern only to an arbitrary number of bits out of 8 bits that cannot be output by the pattern generator.

The reason for this will be described in detail with reference to the frame structure diagram shown in FIG. In FIG. 5, the SDH frame is represented by 270 bytes × 9 lines, and the signal flow continues from the left end of the first line to the right end, then from the left end of the second line to the right end, and ends at the right end of the ninth line. . Further, 9 bytes from the left of each row are bytes for managing data, which are composed of SOH (Section Overhead) and AU (Administrative Unit) pointer, and the remaining 261 bytes are an area for carrying data called payload. Further, in the payload, 1 byte from the left end of each line is PO
It is a management byte called H (PATH Overhead), and I bit (information bit) in the remaining 260 bytes is 139264K.
A PDH frame signal of bit / s is loaded. Here, all the 9 lines in the payload have the same structure, as shown in FIG.
In the figure, only the first row is shown and the other eight rows are not shown.

Further, in this figure, 8I indicates that there are 8 I bits, and 96I indicates that there are 96 I bits. In other words, 8I is all 1 byte, 96
All 12 bytes of I are I bits. The R bit is called a fixed stuff bit, and is a bit on which no information is recorded. That is, 8R indicates that no information is written in all 1 byte.

In each line, there are 5 bytes named X and 1 byte named Z.
The bit configuration of these bytes is shown in the figure. In the X byte, a stuff control bit called C bit (described later) is 1 bit, an R bit is 5 bits, and an O bit is 2 bits. Here, the O bit is called an overhead bit, and is a bit provided in case communication in the future requires overhead. Thus, since there are 5 X bytes in each row, there are a total of 5 C bits in each row.

Further, the Z byte has 6 I bits, and like the other I bits, 139264 Kbit / s.
Data will be posted. Further, the Z byte has one stuff adjustment bit called S bit.
This bit is controlled by the C bit and determines whether it will be the I bit or the R bit. here,
Normally, the C bits of 5 bits included in each row are either "1" or "0", and if all are "1", the S bits become R bits and no data is written. On the other hand, when all are “0”, the S bit becomes the I bit and the data is loaded.

In this way, the SDH frame (155.52 Mbi) is adjusted by adjusting the number of bits to carry the data.
A PDH frame of 139264 Kbit / s, which is asynchronous with t / s), can be loaded on the SDH frame, but at this time, there is always a byte in which data is not loaded in 8-bit units, such as the Z byte described above. It will be. Also,
The SDH measuring device described above needs to be compatible with PDH frames of speeds other than 139264 Kbit / s.

Further, the above-mentioned 44736 Kbit / s, 34368
Kbit / s, 6312 Kbit / s, 2048 Kbit / s,
Even in the 1544 Kbit / s PDH frame, there are bytes that do not carry data in the SDH frame in 8-bit units.
Table 2 shows the bit configuration of those bytes. Note that each bit configuration shown in this table is also specified in G.709 of ITU-T, and in this table, for easy understanding, bits that do not carry data are collectively indicated by "-" and the data is The bits that can be placed are indicated by "I".

[Table 2]

As shown in this table, there are various kinds of bit configurations of bytes in which data is not loaded in 8-bit units, and when a PRBS pattern is loaded on a byte of such bit configuration, parallel processing is not performed. A pattern is generated serially bit by bit and rearranged into a required bit configuration.

Here, P of 32767 (2 ¹⁵ -1) bit length
A configuration example of a PRBS pattern generator that generates an RBS pattern and rearranges it into a required bit configuration will be described with reference to FIG. In this figure, the timing signal 81a is
It becomes "1" at the position where the PRBS pattern is placed 19.44 M
8 signals of bit / s. That is, for example, 155.
52Mbit / s SDH frame, 139264bit / s
When the PRBS pattern is placed on the I bit of the Z byte in the case of asynchronously mapping the PDH frame of No. 3, the timing signal 81a has bits 1 to 6 of "1" and bits 7 and 8 of "0" ( See Table 2).

This timing signal 81a is changed to TTL / E
The CL translator 81 converts the signal into an ECL level, and the parallel / serial conversion circuit 82 converts the signal into 155.52 Mbi.
The timing signal 82a of t / s is converted. The loop register 83 generates a serial PRBS pattern 83a according to the timing signal 82a.

The loop register 83 is a basic PRBS.
6 has the same configuration as the pattern generator described above, but in the case of the loop register 83, the operation of the shift register 21 in FIG. 6 is controlled by the timing signal 82a. That is, for example, the timing signal 82a is "1".
At this time, the PRBS pattern is newly output from the loop register 83 in accordance with the 1-bit clock timing. The serial / parallel conversion circuit 84 includes a serial timing signal 82a and a serial PRBS pattern 83.
a is input, and PRBS is input based on the timing signal 82a.
The pattern has an 8-bit structure. At this time, "0" is inserted in the bits that do not need to carry the PRBS pattern.
The PRBS pattern 84a having an 8-bit structure is an EC
The L / TTL translator converts to TTL level and outputs.

[0023]

By the way, in the circuit configuration as shown in FIG. 8, there is a problem that each configuration needs to operate at a very high speed. For example, 155.52 Mbit
When the PRBS pattern is put on the SDH frame of / s, each component of the PRBS pattern generator needs to operate based on the clock of 155.52 MHz. Since it is difficult to realize such a circuit by TTL, it is usually EC
You must use L. However, ECL is TT
Since the power consumption is much higher than L, the amount of heat generation is large and the degree of integration is low.

The present invention has been made in view of the above circumstances, and it is possible to easily realize a circuit by halving the clock speed required for circuit operation. An object is to provide a generating method and a generating device.

[0025]

According to a first aspect of the present invention, there is provided a plurality of output terminals, and a pseudo random binary sequence pattern having a bit structure based on an instruction from the outside is provided at the plurality of output terminals. In the method of generating a pseudo random binary sequence pattern, a pseudo random binary sequence pattern is sequentially generated by 1 bit or 2 bits based on an instruction from the outside, and the generated pseudo random binary sequence is generated. In the pseudo random binary sequence pattern generation method, the pattern is rearranged into a bit configuration based on an instruction from the outside and is output.

According to a second aspect of the present invention, a pseudo random binary system having a plurality of output ends and generating a pseudo random binary system sequence pattern having a bit structure based on an instruction from the outside at the plurality of output ends is provided. In the normal sequence pattern generator, pattern output means for sequentially outputting the pseudo random binary method sequence pattern by 1 bit or 2 bits based on the instruction from the outside, and the pseudo random binary output by the pattern output means. A pseudo random binary method sequence pattern generating device, comprising: a bit configuration forming means for rearranging a normal sequence pattern into a bit configuration based on an instruction from the outside.

According to a third aspect of the present invention, in the pseudo random binary sequence pattern generating device according to the second aspect, each bit of the instruction from the outside corresponds to each of the plurality of output terminals, A plurality of digital signals indicating whether or not a pseudo-random binary sequence pattern should be present in each bit, wherein the pattern output means serially converts the digital signals in 2-bit units; , If the 2-bit signals output from the serial converting means both indicate that a pseudo-random binary sequence pattern should be present, a pseudo-random binary sequence pattern is generated for every two bits. If 1 bit indicates that a pseudo-random binary sequence pattern should be present, then 1 bit at a time If a random binary system sequence pattern is generated, and none of the bits indicates that the pseudo random binary system sequence pattern should be present, a pattern generating means that does not generate the pseudo random binary system sequence pattern is used. It is characterized by

According to a fourth aspect of the present invention, in the pseudo random binary sequence pattern generating device according to the third aspect, the bit structure forming means is composed of a plurality of flip-flops, and receives the input bit signal. Pseudo-random number output from the pattern output means for the first and second shift registers based on a 2-bit signal output from the serial conversion means and first and second shift registers that sequentially shift. The pattern output control means for controlling the output destination of the binary sequence pattern, the respective flip-flops forming the first and second shift registers, and the bit signal output from the pattern output control means are given a predetermined value. And an output timing adjusting means for outputting at a timing.

According to a fifth aspect of the present invention, in the pseudo random binary sequence pattern generating device according to the fourth aspect, the pattern output control means outputs the 2-bit signal output from the serial conversion means together. When it is indicated that the pseudo random binary sequence pattern should be present, the upper bit of the 2-bit pseudo random binary sequence pattern output from the pattern output means is set to the first bit. In addition to the output to the shift register, the lower bits are output to the second shift register, and of the 2-bit signal output from the serial conversion means, only the upper bits are pseudo random binary sequence patterns. Indicates that there should be a 1-bit pseudo-random binary output from the pattern output means. The sequence pattern is output to the first shift register, and a bit signal indicating that there is no pseudo-random binary sequence pattern is output to the second shift register. If only the lower bits of the signal indicate that the pseudo random binary sequence pattern should be present, the 1-bit pseudo random binary sequence pattern output from the pattern output means is used as the first bit. A bit signal indicating that there is no pseudo-random binary sequence pattern is output to the first shift register, and the 2-bit signal output from the serial conversion means is output to the second shift register. If it does not indicate that a pseudo-random binary sequence pattern should exist, then Similar random binary sequence said first bit signal pattern indicating that there is no, and outputs each to the second shift register.

[0030]

1 shows an embodiment of a PRBS pattern generator according to the present invention. PRB shown in this figure
The S pattern generator includes a timing conversion circuit 1, a loop register 2, and a pattern alignment circuit 3. Also,
As an operation example, a case will be described in which a PRBS pattern is inserted into the information bits of a 44736 Kbit / s PDH frame asynchronously mapped to a 155.52 Mbit / s SDH frame. Here, FIG. 2 shows a frame configuration diagram when the PDH frame of 44736 Kbit / s is asynchronously mapped to the SDH frame of 155.52 Mbit / s. This figure 2
The frame structure in is represented by 84 bytes x 9 lines,
Each row has the same structure. In FIG. 2, only the first row is shown and the other eight rows are not shown.

In FIG. 2, 8R indicates that there are 8 R bits (fixed stuff bits), and 8I and 200
I has 8 bits and 2 I bits (information bits), respectively.
Indicates that there are 00 bits. In addition, in FIG.
The bytes indicated by are respectively "RRCIIII
It has a bit configuration of "I", "CCRRRRRRR", and "CCRROORS". Here, C means a stuff control bit, O means an overhead bit, and S means a stuff adjustment bit.

Returning to FIG. 1, the timing signal conversion circuit 1
Is the input timing signal 1a of 19.44 Mbit / s.
Is 77.76 Mbit / s, which is four times 19.44 Mbit / s.
It is converted into two serial timing signals 1b having a 4-bit length of s. Here, the timing signal 1a is, like the timing signal 81a in FIG. 8, eight signals of 19.44 Mbit / s which become "1" at the position where the PRBS pattern is placed. Here, in the frame configuration diagram shown in FIG.
Since the first byte and the second byte are all fixed stuff bits, the timing signal 1a is all "0", and the serial timing signal 1b is also all "0".

The third byte is the RRCIIIII from the upper byte.
Since the lower 5 bits are information bits, the timing signal 1a is input with the bit configuration "00011111". As a result, the timing signal conversion circuit 1 converts the higher-order two bits into two signals. That is, the signal of the first, third, fifth, and seventh bits (“0011”) from the higher order of the timing signal 1a
Are sequentially output as the upper timing, and in synchronization with this, the signals (“0111”) of the second, fourth, sixth and eighth bits are sequentially output as the lower timing.

Next, a configuration example of the loop register 2 is shown in FIG. This figure shows a PRB of 32767 (2 ¹⁵ -1) bit length.
A circuit that generates an S pattern, each of which is a selector SEL
Fifteen selector-equipped flip-flops (hereinafter referred to as SEL / FF) 5a
˜5o, inverters 6, 7 and two exclusive ORs 8,
9 and 9. Here, 1 from the 4th bit in the figure
Illustration of the second-bit SEL / FFs 5d to 5l is omitted.

The selector S in each SEL / FF
A connection similar to that of the PRBS pattern generation circuit shown in FIG. 6 is made at one input terminal of EL. That is, 2-1
Selector S in SEL / FF 5b to 5o of the 5th bit
The output of the previous bit SEL / FF is input to one input terminal of EL, and the one input terminal of the selector SEL in the 1st bit SEL / FF 5a has 14th and 15th bit SEL / FF 5n, The result of exclusive ORing the output of 5o, that is, the output of exclusive OR 9 is input.

The selector SE in each SEL / FF
The other input terminal of L is connected so that the pattern is shifted by 2 bits in one clock operation based on the same concept as the PRBS pattern generation circuit shown in FIG. That is, the SEL / FF 5c of the 3rd to 15th bits
2 to the other input terminal of the selector at
The output of SEL / FF one bit before is input. Also, 2
The output of the exclusive OR9 is input to the other input terminal of the selector SEL in the bit SEL / FF 5b, and the other input terminal of the selector SEL in the first bit SEL / FF 5a has 13, 14 bits. Eye SEL / FF5
The result of the exclusive OR of the outputs of m and 5n, that is, the output of the exclusive OR 8 is input.

In the above-mentioned SEL / FFs 5a to 5o, each selector SEL is a selector SEL when the two input serial timing signals 1b are both "1".
Shifts the pattern by 2 bits by selecting the output of SEL / FF 2 bits before. If either one is "1" and the other is "0", the selector SE
L shifts the pattern by 1 bit by selecting the output of the flip-flop 1 bit before. In addition, 2
In the case of "0" for both the books, the PRBS pattern generation circuit of FIG. 3 does not shift the pattern by stopping the clock of the flip-flop. By doing this,
A new P is added to the SEL / FFs 5a and 5b of the 1st and 2nd bits.
An RBS pattern is generated.

In the first and second bytes of the frame structure shown in FIG. 2, both of the two serial timing signals 1b are "0", so that the loop register 2 to which they are input does not operate at all. . At the 3rd byte, the first bit is 0 because both the upper and lower timings are "0", but it does not work, but the next bit is "0" and the lower timing is "1", so it is shifted by 1 bit and the next bit is higher. , 2 because the lower timing is "1"
Bit shift is performed, and then, both are shifted by 2 by "1". 15 S that compose the loop register 2
Since the EL / FFs 5a to 5o operate as shift registers, the contents of the flip-flops are the same except that the pattern phases are different. However, in FIG. 3, as an example, the 14th and 15th bit SEL / FF 5n, The outputs from 5o are inverted by inverters 6 and 7, respectively, and output to the pattern alignment circuit 3 as two serial PRBS patterns 2a.

In this way, the PRBS pattern generated in this way becomes a higher-order pattern because the pattern output from the inverter 6 (output from the 15th bit SEL / FF 5o) is higher, and is output from the inverter 7. The pattern (output from the 14th bit SEL / FF 5n) is a lower pattern. The point to note here is
The PRBS pattern generator of FIG.
The PRBS pattern can be generated every 2 bits in accordance with the above. However, when the pattern is generated by only 1 bit, the generated pattern is always 15 regardless of whether the pattern is assigned to the upper pattern or the lower pattern.
This is the point to be output to the SEL / FF 5o of the bit.

Next, the detailed circuit configuration of the pattern alignment circuit 3 is shown in FIG. The pattern alignment circuit 3 includes a gate circuit 10 for allocating the PRBS pattern generated by the loop register 2 to upper and lower levels, and a 3-bit shift register for accumulating the bits of the PRBS pattern allocated to the upper level (hereinafter, upper level save). Register) 14
And a 3-bit shift register (hereinafter referred to as a lower save register) 15 for accumulating bits of the PRBS pattern distributed to the lower order, and a sampling register 16 composed of eight flip-flops for finally sampling the 8-bit PRBS pattern. Composed. here,
The PRBS pattern assigned to the higher rank is called a higher rank pattern, and the PRBS pattern assigned to the higher rank is called a higher rank pattern.

The gate circuit 10 described above uses the loop register 2 and the upper timing of the serial timing signal 1b.
AND gate 12 to which the upper pattern output from is input, and the upper and lower patterns output from the loop register 2, respectively, and the upper timing is "1".
, The lower pattern is output and the upper timing is "0".
In this case, the selector 11 outputs the upper pattern, and the AND gate 13 receives the lower timing of the serial timing signal 1b and the output of the selector 11, respectively.

Further, the gate circuit 10 operates based on the serial timing signal 1b, and its operation content is divided into four cases as shown in Table 3.

[Table 3] Hereinafter, each case in Table 3 will be described.

In the first case, the serial timing signal 1b is "1" for both the upper and lower timings. In this case, the gate circuit 10 outputs the upper pattern to the upper save register 14 and the lower pattern to the lower save register 15.
Output to In the second case, the upper timing is “1”,
In the case where the lower timing is “0”, in this case, the gate circuit 10 outputs the upper pattern to the upper save register 14 and outputs nothing to the lower save register 15.

In the third case, the serial timing signal 1
Upper timing of b is “0”, lower timing is “1”
In this case, in this case, the gate circuit 10 outputs the upper pattern to the lower save register 15 and outputs nothing to the upper save register 14. In the fourth case, the serial timing signal 1b is "0" for both upper and lower timings, and in this case, the gate circuit 10 outputs nothing to both the upper save register 14 and the lower save register 15.

In the gate circuit 10 operating in this way, the above-mentioned serial timing signal 1b and the serial PRBS are provided.
When the pattern 2a is input, both serial timing signals 1b are "0" at the 1st and 2nd bytes.
“0” is output from the gate 12 to the first-bit flip-flop FFH1 of the upper save register 14 and the flip-flop FF2 of the sampling register 16.
Similarly, from the AND gate 13 to the lower save register 15
"0" is also input to the first-bit flip-flop FFL1 and the flip-flop FF1 of the sampling register 16.

The first clock of the third byte operates in the same manner, but in the operation of the second clock, since the upper timing of the serial timing signal 1b is "0" and the lower timing is "1", the flip-flop FFH1 is operated. "0" is input, but the upper pattern of the serial PRBS pattern 2a is input to the flip-flop FFL1.

Further, in the operation of the third clock, since the serial timing signal 1b is "1" for both the upper and lower timings, the upper pattern of the serial PRBS pattern 2a is in the flip-flop FFH1 and the serial PRBS pattern is in the flip-flop FFL1. The lower order of 2a is input. At this time, the upper pattern input to the flip-flop FFL1 of the lower save register 15 at the second clock is shifted to the flip-flop FFL2 of the next bit.

In the operation of the fourth clock, the serial timing signal 1b is "1" in both upper and lower timings as in the third clock. Therefore, the upper and lower patterns of the serial PRBS pattern 2a are stored in the upper save register 14, respectively. It is input to the flip-flop FFH1 and the flip-flop FFL1 of the lower save register 15, and at the same time, to the FF2 and FF1 of the sampling register 16. Furthermore, the FF of the sampling register 16
8, FF6, FF4 are FFs of the upper save register 14
H3, FFH2, FFH1 are also FF7, FF5
FF3 includes FFL3 and FFL of the lower save register 15.
2, the pattern of FFL1 is input.

At this time, at the third clock, the upper pattern shifted to the flip-flop FFL2 of the lower save register 15 is shifted to the flip-flop FFL3, and the flip-flop F of the upper save register 14 is shifted.
The upper pattern input to FH1 and the lower pattern input to flip-flop FFL1 of lower save register 15 are shifted to flip-flop FFH2 and flip-flop FFL2, respectively.

At this time, in each of the flip-flops FF1 to FF8 of the sampling register 16, "0" is input to both the flip-flops FF8 and FF7, and "0" is input to the flip-flops FF6 and FF5 at the second clock. The upper pattern is the flip-flop FF
4, the upper pattern and the lower pattern input at the third clock are input to the flip-flop FF.
The upper pattern and the lower pattern input at the fourth clock are input to 2 and FF1, respectively.

As a result, when the 8 bits are collectively output from the flip-flops FF1 to FF8 of the sampling register 16 at the 4th clock, the PDH frame of 44736 Kbit / s is asynchronously mapped to the SDH frame of 155.52 Mbit / s. The PRBS pattern is inserted into the I bit of the third byte (RRCIIIII) in the frame structure. In this way, the PRBS pattern generated according to the 8-bit timing signal 1a is output from the sampling register 16 in the same 8-bit configuration as the timing signal 1a even in the fourth byte and thereafter.

[0052]

As described above, according to the present invention,
When the PDH frame is placed on the SDH frame and the line quality and data continuity test are performed, the ITU-T
The PRBS pattern can be placed on the information bits in the frame structure defined in G.709. Also, usually 8
In the case where a PRBS pattern is generated in any number of 8 bits of an SDH frame for which bit parallel processing is performed, a P speed equivalent to that of the conventional P P
An RBS pattern can be generated. This is very effective when the required operation speed exceeds the upper limit of the device used, for example, when the circuit operation cannot be realized by TTL or CMOS and the ECL circuit increases the circuit space and power consumption. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PRBS pattern generation block according to an embodiment of the present invention.

[Fig. 2] 44736 in SDH frame of 155.52 Mbit / s
It is an explanatory view for explaining a frame configuration when a PDH frame of Kbit / s is asynchronously mapped.

FIG. 3 is a circuit diagram showing a configuration of a loop register that generates a PRBS pattern of 32767 bits in FIG.

4 is a circuit diagram showing a configuration of a pattern alignment circuit in FIG.

FIG. 5: 139264 in the SDH frame of 155.52 Mbit / s
It is an explanatory view for explaining a frame configuration when a PDH frame of Kbit / s is asynchronously mapped.

FIG. 6 is an explanatory diagram showing a configuration of a loop register portion of a serial PRBS pattern generation block which is a conventional technique.

FIG. 7 is an explanatory diagram showing a configuration of a pattern generation portion of a conventional 8-bit parallel PRBS pattern generation circuit.

FIG. 8 is an explanatory diagram showing a configuration of a serial PRBS pattern generation block which is a conventional technique.

[Explanation of symbols]

 1 Timing conversion circuit 2 Loop register 3 Pattern alignment circuit 5a-5o Flip-flop with selector 6,7 Inverter 8,9 Exclusive OR 10 Gate circuit 11 Selector 12,13 AND gate 14 Upper save register 15 Lower save register 16 Sampling register

Claims (5)

[Claims] 1. Pseudo-random 2 having a plurality of output terminals and having a bit configuration based on an instruction from the outside at the plurality of output terminals.
In a pseudo-random binary sequence pattern generating method for generating a binary sequence pattern, a pseudo-random binary sequence pattern is sequentially generated in units of 1 bit or 2 bits based on an instruction from the outside, and the generated pseudo pattern is generated. A pseudo random binary sequence pattern generating method, wherein the random binary sequence pattern is rearranged into a bit configuration based on an instruction from the outside and is output. 2. Pseudo-random 2 having a plurality of output terminals and having a bit structure based on an instruction from the outside at the plurality of output terminals.
In a pseudo-random binary sequence pattern generator for generating a binary sequence pattern, pattern output means for sequentially outputting one or two bits of the pseudo-random binary sequence pattern based on an instruction from the outside, A pseudo random binary system sequence pattern generator, comprising: a bit configuration forming unit that rearranges the pseudo random binary sequence pattern output from the pattern output unit into a bit configuration based on an instruction from the outside. 3. The external instruction is such that each bit corresponds to each of the plurality of output terminals, and at each bit, a plurality of digital signals indicating whether a pseudo random binary sequence pattern should be present or not. The pattern output means includes a serial conversion means for serially converting the digital signal in 2-bit units, and a 2-bit signal output from the serial conversion means.
If both indicate that a pseudo-random binary sequence pattern should be present, a pseudo-random binary sequence pattern is generated in units of 2 bits, and one bit of the pseudo-random binary sequence pattern should be present. If this is indicated, 1 bit is pseudo-random 2
If a binary sequence pattern is generated and none of the bits indicates that the pseudo-random binary sequence pattern should be present, it should be composed of pattern generating means that does not generate the pseudo-random binary sequence pattern. The pseudo random binary sequence pattern generator according to claim 2. 4. The bit structure forming means is composed of a plurality of flip-flops, and has first and second shift registers for sequentially shifting input bit signals, and 2-bit output from the serial converting means. The first and second shift registers based on a signal,
Pattern output control means for controlling the output destination of the pseudo random binary sequence pattern output from the pattern output means, each flip-flop forming the first and second shift registers, and the pattern output control means. 4. The pseudo random binary sequence pattern generating device according to claim 3, wherein the pseudo random binary sequence pattern generating device is constituted by an output timing adjusting means for outputting the bit signal output from the device at a predetermined timing. 5. The pattern output control means, when the 2-bit signals output from the serial conversion means both indicate that a pseudo random binary sequence pattern should exist, the pattern output means. Of the 2-bit pseudo-random binary sequence pattern output from the above, outputs the upper bits to the first shift register and outputs the lower bits to the second shift register, If only the upper bits of the 2-bit signal output from the serial conversion means indicate that the pseudo-random binary sequence pattern should be present, the 1-bit output from the pattern output means The pseudo random binary sequence pattern is output to the first shift register, and the pseudo random binary sequence pattern is output. A bit signal indicating that there is no signal is output to the second shift register, and only the lower bit of the 2-bit signal output from the serial conversion means has a pseudo-random binary sequence pattern. If it indicates that the pseudo random binary sequence pattern exists, the 1-bit pseudo random binary sequence pattern output from the pattern output means is output to the second shift register. If a bit signal indicating that the pseudo random binary sequence pattern should not exist is output to the first shift register, and the 2-bit signal output from the serial conversion means does not indicate that a pseudo random binary sequence pattern should be present. , A bit signal indicating that a pseudo random binary sequence pattern does not exist, 6. The pseudo random binary sequence pattern generating device according to claim 4, wherein the pseudo random binary sequence pattern generating device outputs the same to each register.