JPH09321213A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09321213A JPH09321213A JP8137228A JP13722896A JPH09321213A JP H09321213 A JPH09321213 A JP H09321213A JP 8137228 A JP8137228 A JP 8137228A JP 13722896 A JP13722896 A JP 13722896A JP H09321213 A JPH09321213 A JP H09321213A
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor chip
- mounting portion
- resin
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路に
関し、特に半導体チップ等をプラスティック等の樹脂に
より封止する樹脂封止型の半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a resin-sealed semiconductor integrated circuit for sealing a semiconductor chip or the like with resin such as plastic.
【０００２】[0002]
【従来の技術】半導体装置は、一般に所望の電気的特性
を有するシリコンウェハーから取り出された半導体チッ
プをダイボンドし、ダイ上の電極とパッケージ上の電極
とを金線にてワイヤボンドし、実使用に供することが可
能な状態へと組み立てられる。これによって組立てられ
た半導体集積回路は、２１５〜２３０℃の高温処理を行
う実装の際に、アイランド，チップ，樹脂封止部は、熱
膨張係数が異なるため、チップの角から樹脂封止部の表
面にかけて、クラックが発生することがある。2. Description of the Related Art In general, a semiconductor device is actually used by die-bonding a semiconductor chip taken out from a silicon wafer having desired electrical characteristics and wire-bonding an electrode on the die and an electrode on the package with a gold wire. It is assembled into a state ready for use. In the semiconductor integrated circuit thus assembled, the thermal expansion coefficient of the island, the chip, and the resin encapsulation portion are different when the semiconductor integrated circuit is subjected to a high temperature treatment of 215 to 230 ° C. Cracks may occur on the surface.
【０００３】この対策として、従来の技術においては、
図４の（ａ），（ｂ）に示すように各リード２及び吊り
ピン３の所定の位置に、特定の温度になるとリード及び
吊りピンの面と垂直に所定の高さだけ突出した形状とな
る形状記憶合金製のフィン９を設けることで、樹脂封止
部７を形成する際に、１７０〜１８０℃という温度によ
り、フィン９がリード及び吊りピンに対し垂直に突出し
た形で封止される。これによって、半導体集積回路を実
装時に高温処理した場合、樹脂封止部とリード、チップ
の膨張に差があっても、フィン９によって膨張による横
ずれを軽減することが可能となっている（特開平４−２
９０２５３参照）。As a countermeasure against this, in the conventional technique,
As shown in FIGS. 4 (a) and 4 (b), at a predetermined position of each lead 2 and the hanging pin 3, when the temperature reaches a specific temperature, a shape protruding vertically by a predetermined height from the surface of the lead and the hanging pin is formed. By providing the fins 9 made of the shape memory alloy, the fins 9 are sealed by the temperature of 170 to 180 ° C. when the resin sealing portion 7 is formed so as to project vertically to the leads and the hanging pins. It Accordingly, when the semiconductor integrated circuit is subjected to high-temperature processing during mounting, even if there is a difference in expansion between the resin sealing portion, the lead, and the chip, the fin 9 can reduce lateral displacement due to expansion (Japanese Patent Laid-Open No. Hei 10 (1999) -31977). 4-2
90253).
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の技術に
おける問題点として、樹脂の充填差が生じてチップ上の
樹脂の流れが速い時は、アイランドが下に押し下げられ
て、樹脂封止部の裏面にアイランドが露出することがあ
る。その理由は、アイランドが吊りピンのみで支えられ
ており、垂直方向へ固定する手段がないため、樹脂の流
動によっては、アイランドが垂直方向へ自由に動き傾き
が生じるからである。As a problem in the above-mentioned conventional technique, when the resin filling difference occurs and the resin flow on the chip is fast, the island is pushed down and the resin sealing portion Islands may be exposed on the back side. The reason is that the island is supported only by the hanging pins and there is no means for fixing the island in the vertical direction, so that the island moves freely in the vertical direction and tilts depending on the flow of the resin.
【０００５】本発明の目的は、樹脂封止を行う際に、チ
ップ上のアイランド下の樹脂の充填差によって、アイラ
ンドが下側に押し下げられようとした場合、アイランド
が垂直方向（上下方向）にシフトおよび樹脂封止部より
露出するのを防ぐようにした半導体装置を提供すること
である。An object of the present invention is to carry out resin encapsulation in the case where the island is pushed down due to the difference in the resin filling under the island on the chip, the island moves vertically (up and down). It is an object of the present invention to provide a semiconductor device which is prevented from being exposed from the shift and the resin sealing portion.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
アイランドの下に切込部を有する形状記憶合金板（図１
（ａ）の４）が接着された構造となっており、この形状
記憶合金板は、特定の温度（１７０〜１８０℃）になる
と、切込部（図１（ａ）の５）がアイランドに垂直に下
側に所定の高さだけ突出した形状となる。According to the present invention, there is provided a semiconductor device comprising:
Shape memory alloy plate with notches under the island (Fig. 1
The shape memory alloy plate has a structure in which (4) of (a) is adhered, and when the shape memory alloy plate reaches a specific temperature (170 to 180 ° C.), the cut portion (5 of FIG. 1A) becomes an island. It has a shape that vertically projects downward by a predetermined height.
【０００７】樹脂封止時、ワイヤリングした組立済みの
本発明リードフレームを、封入金型にセットした際に、
封入金型の１７０〜１８０℃という温度によりアイラン
ドの下に接着された形状記憶合金の切込部がアイランド
に垂直に下側に突出した形状となる。これにより、樹脂
封止時の樹脂の流れがチップの上側とアイランドの下側
で不均等になって、チップ上側の樹脂がアイランドを押
し下げようとする力が加わっても、下側に突出した形状
記憶合金板の切込部が支柱となりアイランドのシフトを
防止することができる。At the time of resin sealing, when the wired and assembled lead frame of the present invention is set in an encapsulating mold,
Due to the temperature of 170 to 180 ° C. of the encapsulating mold, the notch of the shape memory alloy adhered below the island has a shape protruding vertically downward to the island. As a result, the resin flow at the time of resin sealing becomes uneven on the upper side of the chip and the lower side of the island, and even if the resin on the upper side of the chip applies a force to push down the island, the shape protruding downward The notch of the memory alloy plate serves as a pillar to prevent the island from shifting.
【０００８】[0008]
【発明の実施の形態】次に、本発明について図面を参照
して説明する。図１（ａ），（ｂ）は、それぞれ本発明
の一実施の形態のリードフレーム部分の平面図及び半導
体装置全体の断面図である。この実施の形態が図４
（ａ），（ｂ）に示された従来の半導体集積回路と相違
する点は、アイランド１の下に切込部５を有する形状記
憶合金板４を接着させている点にある。この形状記憶合
金板４は、特定の温度（１７０〜１８０℃）になると、
形状記憶合金板４の切込部５が、アイランド１およびリ
ード２に対して垂直に下側に突出した形状となる。Next, the present invention will be described with reference to the drawings. 1A and 1B are a plan view of a lead frame portion and a sectional view of the entire semiconductor device according to an embodiment of the present invention, respectively. This embodiment is shown in FIG.
The difference from the conventional semiconductor integrated circuit shown in (a) and (b) is that a shape memory alloy plate 4 having a notch 5 is bonded below the island 1. When the shape memory alloy plate 4 reaches a specific temperature (170 to 180 ° C.),
The notch 5 of the shape memory alloy plate 4 has a shape protruding downward to the island 1 and the leads 2 perpendicularly.
【０００９】このような切込部５を有する形状記憶合金
板４を設けた構造とすることにより、図２に示すように
樹脂封止部を形成する際に、１７０〜１８０℃という温
度により、切込部５がアイランド１およびリード２に対
し下側に垂直に突出した形で封止される。With the structure having the shape memory alloy plate 4 having the cut portion 5 as described above, when the resin sealing portion is formed as shown in FIG. The notch 5 is sealed so as to vertically project downward from the island 1 and the leads 2.
【００１０】その際に、従来であれば図３に示すよう
に、樹脂の充填差によって、チップ６の上側の樹脂の方
がアイランド１の下側の樹脂より充填速度が速いとき、
チップ６およびアイランド１が下側に傾いて、アイラン
ド１が樹脂封止部７の裏面より露出するようになる。し
かし、本発明の構造であれば、図１（ｂ）に示すよう
に、封入温度（１７０〜１８０℃）によって下側に突出
した形状記憶合金板４の切込部５が支柱となり、アイラ
ンド１およびチップ６が下側に傾くことを防止できる。At this time, in the conventional case, as shown in FIG. 3, when the resin on the upper side of the chip 6 has a higher filling speed than the resin on the lower side of the island 1 due to the difference in resin filling,
The chip 6 and the island 1 are tilted downward so that the island 1 is exposed from the back surface of the resin sealing portion 7. However, according to the structure of the present invention, as shown in FIG. 1B, the notch 5 of the shape memory alloy plate 4 protruding downward due to the sealing temperature (170 to 180 ° C.) serves as a pillar, and the island 1 It is possible to prevent the tip 6 from tilting downward.
【００１１】[0011]
【発明の効果】以上述べたように、本発明によれば、樹
脂封止を行う際に、樹脂の充填差が生じチップ上側の樹
脂がアイランドを押し下げようとしたときの内部変形お
よびアイランドの樹脂封止部の裏面への露出を防ぐこと
ができる。その理由は、アイランド下に設けられた形状
記憶合金の切込部が封入温度によってアイランドに垂直
に下側へ突出することでアイランドの垂直（下）方向へ
のシフトに対して支柱の役割をするからである。As described above, according to the present invention, when resin sealing is performed, a resin filling difference occurs and internal deformation occurs when the resin on the upper side of the chip tries to push down the island and the resin of the island. It is possible to prevent the back surface of the sealing portion from being exposed. The reason is that the notch of the shape memory alloy provided under the island protrudes downward perpendicularly to the island due to the encapsulation temperature, thereby acting as a pillar for shifting the island in the vertical (down) direction. Because.
【図１】（ａ），（ｂ）は本発明の一実施の形態のリー
ドフレーム部分の平面図及び全体の断面図である。1A and 1B are a plan view and a cross-sectional view of a lead frame portion according to an embodiment of the present invention.
【図２】本発明の一実施の形態のリードフレーム部分の
斜視図である。FIG. 2 is a perspective view of a lead frame portion according to the embodiment of the present invention.
【図３】従来の半導体装置の課題を説明するための断面
図である。FIG. 3 is a cross-sectional view illustrating a problem of a conventional semiconductor device.
【図４】（ａ），（ｂ）は従来の半導体装置の一例のリ
ードフレーム部分の平面図及び全体の断面図である。4A and 4B are a plan view and a cross-sectional view of a lead frame portion of an example of a conventional semiconductor device, respectively.
１ アイランド ２ リード ３ 吊りピン ４ 形状記憶合金板 ５ 形状記憶合金板切込部 ６ チップ ７ 樹脂封止部 ８ 金線 ９ フィン 1 Island 2 Lead 3 Hanging Pin 4 Shape Memory Alloy Plate 5 Shape Memory Alloy Plate Notch 6 Chip 7 Resin Sealing 8 Gold Wire 9 Fin
Claims (1)
搭載部を保持する吊りピン、及び複数のリードを備えた
リードフレームと、前記半導体チップ搭載部に搭載固定
された半導体チップと、この半導体チップの各電極と前
記複数のリードとをそれぞれ対応して接続する複数の金
属細線と、前記半導体チップ搭載部、半導体チップ、各
金属細線、吊りピンの所定の部分及び各リードの所定の
部分を内部に封入する樹脂封止部とを有する半導体装置
において、前記半導体チップ搭載部の裏面に、特定の温
度になると一部の切込部分が、前記半導体チップ搭載部
とほぼ垂直に所定の高さだけ下に突出した形状となる形
状記憶合金製の板を設けたことを特徴とする半導体装
置。1. A semiconductor chip mounting portion, a hanging pin for holding the semiconductor chip mounting portion, a lead frame having a plurality of leads, a semiconductor chip mounted and fixed to the semiconductor chip mounting portion, and a semiconductor chip of the semiconductor chip. A plurality of thin metal wires for connecting the respective electrodes and the plurality of leads to each other, the semiconductor chip mounting portion, the semiconductor chip, each thin metal wire, a predetermined portion of the hanging pin, and a predetermined portion of each lead inside. In a semiconductor device having an encapsulating resin encapsulation portion, a part of a cut portion is formed on a back surface of the semiconductor chip mounting portion at a predetermined height substantially perpendicular to the semiconductor chip mounting portion at a specific temperature. A semiconductor device comprising a plate made of a shape memory alloy having a protruding shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8137228A JPH09321213A (en) | 1996-05-30 | 1996-05-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8137228A JPH09321213A (en) | 1996-05-30 | 1996-05-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09321213A true JPH09321213A (en) | 1997-12-12 |
Family
ID=15193784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8137228A Pending JPH09321213A (en) | 1996-05-30 | 1996-05-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09321213A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006100738A1 (en) * | 2005-03-18 | 2006-09-28 | Fujitsu Limited | Semiconductor device and method for manufacturing same |
| JP2011029669A (en) * | 2010-11-08 | 2011-02-10 | Fujitsu Semiconductor Ltd | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05251618A (en) * | 1991-10-16 | 1993-09-28 | Oki Electric Ind Co Ltd | Resin seal semiconductor device |
| JPH0786322A (en) * | 1993-09-16 | 1995-03-31 | Hitachi Ltd | Semiconductor device |
-
1996
- 1996-05-30 JP JP8137228A patent/JPH09321213A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05251618A (en) * | 1991-10-16 | 1993-09-28 | Oki Electric Ind Co Ltd | Resin seal semiconductor device |
| JPH0786322A (en) * | 1993-09-16 | 1995-03-31 | Hitachi Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006100738A1 (en) * | 2005-03-18 | 2006-09-28 | Fujitsu Limited | Semiconductor device and method for manufacturing same |
| US7800210B2 (en) | 2005-03-18 | 2010-09-21 | Fujitsu Semiconductor Limited | Semiconductor device |
| JP2011029669A (en) * | 2010-11-08 | 2011-02-10 | Fujitsu Semiconductor Ltd | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101218673B (en) | Semiconductor device | |
| US5378924A (en) | Apparatus for thermally coupling a heat sink to a lead frame | |
| JPH09260575A (en) | Semiconductor device and lead frame | |
| JPH1167809A (en) | Semiconductor device | |
| JP2004179253A (en) | Semiconductor device and manufacturing method therefor | |
| US20020135076A1 (en) | Heat sink with collapse structure and semiconductor package with heat sink | |
| JP3151346B2 (en) | Semiconductor integrated circuit device, method of manufacturing the same, and mold used for the manufacture thereof | |
| JPH04269856A (en) | Lead frame; semiconductor integrated circuit device using it | |
| JP2002043494A (en) | Flattened plastic package module for integrated circuit | |
| JPH0547979A (en) | Resin-sealed semiconductor device | |
| JPH09321213A (en) | Semiconductor device | |
| JP2007096042A (en) | Semiconductor device | |
| US20200294896A1 (en) | Lead Frame Stabilizer for Improved Lead Planarity | |
| JP2003110080A (en) | Semiconductor device | |
| JP2007134395A (en) | Semiconductor device | |
| JP3565114B2 (en) | Resin-sealed semiconductor device | |
| JPH04340751A (en) | Plastic molded type semiconductor device | |
| KR0172020B1 (en) | Resin-sealed semiconductor device | |
| JPH09330992A (en) | Semiconductor device mounting body and its manufacture | |
| JP3305981B2 (en) | Semiconductor device | |
| JPS6132528A (en) | Manufacture of semiconductor device | |
| JPH08279575A (en) | Semiconductor package | |
| JPH0521649A (en) | Semiconductor device | |
| KR100729028B1 (en) | Lead frame of tape formation and semiconduct package using it | |
| JPH06244312A (en) | Semiconductor device and production method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980512 |