JPH09321182A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH09321182A JPH09321182A JP8157620A JP15762096A JPH09321182A JP H09321182 A JPH09321182 A JP H09321182A JP 8157620 A JP8157620 A JP 8157620A JP 15762096 A JP15762096 A JP 15762096A JP H09321182 A JPH09321182 A JP H09321182A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- epoxy
- resin composition
- resin
- silicone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高密度表面実装タ
イプの樹脂封止型半導体装置に関するものである。さら
に詳しくは、接着シール性と応力緩和性に優れた信頼性
の高い樹脂封止型半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high density surface mount type resin-sealed semiconductor device. More specifically, the present invention relates to a highly reliable resin-sealed semiconductor device having excellent adhesive sealing property and stress relaxation property.
【０００２】[0002]
【従来の技術】エレクトロニクス産業は著しい発展を遂
げ、様々な電子機器が工場、オフィス或いは家庭に入り
込んできている。これらの電子機器に対して、小型で高
性能しかも低価格のものが強く求められている。2. Description of the Related Art The electronics industry has made remarkable progress, and various electronic devices have been introduced into factories, offices or homes. There is a strong demand for small, high-performance and low-cost electronic devices.
【０００３】これに対応するため、半導体の素子の高集
積化やパッケージの軽薄短小化が進行してる。この結
果、半導体装置自身の強度が脆弱なものになってきてい
る。一方、基板搭載方法が、半導体全面が半田溶融温度
まで上昇する表面実装へと移行している。表面実装に於
いて、半田付け時に半導体素子に加わる応力は、非常に
大きなものである。そして、半導体を封止する樹脂組成
物に関しては、１ｍｍ以下の肉厚でも外部応力や環境変
化に対して動作不良や形状破壊を起こすことなく、正常
に機能を発揮する強靭性が求められている。しかし、現
状では、半田衝撃を受けた場合には半導体装置は何らか
の重大な欠陥を生じ、問題が多い。こうした背景から、
半導体装置の信頼性を飛躍的に高める事が要求されてい
る。In order to deal with this, high integration of semiconductor devices and miniaturization of packages have been advanced. As a result, the strength of the semiconductor device itself is becoming weak. On the other hand, the board mounting method is shifting to surface mounting in which the entire surface of the semiconductor rises to the solder melting temperature. In surface mounting, the stress applied to the semiconductor element during soldering is extremely large. A resin composition for encapsulating a semiconductor is required to have a toughness that normally functions without causing malfunction or shape destruction due to external stress or environmental change even if the thickness is 1 mm or less. . However, under the present circumstances, there are many problems that the semiconductor device causes some serious defects when it is subjected to solder impact. Against this background,
It is required to dramatically improve the reliability of semiconductor devices.
【０００４】本発明はこれらの要求を満足させる樹脂封
止型半導体装置を提供するものであり、ＭＣＭ、ＳＯ
Ｎ、ＢＧＡ、ＣＳＰ等と称せられる表面実装型超高密度
樹脂封止型半導体装置を提供するものである。The present invention provides a resin-encapsulated semiconductor device which satisfies these requirements.
The present invention provides a surface mount type super high density resin-encapsulated semiconductor device called N, BGA, CSP or the like.
【０００５】現在、半導体装置の封止方法は殆どが合成
樹脂組成物、特にエポキシ樹脂組成物を使用した樹脂封
止方法である。歴史的には、シリコーン樹脂組成物、次
にエポキシ・シリコーン樹脂組成物を使用した時代を経
て、１５年ほど前よりエポキシ樹脂組成物が実用化され
現在に至ってる。このエポキシ樹脂組成物はエポキシ樹
脂、及び硬化剤、充填剤、添加剤等より構成され優れた
接着性や耐熱性を有している。しかし、現状では衝撃緩
衝性能は不十分であり種々の改良が試みられている。At present, most of the semiconductor device encapsulation methods are resin encapsulation methods using a synthetic resin composition, particularly an epoxy resin composition. Historically, the epoxy resin composition has been put into practical use about 15 years ago after the era of using the silicone resin composition and then the epoxy-silicone resin composition. This epoxy resin composition is composed of an epoxy resin, a curing agent, a filler, an additive, etc., and has excellent adhesiveness and heat resistance. However, at present, the shock absorbing performance is insufficient and various improvements have been tried.
【０００６】過去のシリコーン樹脂組成物やエポキシ・
シリコーン樹脂組成物は、透水性を持つ、強度が低い等
の欠点を有していたため、耐湿性に優れ高強度のエポキ
シ樹脂組成物に取って代わられた。しかし、このエポキ
シ樹脂組成物も現在の厳しい表面実装時の半田付け時の
熱衝撃を受けた場合には、その保護機能は十分ではな
い。表面実装時の半田付け衝撃は、種々の致命的な問
題、例えば樹脂が膨張したり破壊したり、半導体素子が
正常に作動しない等の問題を起こし、半導体装置の信頼
性を著しくて低下させている。[0006] Past silicone resin compositions and epoxies
Since the silicone resin composition has drawbacks such as water permeability and low strength, it has been replaced by an epoxy resin composition having excellent moisture resistance and high strength. However, this epoxy resin composition also does not have a sufficient protection function when it is subjected to the current severe thermal shock during soldering during surface mounting. Soldering shock during surface mounting causes various fatal problems, such as resin swelling and destruction, semiconductor elements not operating properly, etc., and significantly lowers the reliability of semiconductor devices. There is.
【０００７】これらの問題解決のため改良も検討されて
きたが、未だに有効な手法は見つかっていない。改良検
討としては、シリ力を高充填させ熱膨張を小さくし応力
発生を抑えたり、エラストマー添加により弾性率を小さ
くし応力緩和を図ったり、疎水性樹脂を使用して、実装
加熱時の水蒸発による応力を低減する等が知られている
（特公昭６３−１２４８９、特開昭６２−１１６６５
４、特公昭６１−４８５４４）。Improvements have been studied to solve these problems, but no effective method has been found yet. Improvement studies include high filling of the shear force to reduce thermal expansion to suppress stress generation, addition of an elastomer to reduce the elastic modulus to reduce stress, and use of a hydrophobic resin to evaporate water during mounting heating. It is known to reduce the stress due to (Japanese Patent Publication No. 63-12489 and Japanese Patent Laid-Open No. 62-11665).
4, JP-B-61-48544).
【０００８】しかし、これら改良対策も重大欠点を有
し、更なる抜本的解決策が待たれている。即ち、低熱膨
張化のため球状シリカを高充填したり、低弾性率化のた
めにエラストマーを添加する手法では強度低下や水侵入
腐食の問題を生じる。特に、表面実装では水分の爆発的
な気化による急激な膨張が生じ、エポキシ樹脂組成物や
半導体素子が割れたり半導体素子が機能を果たさないと
いった重大な不良を起こす。However, these improvement measures also have serious drawbacks, and further drastic solutions are awaited. That is, in the method in which spherical silica is highly filled for low thermal expansion and an elastomer is added for low elastic modulus, problems of strength reduction and water penetration corrosion occur. In particular, surface mounting causes rapid expansion due to explosive vaporization of water, which causes serious defects such as cracking of the epoxy resin composition and semiconductor elements, or failure of the semiconductor elements to function.
【０００９】応力発生抑制法は、流動性に優れる球状シ
リカを高充填し低熱膨張化を図る手法であるが、球状シ
リカを使用すると界面剥離が生じ、強度低下や水侵入腐
食といった問題が生する。応力緩和法は、柔軟性に優れ
るシリコーンを用い低弾性率化を図る手法であるが、シ
リコーンは接着力が極めて弱いため、強度低下や水侵入
腐食の問題を生じる。シリカ手法に於いて、シリカ表面
をメカノケミカルにより改質する方法（特開平５−３３
５４４６）、シリコーン手法に関しては接着性の改良、
例えば反応性官能基の付与や樹脂変性等の改良が検討さ
れたが（特開昭６１−２８３６４９、特開平８−３４５
１）、官能基数が少なく接着力不足の問題、そして樹脂
変性では応力吸収セルが小さいため応力緩和効果が得ら
れないといった問題を発生した。特に、表面実装では水
分の気化により界面剥離が生じ、水侵入が原因で腐食を
招くことが問題となっている。つまり従来手法は剥離を
助長し、半導体の信頼性を劣化させるものである。The stress generation suppressing method is a method of highly filling spherical silica having excellent fluidity to achieve low thermal expansion, but when spherical silica is used, interfacial peeling occurs, and problems such as strength reduction and water intrusion corrosion occur. . The stress relaxation method is a method for achieving a low elastic modulus by using silicone having excellent flexibility, but since silicone has an extremely weak adhesive force, problems of strength reduction and water intrusion corrosion occur. In the silica method, a method of modifying the surface of silica by mechanochemicals (Japanese Patent Application Laid-Open No. 5-33)
5446), improved adhesion for silicone approaches,
For example, improvement of addition of reactive functional groups and modification of resin has been studied (JP-A-61-283649 and JP-A-8-345).
1), there are problems that the number of functional groups is small and the adhesive strength is insufficient, and that the stress relaxation effect cannot be obtained because the stress absorption cell is small when the resin is modified. Particularly, in surface mounting, there is a problem that vaporization of water causes interfacial peeling, which causes corrosion due to water intrusion. That is, the conventional method promotes peeling and deteriorates the reliability of the semiconductor.
【００１０】[0010]
【発明が解決しようとする課題】本発明は、エポキシ樹
脂組成物及びエポキシ・シリコーンエラストマー樹脂組
成物の２種類の樹脂で半導体素子を２層に封止すること
により、信頼性が高く高密度表面実装を実現する樹脂封
止型半導体装置を提供するものである。特に、応力緩和
性及び接着性に優れるエポキシ・シリコーンエラストマ
ー樹脂組成物を緩衝層として用いることにより半田衝撃
による半導体素子及び外部保護材の破壊を防ぎ、信頼性
が高く高密度表面実装を実現する樹脂封止型半導体装置
を提供するものである。SUMMARY OF THE INVENTION According to the present invention, a semiconductor element is sealed in two layers with two kinds of resins, an epoxy resin composition and an epoxy-silicone elastomer resin composition, to provide a highly reliable and high-density surface. Provided is a resin-sealed semiconductor device that realizes mounting. In particular, by using an epoxy-silicone elastomer resin composition that has excellent stress relaxation and adhesive properties as a buffer layer, it is possible to prevent damage to semiconductor elements and external protective materials due to solder impact, and to realize highly reliable, high-density surface mounting. An encapsulated semiconductor device is provided.
【００１１】[0011]
【課題を解決するための手段】本発明者は、エポキシ・
シリコーンエラストマー樹脂組成物に着目し、樹脂封止
型半導体装置につき鋭意研究し、本発明を完成させたの
である。即ち、本発明の要旨は、回路基板上に半導体素
子を直接搭載する方式の樹脂封止型半導体装置にして、
半導体装置のマウント材又はバンプが設けられる回路基
板側をエポキシ・シリコーンエラストマー樹脂組成物で
封止し、更に該封止部分をエポキシ樹脂組成物で封止し
たことを特徴とする２層樹脂封止型半導体装置である。The present inventor has found that
The present invention has been completed by paying attention to a silicone elastomer resin composition and earnestly researching a resin-encapsulated semiconductor device. That is, the gist of the present invention is to provide a resin-sealed semiconductor device in which a semiconductor element is directly mounted on a circuit board,
A two-layer resin encapsulation characterized in that a circuit board side on which a mount material or bumps of a semiconductor device is provided is encapsulated with an epoxy-silicone elastomer resin composition, and further the encapsulation part is encapsulated with an epoxy resin composition. Type semiconductor device.
【００１２】半導体素子の封止に使用する樹脂組成物で
あるエポキシ・シリコーンエラストマー樹脂組成物とし
ては、応力緩和性及び接着性に優れるものを使用する
が、エポキシ・シリコーンエラストマー樹脂組成物とし
て、９５〜５重量％のエポキシ樹脂、及び平均粒径が
０．１μｍ〜５０μｍで粒径分布に於いて粒径１００μ
ｍ以下が９５％以上であり、その表面に反応性官能基を
有し、その表層は硬度が針入度１５０ｍｍ以下かつＪＩ
ＳＡ４０度以下である柔軟性シリコーン及びその内部は
低熱膨張絶縁性物質からなる複合体にして、内部の比率
が１０〜９０重量％であるシリコーン系複合体５〜９５
重量％とから構成される組成物からなるものを使用する
のが好ましい。As the epoxy / silicone elastomer resin composition which is a resin composition used for sealing a semiconductor element, one having excellent stress relaxation property and adhesiveness is used. ~ 5% by weight of epoxy resin, and an average particle size of 0.1 µm to 50 µm and a particle size of 100 µ in the particle size distribution
m or less is 95% or more, has a reactive functional group on the surface, and the surface layer has a hardness of 150 mm or less and JI
Flexible silicone having an SA of 40 degrees or less and a silicone-based complex having an internal ratio of 10 to 90% by weight in the form of a complex composed of a low thermal expansion insulating material.
Preference is given to using those which consist of a composition which is composed by weight.
【００１３】更に、半導体素子の封止に使用する樹脂組
成物であるエポキシ・シリコーンエラストマー樹脂組成
物として好ましいのは、９５〜５重量％のエポキシ樹
脂、及び表面に反応性官能基を有し、平均粒径が０．０
１μｍから５０μｍで粒径分布に於いて粒径１００μｍ
以下が９５％以上であって、その硬度が針入度１５０ｍ
ｍ以下かつＪＩＳＡ４０度以下の柔軟性シリコーン５〜
９５重量％からなる樹脂組成物である。Further, as the epoxy / silicone elastomer resin composition which is a resin composition used for encapsulating a semiconductor element, 95 to 5% by weight of an epoxy resin and a surface having a reactive functional group are preferable. Average particle size 0.0
From 1 μm to 50 μm, 100 μm in particle size distribution
The following is 95% or more and the hardness is 150 m
Flexible silicone of m or less and JIS A of 40 degrees or less 5
The resin composition is 95% by weight.
【００１４】本発明の特徴は、半導体素子の樹脂封止
を、エポキシ樹脂組成物とエポキシ・シリコーンエラス
トマー樹脂組成物の２種類の樹脂組成物を使用して行
い、まず半導体装置のマウント材又はバンプが設けられ
る回路基板側をエポキシ・シリコーンエラストマー樹脂
組成物で封止し、更に該封止部分をエポキシ樹脂組成物
で封止した、２層の樹脂構造で封止した半導体装置にあ
る。The present invention is characterized in that a semiconductor element is sealed with a resin by using two kinds of resin compositions, an epoxy resin composition and an epoxy-silicone elastomer resin composition. Is a semiconductor device in which the circuit board side provided with is sealed with an epoxy-silicone elastomer resin composition, and the sealed portion is further sealed with an epoxy resin composition, which is sealed with a two-layer resin structure.
【００１５】半導体装置のエポキシ・シリコーンエラス
トマー樹脂組成物で封止した樹脂層の厚みは、マウント
材もしくはバンプより厚く、半導体素子より薄いものが
好ましい。この樹脂層の厚みは、半導体素子の厚みにも
依存するが、一般的には３ないし５００μｍであるのが
好ましい。又、半導体素子はＴＡＢ又はフリップチップ
方式で搭載されたものが好ましい。又、回路基板はフィ
ルム等の柔軟素材からできたものを使用することができ
る。The thickness of the resin layer sealed with the epoxy-silicone elastomer resin composition of the semiconductor device is preferably thicker than the mount material or bump and thinner than the semiconductor element. Although the thickness of this resin layer depends on the thickness of the semiconductor element, it is generally preferably 3 to 500 μm. Further, the semiconductor element is preferably mounted by a TAB or flip chip method. The circuit board may be made of a flexible material such as a film.
【００１６】これを、図に基づいて説明する。図２は、
従来のワイヤーボンデイング方式による半導体装置の一
例である。半導体素子１は、マウント材６を介して回路
基板２に搭載されて、素子からワイヤー３で基板電極５
に接続されている。この半導体装置を保護するため、樹
脂層４を設けている。一般的には、樹脂層４はエポキシ
樹脂組成物が使用される。これに対して、本発明の場合
は、図１に示したように、樹脂層が、樹脂層７と樹脂層
８の２層から構成される。即ち、マウント材のある回路
基板側に樹脂層７（以下、基板側樹脂層という）を設
け、この層はエポキシ・シリコーンエラストマー樹脂組
成物からなる。更に、その上部に設けられた樹脂層８
（以下、素子側樹脂層という）は、エポキシ樹脂組成物
からなる。This will be described with reference to the drawings. FIG.
It is an example of a semiconductor device according to a conventional wire bonding method. The semiconductor element 1 is mounted on the circuit board 2 via the mount material 6, and the element 3 is connected to the board electrode 5 by the wire 3.
It is connected to the. A resin layer 4 is provided to protect this semiconductor device. Generally, an epoxy resin composition is used for the resin layer 4. On the other hand, in the case of the present invention, as shown in FIG. 1, the resin layer is composed of two layers, the resin layer 7 and the resin layer 8. That is, a resin layer 7 (hereinafter referred to as a board-side resin layer) is provided on the side of the circuit board having the mount material, and this layer is made of an epoxy-silicone elastomer resin composition. Further, the resin layer 8 provided on the upper portion thereof
(Hereinafter, referred to as a device-side resin layer) is made of an epoxy resin composition.
【００１７】先に説明したように、基板側樹脂層の厚み
は、マウント材もしくはバンプより厚く、半導体素子よ
り薄いものが好ましく、半導体の厚みにも依存するが、
一般的には３ないし５００μｍであるのが好ましい。こ
の場合は、必然的に回路基板側樹脂層は半導体素子全体
を覆うことにはならない。基板側樹脂層の上部を更に素
子側樹脂層で封止することにより、半導体素子全体が、
樹脂層で覆われることになる。しかし、基板側樹脂層で
半導体素子を封止する場合、樹脂層が半導体素子全体を
覆う形で封止しても勿論よい。As described above, the thickness of the substrate-side resin layer is preferably thicker than the mount material or bump and thinner than the semiconductor element, and depends on the thickness of the semiconductor.
Generally, it is preferably 3 to 500 μm. In this case, the circuit board side resin layer does not necessarily cover the entire semiconductor element. By sealing the upper part of the substrate side resin layer with the element side resin layer, the entire semiconductor element is
It will be covered with a resin layer. However, when the semiconductor element is sealed with the substrate-side resin layer, the resin layer may of course be sealed so as to cover the entire semiconductor element.
【００１８】半導体素子を直接基板に搭載・接続する方
法は、ワイヤーボンデイング方式、ＴＡＢ方式及びフリ
ップチップ方式がある。ワイヤーボンデイング方式は、
素子電極と基板配線電極とを文字通りワイヤーで結線す
る方式であり、技術として長年の実績のある方式であ
る。ＴＡＢ方式は、配線を形成した長尺のフイルムキャ
リヤーテープに、半導体素子をいったん接続し、樹脂封
止後その周辺で打ち抜き、これを基板上に接続する方式
である。フリップチップ方式は、素子の電極に突起を設
け、基板電極と対向させた状態で相互の電極を接合する
方式である。There are a wire bonding method, a TAB method and a flip chip method as a method of directly mounting and connecting the semiconductor element on the substrate. The wire bonding method is
This is a method of literally connecting the element electrodes and the board wiring electrodes with wires, and is a method with a long-established track record as a technology. The TAB method is a method in which a semiconductor element is once connected to a long film carrier tape on which wiring is formed, and after resin sealing, punching is performed around the semiconductor element, and this is connected to a substrate. The flip-chip method is a method in which projections are provided on the electrodes of the device and the electrodes are joined together while facing the substrate electrodes.
【００１９】本発明の技術は半導体素子実装型半導体装
置全てに対して有効であるが、特に半導体素子をＴＡＢ
方式又はフリップチップ方式で搭載する半導体装置に対
して効力を発揮する。ＴＡＢ方式やフリップチップ方式
は、接合部が回路基板との接着面と電気接点の両機能を
持つため、応力により接合部が損傷を受けると重大な不
良を起こすからである。又、回路基板がフィルム状等の
薄い場合にも熱衝撃による変形が激しいので、本技術を
適用すると半導体装置に画期的な効果をもたらす。The technique of the present invention is effective for all semiconductor device mounting type semiconductor devices.
It is effective for semiconductor devices mounted by the method or flip chip method. This is because, in the TAB method and the flip-chip method, the joint portion has both functions of an adhesive surface to the circuit board and an electric contact, and if the joint portion is damaged by stress, a serious failure occurs. Further, even when the circuit board is thin such as a film, the deformation due to thermal shock is severe. Therefore, application of the present technology brings a revolutionary effect to the semiconductor device.
【００２０】次に、本発明で使用する樹脂組成物につい
て説明する。素子側樹脂組成物は、エポキシ樹脂、及び
硬化剤、充填剤、添加剤等より構成される。エポキシ樹
脂はビスフェノール型エポキシ樹脂等（日本化薬
（株）：ＥＰＰＮ等）、充填剤はシリカ等（電気化学工
業（株）：ＦＲ、ＦＢシリーズ等）、硬化剤はフェノー
ルノボラック樹脂等（明和化成（株）：ＨＰシリーズ
等）、硬化促進剤は有機リン化合物等（北興化学工業
（株）：ＴＰＰ等）、添加剤は難燃剤、染顔料等（三国
精錬（株）：アンチモン類，三菱化学（株）：カーボン
ブラック等）が一般的に使用される。又、使用する原料
類は高純度のものが良く、導電性異物や電解質は総量で
５０PPM以下、特に１０PPM以下が好ましい。Next, the resin composition used in the present invention will be described. The element-side resin composition is composed of an epoxy resin, a curing agent, a filler, an additive and the like. Epoxy resin is bisphenol type epoxy resin etc. (Nippon Kayaku Co., Ltd .: EPPN etc.), filler is silica etc. (Denki Kagaku Kogyo KK: FR, FB series etc.), curing agent is phenol novolac resin etc. (Meiwa Kasei) Co., Ltd .: HP series, etc., curing accelerators are organic phosphorus compounds, etc. (Hokuko Chemical Industry Co., Ltd .: TPP, etc.), additives are flame retardants, dyes and pigments, etc. (Mikuni Smelting Co., Ltd .: Antimonies, Mitsubishi Chemical). (Inc .: carbon black, etc.) is generally used. The raw materials used are preferably highly pure, and the total amount of conductive foreign matters and electrolytes is preferably 50 PPM or less, more preferably 10 PPM or less.
【００２１】基板側樹脂組成物として、基本的には応力
緩和性及び接着性に優れるものを使用する。なかでも、
エポキシ・シリコーンエラストマー樹脂組成物として、
９５〜５重量％のエポキシ樹脂、及び平均粒径が０．１
μｍ〜５０μｍで粒径分布に於いて粒径１００μｍ以下
が９５％以上であり、その表面に反応性官能基を有し、
その表層は硬度が針入度１５０ｍｍ以下かつＪＩＳＡ４
０度以下である柔軟性シリコーン及びその内部は低熱膨
張絶縁性物質からなる複合体にして、内部の比率が１０
〜９０重量％であるシリコーン系複合体５〜９５重量％
とから構成される組成物からなるものを使用することが
できる。As the substrate-side resin composition, a resin composition which is basically excellent in stress relaxation property and adhesiveness is used. Above all,
As an epoxy / silicone elastomer resin composition,
95 to 5 wt% epoxy resin, and an average particle size of 0.1
In the particle size distribution, the particle size of 100 μm or less is 95% or more, and the surface has a reactive functional group.
The surface layer has a hardness of 150 mm or less and JIS A4.
A flexible silicone having a temperature of 0 ° C. or less and the inside of the composite are made of a low thermal expansion insulating material, and the ratio of the inside is 10
~ 90 wt% silicone composite 5 to 95 wt%
It is possible to use a composition consisting of
【００２２】更に、基板側樹脂組成物として、９５〜５
重量％のエポキシ樹脂、及び表面に反応性官能基を有
し、平均粒径が０．０１μｍから５０μｍで粒径分布に
於いて粒径１００μｍ以下が９５％以上であって、その
硬度が針入度１５０ｍｍ以下かつＪＩＳＡ４０度以下の
柔軟性シリコーン５〜９５重量％からなる樹脂組成物も
使用することができる。Further, as the substrate side resin composition, 95 to 5
It has a weight% of epoxy resin, and has a reactive functional group on the surface, the average particle size is 0.01 μm to 50 μm, and the particle size distribution 100 μm or less is 95% or more, and the hardness is A resin composition composed of 5 to 95% by weight of flexible silicone having a degree of 150 mm or less and JIS A of 40 degrees or less can also be used.
【００２３】基板側樹脂組成物として使用するエポキシ
・シリコーンエラストマー樹脂組成物の主たる成分であ
る柔軟性シリコーン組成物であるが、その内部に低熱膨
張絶縁性物質を含有するものをシリコーン系複合体と称
し、内部に低熱膨張絶縁性物質を含有しないものと表現
上区別した。A flexible silicone composition, which is the main component of the epoxy-silicone elastomer resin composition used as the substrate-side resin composition, contains a low thermal expansion insulating material inside it as a silicone composite. The expression is distinguished from that which does not contain a low thermal expansion insulating material inside.
【００２４】更に、エポキシ・シリコーンエラストマー
樹脂組成物に、従来使用されている充填剤、硬化剤、硬
化促進剤及び添加剤等を混合使用してもよい。そして、
シリコーン系複合体又は柔軟性シリコーンの表面に存す
る反応性官能基が、エポキシ基、アルコキシ基、シラノ
ール基、ヒドロキシル基、アミノ基、又はアルコール基
からなる群から選ばれた少なくとも一種からなり、該官
能基の密度が２００〜３６０００ ｇ／当量の範囲にあ
ることが好ましい。又、シリコーン系複合体の内部に含
有する低熱膨張絶縁性物質は、その熱膨張率が１×１０
-4以下が好ましく、具体的には、酸化珪素、酸化アルミ
ニウム、窒化珪素、窒化アルミニウム、酸化マグネシウ
ム、酸化ベリリウム、酸化ジルコニウム及び窒化ホウ素
からなる群から選ばれた少なくとも一種の化合物であ
る。尚、当該樹脂組成物の詳細に関しては、本出願人の
特許出願（番号「平８−９６１８７」及び「平８ー９６
２６６」）に記載している。Further, conventionally used fillers, curing agents, curing accelerators and additives may be mixed and used in the epoxy / silicone elastomer resin composition. And
The reactive functional group present on the surface of the silicone-based complex or the flexible silicone comprises at least one selected from the group consisting of an epoxy group, an alkoxy group, a silanol group, a hydroxyl group, an amino group, or an alcohol group. The density of the group is preferably in the range of 200 to 36000 g / equivalent. Further, the low thermal expansion insulating substance contained in the silicone-based composite has a coefficient of thermal expansion of 1 × 10 5.
-4 or less is preferable, and specifically, at least one compound selected from the group consisting of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, magnesium oxide, beryllium oxide, zirconium oxide, and boron nitride. In addition, regarding the details of the resin composition, a patent application of the present applicant (No. “Hair 8-96187” and “Heir 8-96”)
266 ”).
【００２５】シリコーン系複合体は、以下の方法で製造
することができる。まず、低熱膨張絶縁性物質の表面を
化学的手段若しくは物理的手段により活性化する。例え
ば、酸化珪素等の低熱膨張絶縁性物質を弗酸等の強酸で
洗浄したり、或いはターボミルで粉砕する。これらの過
程に於いて酸化珪素等の低熱膨張絶縁性物質は、その表
面のＯＨ基等の官能基が増加する。こうして表面が活性
化した酸化珪素等の低熱膨張絶縁性物質の存在下に、反
応性官能基を２個有するアルコキシシランをポリシロキ
サンの存在下又は不存在下に重合させ、酸化珪素等の表
層にシリコーン重合体を形成せしめる。又、この際ポリ
シロキサンを、反応性官能基２個以上有するアルコキシ
シラン類の存在下又は不存在下に重合させても良い。The silicone composite can be manufactured by the following method. First, the surface of the low thermal expansion insulating material is activated by chemical means or physical means. For example, a low thermal expansion insulating material such as silicon oxide is washed with a strong acid such as hydrofluoric acid, or pulverized with a turbo mill. In these processes, the functional group such as OH group on the surface of the low thermal expansion insulating material such as silicon oxide increases. In this manner, an alkoxysilane having two reactive functional groups is polymerized in the presence or absence of polysiloxane in the presence of a low thermal expansion insulating substance such as silicon oxide whose surface is activated, to form a surface layer such as silicon oxide. Form a silicone polymer. At this time, the polysiloxane may be polymerized in the presence or absence of alkoxysilanes having two or more reactive functional groups.
【００２６】又、柔軟性シリコーンは、次の方法で得る
ことができる。シリコーンは、もともと反応性官能基を
有するシリコーンを用いても良いし、別途調製しても良
い。別途調製するためには、まずシリコーンを弗酸水等
で処理するか、或いは高速擂塊機にて破断処理して、シ
リコーンの表面を活性化しＯＨ基等の数を増加せしめ、
活性化したシリコーンに、反応性官能基を有するアルコ
キシシランを反応させるのである。The flexible silicone can be obtained by the following method. As the silicone, a silicone having a reactive functional group may be used originally, or may be prepared separately. To prepare separately, first treat the silicone with hydrofluoric acid water or the like, or rupture it with a high-speed kneading machine to activate the surface of the silicone and increase the number of OH groups, etc.
The activated silicone is reacted with an alkoxysilane having a reactive functional group.
【００２７】シリコーン系複合体の内部に含有する低熱
膨張絶縁性物質は、その粒径は出来るだけ小さい方が好
ましい。特にフリップチップ方式に於いては、バンプ自
身の大きさが小さいので、半導体素子と回路基板との間
の距離が必然的に小さくなるので、絶縁性物質の粒径は
小さいものが好ましい。The low thermal expansion insulating material contained in the silicone-based composite preferably has a particle size as small as possible. Particularly in the flip chip method, since the size of the bump itself is small, the distance between the semiconductor element and the circuit board is inevitably small. Therefore, it is preferable that the particle diameter of the insulating material is small.
【００２８】シリコーン系複合体又は柔軟性シリコーン
は、その粒径が重要である。即ち、平均粒径が５０μｍ
以下で、粒径分布に於いて粒径１００μｍ以下が９５％
以上であるものが好ましい。シリコーン系物質の粒径が
大きすぎると、局部応力が発生し好ましくない（電子通
信学会 昭和６０年度講演要旨集）。フリップチップ方
式で搭載する場合は、バンプ材の寸法以下の粒径のもの
が９５％以上であることが好ましい。特に好ましいの
は、粒径５０μｍ以下のものの比率が９５％以上で、か
つ粒径がバンプ材の寸法よりも小さいものの比率が９５
％以上のものである。又、シリコーン系複合体又は柔軟
性シリコーンの使用量は、５〜９５重量％、特に２０〜
８５重量％が好ましい。使用量が少ないと、応力緩和効
果が得られないし、使用量が多いと硬化性で問題を起こ
す場合があるからである。本発明に於いて、粒径は、島
津製作所製「島津レーザ式粒度分布測定装置 ＳＡＬＤ
−３２０００」を使用して測定した。The particle size of the silicone-based composite or flexible silicone is important. That is, the average particle size is 50 μm
95% of particle size distribution is 100 μm or less.
Those described above are preferred. If the particle size of the silicone-based material is too large, local stress is generated, which is not desirable (Abstracts of the Presentation at the 1985 IEICE). When mounting by the flip chip method, it is preferable that 95% or more of the particles have a grain size equal to or smaller than the size of the bump material. Particularly preferably, the ratio of particles having a particle size of 50 μm or less is 95% or more, and the ratio of particles having a particle size smaller than the size of the bump material is 95%.
% Or more. The amount of the silicone-based composite or flexible silicone used is 5 to 95% by weight, particularly 20 to
85% by weight is preferred. This is because if the amount used is small, the stress relaxation effect cannot be obtained, and if the amount used is large, a problem may occur in curability. In the present invention, the particle size is “Shimadzu laser particle size distribution analyzer SALD” manufactured by Shimadzu Corporation.
-32000 ".
【００２９】回路基板に使用する材質は、柔軟性を有す
るものも使用することができる。材料としては ,ポリエ
ステル、エポキシ又はポリイミドが使用される。耐熱性
の点では、ポリイミドが特に好ましい。小型化や薄型化
が強く求められる機器、分野に於いては、柔軟性を有す
る基板が好ましい。The material used for the circuit board may be flexible. As the material, polyester, epoxy or polyimide is used. From the viewpoint of heat resistance, polyimide is particularly preferable. A flexible substrate is preferable in a device or field in which miniaturization and thinning are strongly required.
【００３０】本発明のエポキシ・シリコーンエラストマ
ー樹脂組成物は、エポキシ樹脂組成物との接着性に優れ
ているので、封止用樹脂組成物を２層使用しても、その
界面で接着が破壊することはない。半田付けの際、熱衝
撃を最も受けるのは半導体が回路基板に搭載されている
周辺である。特に、フリップチップ方式に於いては、半
導体素子がバンプで回路基板と接続されている。この接
着点が小さいため、半田付け時の熱衝撃を大きく受け
る。従って、この部分の応力を緩和させることが重要で
ある。この点、本発明のエポキシ・シリコーンエラスト
マー樹脂組成物は、応力緩和特性に優れ、応力緩衝層と
して作用し、半田付け等の熱衝撃にも耐えることが可能
となる。Since the epoxy-silicone elastomer resin composition of the present invention has excellent adhesiveness with the epoxy resin composition, even if two layers of the encapsulating resin composition are used, the adhesion is broken at the interface. There is no such thing. When soldering, it is the periphery where the semiconductor is mounted on the circuit board that is most subject to thermal shock. Particularly in the flip-chip method, the semiconductor element is connected to the circuit board by bumps. Since this bonding point is small, it receives a large thermal shock during soldering. Therefore, it is important to relax the stress in this portion. In this respect, the epoxy-silicone elastomer resin composition of the present invention has excellent stress relaxation characteristics, acts as a stress buffer layer, and can withstand thermal shock such as soldering.
【００３１】又、エポキシ・シリコーンエラストマー樹
脂組成物の上部は耐湿性及び強度特性で実績のあるエポ
キシ樹脂組成物層により封止されているので、外的圧力
や水分の侵入に対して半導体素子を保護する。基板側樹
脂組成物で、半田付け時に生じる応力を緩和し、素子側
樹脂組成物で半導体装置を完全に封止しているので、理
想的な樹脂封止型半導体装置が得られるのである。同時
に、コスト面でも有利となるので、本発明の実用価値が
大きい。Further, since the upper part of the epoxy-silicone elastomer resin composition is sealed with the epoxy resin composition layer which has a proven track record of moisture resistance and strength characteristics, the semiconductor element is protected against external pressure and moisture intrusion. Protect. Since the board-side resin composition relieves the stress generated during soldering and the element-side resin composition completely seals the semiconductor device, an ideal resin-sealed semiconductor device can be obtained. At the same time, it is advantageous in terms of cost, so that the practical value of the present invention is great.
【００３２】本発明のエポキシ・シリコーンエラストマ
一樹脂組成物は、エポキシ樹脂組成物及び回路基板と接
着し界面を一体化させることにより、水の侵入を防止す
る。更に、外部応力を受けた場合には、エポキシ・シリ
コーンエラストマ一樹脂組成物自身の変形により応力を
緩和するだけでなく、直ちに元の形状に戻り界面破壊を
防ぐのである。つまり本発明により接着シール性と応力
緩和性に優れた信頼性の高い半導体装置が得られること
になる。The epoxy / silicone elastomer resin composition of the present invention prevents water from entering by adhering to the epoxy resin composition and the circuit board and integrating the interface. Further, when an external stress is applied, not only the stress is relieved by the deformation of the epoxy-silicone elastomer-resin composition itself, but also the original shape is immediately restored to prevent the interface destruction. That is, according to the present invention, a highly reliable semiconductor device having an excellent adhesive sealing property and stress relaxation property can be obtained.
【００３３】[0033]
【発明の実施の形態】次に、本発明の半導体装置の実施
形態を具体的に説明する。Next, embodiments of the semiconductor device according to the present invention will be described in detail.
【００３４】半導体装置は、半導体素子を回路基板に装
着し回路を形成したものであるが、半導体素子の搭載方
法によって種々の形態がある。その一つがワイヤーボン
デイング方式である。この方式については、図２に示し
たように、半導体素子１が、マウント材６を介して回路
基板２に搭載されて、素子からワイヤー３で基板電極５
に接続されている形態のものである。半導体装置を保護
するため、一般的には樹脂層４が設けられる。表面実装
を行うときに、樹脂層４と半導体素子１は、いわゆる半
田衝撃を受ける。この衝撃は、特に半導体素子が回路基
板と接触しているマウント材周辺が最も大きい。この観
点から、本発明では半田衝撃の最も大きい部分即ちマウ
ント材を中心とする部分を封止するのに、緩和性能と接
着性能に優れたエポキシ・シリコーンエラストマー樹脂
組成物を使用するものである。A semiconductor device is one in which a semiconductor element is mounted on a circuit board to form a circuit, but there are various forms depending on the mounting method of the semiconductor element. One of them is the wire bonding method. Regarding this method, as shown in FIG. 2, the semiconductor element 1 is mounted on the circuit board 2 through the mount material 6, and the substrate electrode 5 is connected to the circuit board 2 by the wire 3 from the element.
Is connected to the. A resin layer 4 is generally provided to protect the semiconductor device. During surface mounting, the resin layer 4 and the semiconductor element 1 are subjected to so-called solder impact. This impact is greatest especially around the mount material where the semiconductor element is in contact with the circuit board. From this point of view, the present invention uses an epoxy-silicone elastomer resin composition having excellent relaxation performance and adhesive performance to seal a portion having the largest solder impact, that is, a portion centering on the mount material.
【００３５】図１に於いて、半導体素子１がマウント材
６を介して回路基板２と接触しているが、このマウント
材６を中心としてエポキシ・シリコーンエラストマー樹
脂組成物層７で封止する。この樹脂組成物層の厚さは、
半導体素子全体を覆うものでもよいが、マウント材より
も厚く、半導体素子よりも薄いものが好ましい。更に、
該樹脂組成物層７の周辺部分を、エポキシ樹脂組成物層
８で封止する。本発明は、封止樹脂層が２層から構成さ
れ、マウント材を中心とする部分をエポキシ・シリコー
ンエラストマー樹脂組成物層７で封止し、更に、その周
辺部をエポキシ樹脂組成物層８で封止するものである。In FIG. 1, the semiconductor element 1 is in contact with the circuit board 2 through the mount material 6, and the mount material 6 is used as the center for sealing with the epoxy-silicone elastomer resin composition layer 7. The thickness of this resin composition layer is
Although it may cover the entire semiconductor element, it is preferably thicker than the mount material and thinner than the semiconductor element. Furthermore,
The peripheral portion of the resin composition layer 7 is sealed with an epoxy resin composition layer 8. In the present invention, the encapsulating resin layer is composed of two layers, the part centering on the mount material is encapsulated with the epoxy-silicone elastomer resin composition layer 7, and the peripheral part thereof is further encapsulated with the epoxy resin composition layer 8. It is to be sealed.
【００３６】次に、ＴＡＢ方式の半導体素子搭載形態の
ものについて説明する。図３に、ＴＡＢ方式に於ける本
発明の半導体装置の実施例形態の一例を示した。半導体
素子１は、バンプ１０を介してリード線９に接続されか
つその上部にフレキシブル回路基板１１が設けられてい
る。ここに於いて、バンプ１０は、回路の接点であると
同時に半導体素子を保持する役割を果たすものである。
半導体素子１自身は、回路基板２に直接に固定されず、
リード線９を介してフレキシブル回路基板１１に保持さ
れている。表面実装時、バンプ１０部分が半田衝撃を最
も大きく受けるが、半田衝撃を最も大きく受けるこの部
分を、エポキシ・シリコーンエラストマー樹脂組成物層
７で封止することが、本発明のポイントである。Next, a TAB type semiconductor element mounting form will be described. FIG. 3 shows an example of the embodiment of the semiconductor device of the present invention in the TAB method. The semiconductor element 1 is connected to the lead wire 9 via the bump 10 and the flexible circuit board 11 is provided on the lead wire 9. Here, the bump 10 serves as a contact point of a circuit and at the same time plays a role of holding a semiconductor element.
The semiconductor element 1 itself is not directly fixed to the circuit board 2,
The flexible circuit board 11 is held via the lead wires 9. At the time of surface mounting, the bump 10 portion is most subjected to the solder impact, and the point of the present invention is to seal this portion most subjected to the solder impact with the epoxy-silicone elastomer resin composition layer 7.
【００３７】図３に於いて、半導体素子１はリード線９
に接続されかつその上部のフレキシブル基板１１に保持
されている。半導体装置のバンプ１０を中心とする部分
を、まずエポキシ・シリコーンエラストマー樹脂組成物
層７で封止する。次に、エポキシ・シリコーンエラスト
マー樹脂組成物層７で封止した部分の周辺部を、エポキ
シ樹脂組成物層８で封止する。この場合は、ワイヤーボ
ンデイング方式とは異なり、半導体素子は、回路基板２
には固定されないので、エポキシ・シリコーンエラスト
マー樹脂組成物層７の下部を、エポキシ樹脂組成物層８
で封止することになる。In FIG. 3, the semiconductor element 1 has a lead wire 9
And is held by the flexible substrate 11 above it. A portion of the semiconductor device centering on the bump 10 is first sealed with an epoxy / silicone elastomer resin composition layer 7. Next, the periphery of the portion sealed with the epoxy-silicone elastomer resin composition layer 7 is sealed with the epoxy resin composition layer 8. In this case, unlike the wire bonding method, the semiconductor element is the circuit board 2
Since it is not fixed to the epoxy-silicone elastomer resin composition layer 7,
Will be sealed with.
【００３８】図３に於いて、樹脂層８は素子１の最下部
を被覆していないものになっているが、これに限定され
るものではない。素子１の最下部を含めて素子１全体を
樹脂層８で封止できることは言うまでもない。In FIG. 3, the resin layer 8 does not cover the lowermost portion of the element 1, but the present invention is not limited to this. It goes without saying that the entire element 1 including the lowermost portion of the element 1 can be sealed with the resin layer 8.
【００３９】図４は、フリップチップ方式に於ける、本
発明の実施例形態の一例を示したものである。この場
合、半導体素子１は、バンプ１０を介して回路基板２に
固定されている。この場合も、バンプ部分が最も半田衝
撃を大きく受ける。従って、この部分を、エポキシ・シ
リコーンエラストマー樹脂組成物層７でまず封止する。
次に、該封止部分の周辺部を、エポキシ樹脂組成物層８
で封止する。基板側樹脂層７の厚さは、半導体素子１よ
りも薄く、半導体素子１と回路基板２の接合部であるバ
ンプ１０よりも厚くすることが好ましい。基板側樹脂層
の厚さが、バンプよりも薄いと、応力緩和が不足し、厚
すぎると熱膨張差による応力が大きくなりやすいのはい
ずれの場合も同様である。FIG. 4 shows an example of the embodiment of the present invention in the flip chip system. In this case, the semiconductor element 1 is fixed to the circuit board 2 via the bump 10. Also in this case, the bump portion is most subjected to the solder impact. Therefore, this portion is first sealed with the epoxy-silicone elastomer resin composition layer 7.
Next, the peripheral portion of the sealing portion is covered with the epoxy resin composition layer 8
Seal with. The thickness of the board-side resin layer 7 is preferably smaller than that of the semiconductor element 1 and larger than that of the bump 10, which is a joint between the semiconductor element 1 and the circuit board 2. In any case, if the substrate-side resin layer is thinner than the bumps, stress relaxation is insufficient, and if it is too thick, the stress due to the difference in thermal expansion tends to increase.
【００４０】以下、本発明の半導体封止用の樹脂組成物
を、実施例に基づいて説明する。The resin composition for semiconductor encapsulation of the present invention will be described below based on Examples.
【実施例１、比較例１〜７】 １．シリコーン系複合体（１）の調製 酸化珪素粉末（龍森（株）製品 品番ＲＤ−８）をター
ボミルで粉砕した。粉砕した酸化珪素粉末を乳化器に投
入し、これに末端ＯＨ基のジメチルシリコーンオイル
（信越化学工業（株）製品 品番ＲＦ−７００）、ジメ
チルジメトキシシラン（信越化学工業（株）製品 品番
ＫＢＭ−２２）、及びメチルトリメトキシシラン（信越
化学工業（株）製品 品番ＫＢＭ−１３）を重量比１
０：１０：１の割合にて混合したものを酸化珪素粉末に
対し３０重量％の割合で添加し、８０℃で１５分間混練
した。更に、流動乾燥機に於いて１２０℃で１時間処理
し、その後篩別した。この結果、酸化珪素粉末を内部に
有し、その表層にメトキシ基を有するシリコーンが形成
されたシリコーン複合体１を得た。[Example 1, Comparative Examples 1 to 7] 1. Preparation of Silicone Composite (1) Silicon oxide powder (Tatsumori Co., Ltd. product No. RD-8) was pulverized with a turbo mill. The crushed silicon oxide powder is put into an emulsifier, and dimethyl silicone oil having a terminal OH group (Shin-Etsu Chemical Co., Ltd. product No. RF-700), dimethyldimethoxysilane (Shin-Etsu Chemical Co., Ltd. product No. KBM-22). ), And methyltrimethoxysilane (product number KBM-13, manufactured by Shin-Etsu Chemical Co., Ltd.) in a weight ratio of 1
The mixture mixed at a ratio of 0: 10: 1 was added at a ratio of 30% by weight to the silicon oxide powder, and kneaded at 80 ° C. for 15 minutes. Further, it was treated in a fluidized dryer at 120 ° C. for 1 hour and then sieved. As a result, a silicone composite 1 having silicon oxide powder inside and having methoxy group-containing silicone formed on the surface thereof was obtained.
【００４１】得られたシリコーン系複合体１は、平均粒
径は８μｍ、粒径１００μｍ以下の比率が９９．９％以
上、表層部の硬度は針入度で１０ｍｍであった。又、シ
リコーン系複合体１はメトキシ基を１０００ｇ／当量有
していた。表層部に形成されたシリコーン部は３０％で
あった。尚、粒径は、島津製作所製「島津レーザ式粒度
分布測定装置 ＳＡＬＤ−３２０００」を使用して測定
した。粒径分布つまり１００μｍ以下の比率は、得られ
た粒度度数分布図に於ける、１００μｍ以下の粒度の割
合を面積の比率として求めた。又、平均粒径は、粒度累
積分布図に於ける５０％を占める粒径として求めた。The obtained silicone-based composite 1 had an average particle size of 8 μm, a ratio of particle sizes of 100 μm or less was 99.9% or more, and the hardness of the surface layer portion was 10 mm in terms of penetration. Further, the silicone-based composite 1 had 1000 g / equivalent of methoxy groups. The silicone portion formed on the surface layer portion was 30%. The particle size was measured using "Shimadzu laser particle size distribution analyzer SALD-32000" manufactured by Shimadzu Corporation. For the particle size distribution, that is, the ratio of 100 μm or less, the ratio of the particle size of 100 μm or less in the obtained particle size distribution chart was determined as the area ratio. Further, the average particle size was obtained as a particle size occupying 50% in the particle size cumulative distribution chart.
【００４２】２．半導体封止用樹脂組成物（Ａ）の調製 先に調製したシリコーン系複合体１に、表１に示したエ
ポキシ樹脂、硬化促進剤、難燃剤、処理剤、顔料を混合
し、６０℃の温度で１５分間加熱真空乳化器を使用して
混練し基板側樹脂層用の樹脂組成物Ａを得た。2. Preparation of resin composition (A) for semiconductor encapsulation The epoxy resin, the curing accelerator, the flame retardant, the treating agent and the pigment shown in Table 1 are mixed with the silicone-based composite 1 prepared above, and the temperature is 60 ° C. And was kneaded for 15 minutes using a heating vacuum emulsifier to obtain a resin composition A for a substrate-side resin layer.
【００４３】[0043]
【表１】 [Table 1]
【００４４】尚、使用物質の内容は、次の通りである。 エホ゜キシ樹脂 ＲＥ−３０４Ｓ ：ビスフェノールＦ型エポキシ樹脂 ＹＸ−４０００Ｈ：ビス（ジメチルグリシジルオキシフェニール ） ＥＰＰＮ−５０１：多官能型エポキシ樹脂 硬化臓進剤 アルミキレートＡ：アルミニウムアセチルアセトネート ＴＰＰ ：トリフェニールホスフィン 難燃剤 ＢＲＥＮ−３０１：臭素化フェノールノボラック型エポキシ樹脂 処理剤 ＫＢＭ−３０３ ：β（エポキシシクロヘキシル）エチルトリメ トキシシラン 顔料 ＃４５ ：カーボンブラックThe contents of the substances used are as follows. Epoxy resin RE-304S: Bisphenol F type epoxy resin YX-4000H: Bis (dimethylglycidyloxyphenyl) EPPN-501: Polyfunctional epoxy resin Curing promoter Aluminum chelate A: Aluminum acetylacetonate TPP: Triphenylphosphine flame retardant BREN-301: Brominated phenol novolac type epoxy resin treatment agent KBM-303: β (epoxycyclohexyl) ethyltrimethoxysilane pigment # 45: carbon black
【００４５】３．半導体封止効果の評価 次に、上記樹脂組成物Ａを基板側樹脂層に使用し、エポ
キシ樹脂組成物を素子側樹脂組成物に使用して、模擬半
導体素子を封止しその信頼性（密着性、耐衝撃性、腐食
性）を評価した。結果は、表２に示した。同時に、封止
用樹脂組成物が１層の場合、及び封止用樹脂層が２層の
場合であって基板側樹脂組成物として、エポキシ・シリ
コーンエラストマー樹脂組成物を使用しないケースを比
較例として加えた。3. Evaluation of semiconductor encapsulation effect Next, the resin composition A was used for the resin layer on the substrate side, and the epoxy resin composition was used for the resin composition on the element side to encapsulate the simulated semiconductor element and its reliability (adhesion). Property, impact resistance, and corrosiveness) were evaluated. The results are shown in Table 2. At the same time, a case where the encapsulating resin composition is one layer, and a case where the encapsulating resin layer is two layers and the epoxy-silicone elastomer resin composition is not used as the substrate-side resin composition is used as a comparative example. added.
【００４６】[0046]
【表２】 [Table 2]
【００４７】実施例及び比較例に使用したエポキシ樹脂
組成物は、次の通りである。 Ｂ：エポキシ樹脂組成物 北陸塗料（株）製品 チップ
コート１３２０ Ｃ：シリコーン樹脂組成物 信越化学工業（株）製品
ＫＭＣ−１０ Ｄ：エポキシ・シリコーン樹脂組成物 ダウコーニング
・シリコーン（株）製品 ＭＣ−６４５５ 又、半導体封止成型条件及び評価条件は、次の通りであ
る。 半導体封止成型条件：ドロッピング封止後オーブンで硬
化させた（Ｅ−１／１５０） 具体的には、最初にエポキシ・シリコーンエラストマー
樹脂組成物を半導体素子周りに適度の厚さにドロッピン
グし、硬化させた後エポキシ樹脂組成物をその上にドロ
ッピングさせて、２層の樹脂組成物層を形成せしめたThe epoxy resin compositions used in Examples and Comparative Examples are as follows. B: Epoxy resin composition Hokuriku Paint Co., Ltd. product Chip Coat 1320 C: Silicone resin composition Shin-Etsu Chemical Co., Ltd. product
KMC-10 D: Epoxy / Silicone Resin Composition Dow Corning Silicone Co., Ltd. MC-6455 Further, semiconductor encapsulation molding conditions and evaluation conditions are as follows. Semiconductor encapsulation molding conditions: Dropping encapsulation followed by curing in an oven (E-1 / 150) Specifically, first, the epoxy / silicone elastomer resin composition was dropped by a proper thickness around the semiconductor element and cured. After that, the epoxy resin composition was dropped onto the resin composition to form two resin composition layers.
【００４８】 評価条件： パッケージ：ＣＯＢ（フリップチップ方式）１０ｍｍL×１０ｍｍW×２ｍｍt 模擬素子 ：バンプ寸法 Φ３０μｍ 耐衝撃性テスト ４L×４W×０．４tｍｍ、ＳｉＮ膜、回路無し 腐食テスト ３L×３W×０．４tｍｍ、回路幅／間隔＝１０ ／１０μｍ 前処理 ：ＰＣＴ吸湿 １２５℃＊１００％＊２０ｈｒｓ ＋半田浸食 ２６０℃＊１０ｓｅｃ 評価方法 ：界面状態 超音波探傷機にて界面間隔を測定 界面は模擬素子と封止樹脂との界面である 耐衝撃テスト 前処理時のクラック発生数（＞５０μｍ） 検体２０個のうちクラックの発生した数 腐食テスト ＰＣＴ放置（１０００ｈｒｓ）後のアルミニウ ム回路腐食数 検体２０個のうち回路断線の発生した数 変形テスト 半導体装置を５０Ｋｇで押したときの変形 変形する場合は特性変動を起こすEvaluation conditions: Package: COB (flip chip method) 10 mm L × 10 mm W × 2 mm t Simulated element: Bump size Φ30 μm Impact resistance test 4 L × 4 W × 0.4 t mm, SiN film, no circuit Corrosion Test 3 L x 3 W x 0.4 t mm, circuit width / spacing = 10/10 μm Pretreatment: PCT moisture absorption 125 ° C * 100% * 20hrs + solder erosion 260 ° C * 10sec Evaluation method: Interface state For ultrasonic flaw detector The interface distance is measured by the interface between the simulated element and the sealing resin Impact resistance test Number of cracks generated during pretreatment (> 50 μm) Number of cracks in 20 specimens Corrosion test After PCT exposure (1000 hrs) Aluminum circuit corrosion number of the number of circuit breaks out of 20 specimens Deformation test Deformation when semiconductor device is pressed at 50 Kg Cause a characteristic change
【００４９】実施例１は、本発明に基づくものである。
比較例１は、回路基板側のエポキシ・シリコーンエラス
トマ一樹脂組成物の厚さが大きい場合、同２から４は１
層成形の場合、同５は基板側樹脂組成物がエポキシ・シ
リコーン樹脂組成物の場合、同６は、基板側樹脂組成物
がエポキシ樹脂組成物での比較例である。本発明の方法
で封止した装置が抜群の信頼性を示した。従来技術を使
用したものや本発明の請求範囲より外れたものは重大な
不良を発生した。Example 1 is based on the present invention.
In Comparative Example 1, when the thickness of the epoxy-silicone elastomer resin composition on the circuit board side is large, 2 to 4 are 1
In the case of layer molding, 5 is a comparative example in which the substrate-side resin composition is an epoxy-silicone resin composition, and 6 is a comparative example in which the substrate-side resin composition is an epoxy resin composition. The device sealed by the method of the present invention showed outstanding reliability. Those using the prior art and those outside the scope of the claims of the present invention caused serious defects.
【００５０】[0050]
【実施例２】 １．シリコーン系複合体（２）の調製 硬度ＪＩＳＡ５度のミラブル型シリコーンゴム（ワッカ
ーケミカル製）１００重量部と窒化珪素粉末ＳＮ−Ｆ１
（電気化学工業（株）製）１００重量部とを振動式ボー
ルミルにて１時間混合粉砕した。粉砕物を、ダブルコー
ンミキサーに投入し、これにＮ-β-（アミノエチル）γ
-アミノプロピルトリメトシキシラン（日本ユニカー
（株）製 品番Ａ−１１００）を１重量％添加し１５分
間混合した。このものを、更に１２０℃で１時間熱処理
し、冷却後篩別しシリコーン系複合体２を得た。 ２．半導体封止用樹脂組成物（Ａ１）の調製と半導体装
置の性能評価 このシリコーン系複合体２を用いて、実施例１と同様に
してエポキシ・シリコーンエラストマー樹脂組成物Ａ１
を調製し、実施例１と同様にして半導体封止特性を評価
した。結果は表２に示す。この結果から、性能の優れた
半導体装置が得られることが分かる。Embodiment 2 1. Preparation of Silicone Composite (2) 100 parts by weight of a millable type silicone rubber (manufactured by Wacker Chemical) having a hardness of JIS A5 and silicon nitride powder SN-F1
100 parts by weight (manufactured by Denki Kagaku Kogyo Co., Ltd.) was mixed and pulverized for 1 hour in a vibrating ball mill. The crushed product is put into a double cone mixer, and N-β- (aminoethyl) γ
-Aminopropyltrimethoxysilane (product number A-1100 manufactured by Nippon Unicar Co., Ltd.) was added at 1% by weight and mixed for 15 minutes. This was further heat-treated at 120 ° C. for 1 hour, cooled and sieved to obtain a silicone-based composite 2. 2. Preparation of resin composition for semiconductor encapsulation (A1) and performance evaluation of semiconductor device Epoxy-silicone elastomer resin composition A1 using this silicone composite 2 in the same manner as in Example 1.
Was prepared and the semiconductor sealing characteristics were evaluated in the same manner as in Example 1. The results are shown in Table 2. From this result, it can be seen that a semiconductor device with excellent performance can be obtained.
【００５１】[0051]
【実施例３】 １．柔軟性シリコーン（１）の製法 信越化学工業（株）製品番 ＫＭＰ５９４のシリコーン
ゴムを、細川ミクロン（株）製「メカノフュージョンシ
ステム」に入れ表面を破壊し、シラノール基を生成せし
める。次に、該シリコーンゴムをヘンシェルミキサーに
入れ、１００ｒｐｍで撹拌しながらγ-グリシドキシプ
ロピルメチルジエトキシシラン（信越化学工業（株）製
品ＫＢＥ−４０２）０．５重量％を１分間で噴霧添加す
る。噴霧後、乾燥機に於いて１２０℃で２時間加熱し
た。その後篩い分けし、柔軟性シリコーン１を得た。得
られた柔軟性シリコーン１の平均粒径は、５μｍで粒径
１００μｍ以下の比率は９９％以上であり、エポシキ基
を５０００ｇ／当量含有し、硬度は針入度が１５ｍｍ、
ＪＩＳＡが２以下であった。尚、平均粒径及び粒径分布
は、電子顕微鏡及び島津製作所製「島津レーザ式粒度分
布測定装置 ＳＡＬＤ−３２０００」を使用して測定し
た。粒径分布つまり粒径１００μｍ以下の比率は、得ら
れた粒度度数分布図に於いて、１００μｍ以下の占める
面積の割合で表した。又、平均粒径は、得られた粒度累
積分布図に於いて、５０％が占める粒径を以て表した。Embodiment 3 1. Manufacturing method of flexible silicone (1) Shin-Etsu Chemical Co., Ltd. product number KMP594 silicone rubber is put in "Mechanofusion System" manufactured by Hosokawa Micron Co., Ltd. to destroy the surface and generate silanol groups. Next, the silicone rubber was placed in a Henschel mixer, and 0.5% by weight of γ-glycidoxypropylmethyldiethoxysilane (KBE-402 manufactured by Shin-Etsu Chemical Co., Ltd.) was added by spraying for 1 minute while stirring at 100 rpm. To do. After spraying, it was heated in a dryer at 120 ° C. for 2 hours. After that, sieving was performed to obtain flexible silicone 1. The obtained flexible silicone 1 has an average particle size of 5 μm and a ratio of particle size of 100 μm or less is 99% or more, contains an epoxy group of 5000 g / equivalent, and has a hardness of 15 mm and a penetration of 15 mm.
JISA was 2 or less. The average particle size and the particle size distribution were measured using an electron microscope and “Shimadzu laser particle size distribution analyzer SALD-32000” manufactured by Shimadzu Corporation. The particle size distribution, that is, the ratio of the particle size of 100 μm or less was expressed by the ratio of the area occupied by 100 μm or less in the obtained particle size distribution chart. In addition, the average particle size is represented by the particle size which 50% occupies in the obtained particle size cumulative distribution chart.
【００５２】２．半導体封止用樹脂組成物（Ａ２）の調
製 先に調製した柔軟性シリコーン１に、エポキシ樹脂、硬
化剤、硬化促進剤、充填剤、難燃剤、処理剤、顔料を混
合し、６０℃の温度で１５分間加熱真空乳化器を使用し
て混練し基板側封止用樹脂組成物Ａ２を得た。この際
の、樹脂組成を表３に示した。2. Preparation of resin composition for semiconductor encapsulation (A2) Epoxy resin, a curing agent, a curing accelerator, a filler, a flame retardant, a treatment agent, and a pigment are mixed with the flexible silicone 1 prepared above, and the temperature is 60 ° C. And was kneaded for 15 minutes using a heating vacuum emulsifier to obtain a substrate-side sealing resin composition A2. The resin composition at this time is shown in Table 3.
【００５３】[0053]
【表３】 [Table 3]
【００５４】３．半導体封止効果の評価 次に、該樹脂組成物Ａ２を基板側樹脂層に使用し、素子
側樹脂層にエポキシ樹脂組成物Ｂを使用して、模擬半導
体素子を封止しその信頼性（密着性、耐衝撃性、腐食
性)を評価した。評価結果は、表２に示した様に、極め
て優れた樹脂封止型半導体装置が得られたことが分か
る。3. Evaluation of Semiconductor Encapsulation Effect Next, the resin composition A2 was used for the substrate-side resin layer, and the epoxy resin composition B was used for the element-side resin layer to seal the simulated semiconductor element and to evaluate its reliability (adhesion). Property, impact resistance, and corrosiveness) were evaluated. As shown in Table 2, the evaluation results show that an extremely excellent resin-sealed semiconductor device was obtained.
【００５５】[0055]
【実施例４】酸化アルミニウムを１０％弗酸水溶液に１
分間浸漬しその後純水で５回洗浄する。酸洗浄により表
面が水酸化物となった酸化アルミニウム粉末を乳化器に
投入し、これに末端ＯＨ基のジメチルシリコーンオイル
（信越化学工業（株）製品品番ＲＦ−７００）、硬度Ｊ
ＩＳＡ５度のミラブル型シリコーンゴム（ワッカーケミ
カル製）、ジメチルジメトキシシラン（信越化学工業
（株）製品 品番ＫＢＭ−２２）、及びメチルトリメト
キシシラン（信越化学工業（株）製品 品番ＫＢＭ−１
３）を重量比１０：５：５：１の割合に混合添加したも
のを７０重量％加え、８０℃で１５分間混練した。更
に、これとγ-グリシドキシプロピルトリメトキシシラ
ン１重量％とをダブルコーンミキサーに投入し、１５分
間混合した。このものを、更に流動乾燥機に於いて１２
０℃で１時間熱処理し、その後篩別した。この結果、酸
化アルミニウム粉末を内層とし、その表層にエポキシ基
を有するシリコーン系複合体３が得られた。これを基板
側樹脂組成物として、エポキシ樹脂組成物Ｂを素子側樹
脂組成物に使用して、同様に半導体装置特性を評価し
た。樹脂成型性も半導体装置特性ともいづれも性能の優
れたものであった。Example 4 1% aluminum oxide in 10% hydrofluoric acid solution
Immerse for a minute and then wash 5 times with pure water. Aluminum oxide powder whose surface has been converted to hydroxide by acid washing is put into an emulsifier, and dimethyl silicone oil having a terminal OH group (Shin-Etsu Chemical Co., Ltd. product number RF-700), hardness J
ISA 5 degree millable type silicone rubber (manufactured by Wacker Chemical), dimethyldimethoxysilane (Shin-Etsu Chemical Co., Ltd. product No. KBM-22), and methyltrimethoxysilane (Shin-Etsu Chemical Co., Ltd. product No. KBM-1)
70% by weight of 3) was mixed and added in a weight ratio of 10: 5: 5: 1, and the mixture was kneaded at 80 ° C. for 15 minutes. Further, this and 1% by weight of γ-glycidoxypropyltrimethoxysilane were put into a double cone mixer and mixed for 15 minutes. This product was further processed in a fluid dryer for 12
It was heat-treated at 0 ° C. for 1 hour and then sieved. As a result, a silicone composite 3 having an aluminum oxide powder as an inner layer and an epoxy group on the surface layer was obtained. Using this as the substrate-side resin composition, the epoxy resin composition B was used as the element-side resin composition, and the semiconductor device characteristics were similarly evaluated. Both resin moldability and semiconductor device characteristics were excellent in performance.
【００５６】[0056]
【実施例５】窒化アルミニウム粉末をターボミルで粉砕
した。粉砕した窒化アルミニウム粉末を乳化器に投入
し、これに末端ＯＨ基のジメチルシリコーンオイル（信
越化学工業（株）製品 品番ＲＦ−７００）及びジメチ
ルジメトキシシラン（信越化学工業（株）製品 品番Ｋ
ＢＭ−２２）を重量比１：１の割合に混合したものを６
５重量％添加し、８０℃で１５分間混練した。更に、流
動乾燥機に於いて１２０℃で１時間処理し、その後篩別
した。この結果、窒化アルミニウム粉末を内部に有し、
その表層にメトキシ基を有するシリコーン系複合体４が
得られた。同様に半導体装置特性を評価し、樹脂成型性
も半導体装置特性ともいづれも性能の優れたものであっ
た。Example 5 Aluminum nitride powder was pulverized with a turbo mill. The crushed aluminum nitride powder is put into an emulsifier, and dimethyl silicone oil having a terminal OH group (Shin-Etsu Chemical Co., Ltd. product No. RF-700) and dimethyldimethoxysilane (Shin-Etsu Chemical Co., Ltd. product No. K).
BM-22) was mixed at a weight ratio of 1: 1 to give 6
5% by weight was added, and the mixture was kneaded at 80 ° C for 15 minutes. Further, it was treated in a fluidized dryer at 120 ° C. for 1 hour and then sieved. As a result, having aluminum nitride powder inside,
A silicone-based composite 4 having a methoxy group on its surface was obtained. Similarly, the semiconductor device characteristics were evaluated, and the resin moldability and the semiconductor device characteristics were both excellent in performance.
【００５７】[0057]
【発明の効果】エポキシ・シリコーンエラストマ一樹脂
組成物は、応力緩和特性に優れ、エポキシ樹脂と回路基
板との接着性に優れるので、エポキシ・シリコーンエラ
ストマ一樹脂組成物を応力緩衝層として用いることによ
り、半田付け等の熱衝撃に耐えることが可能となる。
又、外周部は耐湿性及び強度特性で実績のあるエポキシ
樹脂組成物により封止されているので、外的圧力や水分
侵入より半導体素子を保護する。これによりコスト面で
も有利となり、本発明の実用性が大きい。本発明のエポ
キシ・シリコーンエラストマ一樹脂組成物は、エポキシ
樹脂組成物及び回路基板と接着し界面を一体化させるこ
とにより、水の侵入を防止し、更に、外部応力を受けた
場合には自身が変形することにより応力を緩和するだけ
でなく、直ちに元の形状に戻り界面破壊を防ぐ。つまり
本発明により接着シール性と応力緩和性に優れた信頼性
の高い半導体装置が得られる。The epoxy / silicone elastomer resin composition has excellent stress relaxation characteristics and excellent adhesion between the epoxy resin and the circuit board. Therefore, by using the epoxy / silicone elastomer resin composition as a stress buffer layer, It is possible to withstand thermal shock such as soldering.
Further, since the outer peripheral portion is sealed with an epoxy resin composition that has a proven track record in moisture resistance and strength characteristics, the semiconductor element is protected from external pressure and moisture intrusion. This is advantageous in terms of cost, and the present invention is highly practical. The epoxy / silicone elastomer-based resin composition of the present invention prevents water from entering by adhering the epoxy resin composition and the circuit board to form an integrated interface, and when the external stress is applied, By deforming, not only the stress is relieved, but it immediately returns to its original shape and prevents interface destruction. That is, according to the present invention, a highly reliable semiconductor device having an excellent adhesive sealing property and stress relaxation property can be obtained.
【図１】ワイヤーボンデイング方式の一実施形態を示す
図であるFIG. 1 is a diagram showing an embodiment of a wire bonding system.
【図２】ワイヤーボンデイング方式の一般的な形態を示
す図であるFIG. 2 is a diagram showing a general form of a wire bonding method.
【図３】ＴＡＢ方式の一実施形態を示す図であるFIG. 3 is a diagram showing an embodiment of a TAB system.
【図４】フリップチップ方式の一実施形態を示す図であ
るFIG. 4 is a diagram showing an embodiment of a flip chip method.
１ 半導体素子 ２ 回路基板 ３ ワイヤー ４ 封止用樹脂層 ５ 基板電極 ６ マウント材 ７ 基板側樹脂層 ８ 素子側樹脂層 ９ リード線 １０ バンプ １１ フレキシブル回路基板 1 Semiconductor Element 2 Circuit Board 3 Wire 4 Sealing Resin Layer 5 Board Electrode 6 Mounting Material 7 Board Side Resin Layer 8 Element Side Resin Layer 9 Lead Wire 10 Bump 11 Flexible Circuit Board
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 // Ｃ０８Ｌ 63/00 ＮＫＢ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location // C08L 63/00 NKB
Claims (6)
式の樹脂封止型半導体装置にして、半導体装置のマウン
ト材又はバンプが設けられる回路基板側をエポキシ・シ
リコーンエラストマー樹脂組成物で封止し、更に該封止
部分をエポキシ樹脂組成物で封止したことを特徴とする
２層樹脂封止型半導体装置1. A resin-sealed semiconductor device in which a semiconductor element is directly mounted on a circuit board, and a mounting material of the semiconductor device or a circuit board side provided with bumps is sealed with an epoxy-silicone elastomer resin composition. And a two-layer resin-encapsulated semiconductor device characterized by further encapsulating the encapsulation portion with an epoxy resin composition.
成物が、９５〜５重量％のエポキシ樹脂、及び平均粒径
が０．１μｍ〜５０μｍで粒径分布に於いて粒径１００
μｍ以下が９５％以上であり、その表面に反応性官能基
を有し、その表層は硬度が針入度１５０ｍｍ以下かつＪ
ＩＳＡ４０度以下である柔軟性シリコーン及びその内部
は低熱膨張絶縁性物質からなる複合体にして、内部の比
率が１０〜９０重量％であるシリコーン系複合体５〜９
５重量％とから構成される組成物からなることを特徴と
する請求項１記載の樹脂封止型半導体装置2. An epoxy / silicone elastomer resin composition comprising 95 to 5% by weight of an epoxy resin and an average particle size of 0.1 μm to 50 μm and a particle size of 100 in the particle size distribution.
μm or less is 95% or more, has a reactive functional group on its surface, and the surface layer has hardness of 150 mm or less and J
Flexible silicone having an ISA of 40 degrees or less and a silicone-based composite having an internal ratio of 10 to 90% by weight, which is a composite made of a low thermal expansion insulating material.
The resin-encapsulated semiconductor device according to claim 1, wherein the resin-encapsulated semiconductor device is composed of 5% by weight.
成物が、９５〜５重量％のエポキシ樹脂、及び表面に反
応性官能基を有し、平均粒径が０．０１μｍから５０μ
ｍで粒径分布に於いて粒径１００μｍ以下が９５％以上
であって、その硬度が針入度１５０ｍｍ以下かつＪＩＳ
Ａ４０度以下の柔軟性シリコーン５〜９５重量％から構
成される組成物からなることを特徴とする請求項１記載
の樹脂封止型半導体装置3. An epoxy / silicone elastomer resin composition having an epoxy resin content of 95 to 5% by weight and a reactive functional group on the surface, and having an average particle diameter of 0.01 μm to 50 μm.
In the particle size distribution of m, the particle size of 100 μm or less is 95% or more, and the hardness is 150 mm or less and JIS
2. The resin-encapsulated semiconductor device according to claim 1, wherein the resin-encapsulated semiconductor device comprises a composition composed of 5 to 95% by weight of flexible silicone having an A of 40 degrees or less.
成物で封止した層の厚みが、３ないし５００μｍでかつ
マウント材又はバンプ材より厚く、半導体素子より薄い
ことを特徴とする請求項１ないし請求項３のいずれか１
項に記載の樹脂封止型半導体装置4. The thickness of the layer sealed with the epoxy-silicone elastomer resin composition is 3 to 500 μm, which is thicker than the mount material or the bump material and thinner than the semiconductor element. One of
Item 6. The resin-encapsulated semiconductor device according to item
リップチップ方式であることを特徴とする請求項１ない
し請求項４のいずれか１項に記載の樹脂封止型半導体装
置5. The resin-encapsulated semiconductor device according to claim 1, wherein the semiconductor element mounting method is a TAB method or a flip chip method.
とを特徴とする請求項１ないし請求項５のいずれか１項
に記載の樹脂封止型半導体装置6. The resin-encapsulated semiconductor device according to claim 1, wherein the circuit board is a flexible material such as a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8157620A JPH09321182A (en) | 1996-05-29 | 1996-05-29 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8157620A JPH09321182A (en) | 1996-05-29 | 1996-05-29 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09321182A true JPH09321182A (en) | 1997-12-12 |
Family
ID=15653717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8157620A Withdrawn JPH09321182A (en) | 1996-05-29 | 1996-05-29 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09321182A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008210959A (en) * | 2007-02-26 | 2008-09-11 | Kyocera Corp | Electronic component mounting structure |
| JP2010141077A (en) * | 2008-12-11 | 2010-06-24 | Sanken Electric Co Ltd | Electronic circuit device |
| WO2014103133A1 (en) | 2012-12-28 | 2014-07-03 | 富士電機株式会社 | Semiconductor device |
| US10438864B2 (en) | 2015-08-21 | 2019-10-08 | Hewlett-Packard Development Company, L.P. | Circuit packages comprising epoxy mold compounds and methods of compression molding |
| JP2020513157A (en) * | 2017-04-07 | 2020-04-30 | ▲寧▼波舜宇光▲電▼信息有限公司 | Semiconductor packaging method and semiconductor device based on molding process |
| US11081518B2 (en) | 2017-04-07 | 2021-08-03 | Ningbo Sunny Opotech Co., Ltd. | Semiconductor packaging method and semiconductor device based on molding process |
-
1996
- 1996-05-29 JP JP8157620A patent/JPH09321182A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008210959A (en) * | 2007-02-26 | 2008-09-11 | Kyocera Corp | Electronic component mounting structure |
| JP2010141077A (en) * | 2008-12-11 | 2010-06-24 | Sanken Electric Co Ltd | Electronic circuit device |
| US8237532B2 (en) | 2008-12-11 | 2012-08-07 | Sanken Electric Co., Ltd. | Electronic circuit device |
| WO2014103133A1 (en) | 2012-12-28 | 2014-07-03 | 富士電機株式会社 | Semiconductor device |
| US9852968B2 (en) | 2012-12-28 | 2017-12-26 | Fuji Electric Co., Ltd. | Semiconductor device including a sealing region |
| US10438864B2 (en) | 2015-08-21 | 2019-10-08 | Hewlett-Packard Development Company, L.P. | Circuit packages comprising epoxy mold compounds and methods of compression molding |
| JP2020513157A (en) * | 2017-04-07 | 2020-04-30 | ▲寧▼波舜宇光▲電▼信息有限公司 | Semiconductor packaging method and semiconductor device based on molding process |
| US11081518B2 (en) | 2017-04-07 | 2021-08-03 | Ningbo Sunny Opotech Co., Ltd. | Semiconductor packaging method and semiconductor device based on molding process |
| US11728368B2 (en) | 2017-04-07 | 2023-08-15 | Ningbo Sunny Opotech Co., Ltd. | Semiconductor packaging method and semiconductor device based on molding process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030805 |