JPH09312394A - Mos semiconductor device and method of fabricating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS semiconductor device in which the influence of damages and contamination or the surface caused by exposure to a plasma atmosphere are eliminated at the time of formation of a gate electrode or etchback of a side wall insulating film. SOLUTION: On the surface of a p-type silicon substrate 1, an element separation insulating film 2, a gate oxide film 3, a gate electrode 4 are formed (a). A thermal oxidation is performed by using the gate electrode 4 as a mask, thereby forming an oxide film 11 having the thickness of 20 to 100nm. Phosphorus is ion implanted, thereby forming an n<-> type diffusion layer 5 (b). Oxide film side walls 6 are formed and arsenic is ion-implanted, thereby forming an n<+> type diffusion layer 7 (c). A layer insulating film 9 and Al wiring 10 are formed (d). Consequently, damages and contamination on the surface of the substrate when the gate electrode is formed are taken in the relatively thick oxide film and are removed from the surface of the substrate. Since the surface of the substrate is not exposed by the oxide film 11 at the time of etchback for forming the oxide film side walls, the surface of the substrate is prevented from being damaged or contaminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method for manufacturing the same, and more particularly to a MOS type semiconductor device with improved leakage current characteristics and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 6A to 6C are cross-sectional views in order of steps showing a conventional method of manufacturing a general MOS type semiconductor device. After an element isolation oxide film (not shown) is formed on the surface of the p-type silicon substrate 1 by a LOCOS method or the like to define an element active region,
A gate oxide film 3 is formed on the silicon substrate in the element active region, and a conductive film such as a polysilicon film is formed thereon. Subsequently, the photolithography method and the dry etching method are applied to form the gate electrode 4 [FIG. 6A].

Next, thermal oxidation is performed to form a thin silicon oxide film 8a on the surface of the silicon substrate and the surface of the gate electrode. This silicon oxide film 8a is an oxide film formed for the purpose of preventing channeling at the time of ion implantation and out-diffusion at the time of subsequent activation heat treatment, and has a film thickness of about 10 nm or less. It Then, an n-type impurity, for example, phosphorus is ion-implanted at a low concentration to form the n ⁻ -type diffusion layer 5 [FIG.
(B)]. Then, a silicon oxide film is deposited and etched back by an anisotropic dry etching method to form an oxide film sidewall 6 [FIG. 6 (c)]. Thereafter, the silicon oxide film 8b for preventing the channeling of the ion-implanted species and the out-diffusion thereof is again formed by thermal oxidation.
Is thinly formed (about 10 nm or less), and n-type impurities such as arsenic are ion-implanted at a high concentration to form an n ⁺ -type diffusion layer 7 (FIG. 6D).

In the conventional example described above, a polysilicon gate is used. In this conventional example, the word line width is narrowed due to the miniaturization of the semiconductor integrated circuit, and the word line length is increased due to the large scale of the semiconductor integrated circuit. Is extended,
The resistance of the word line increases, and the operation delay becomes a problem. Therefore, the gate electrode is formed on the polysilicon film 4 as shown in FIG.
A gate electrode composed of a two-layer film of a and a silicide film, for example, a W (tungsten) silicide film 4b, that is, a gate electrode having a so-called polycide structure has been adopted. FIG. 7 is a cross-sectional view showing a state after forming the oxide film side wall 6 of the transistor having the polycide structure.

[0005]

In the conventional example shown in FIG. 6, the polysilicon film is etched by the dry method to form the gate electrode 4, or the CVD silicon oxide film is etched back to form the oxide film. When the side wall 6 is formed, the surface of the silicon substrate is exposed, so that the surface of the substrate is exposed to the plasma atmosphere and is damaged or contaminated by ion bombardment. Further, when the gate electrode shown in FIG. 7 is formed in the polycide structure, W in the W silicide film 4b is knocked out by the ions in the etch back process for forming the oxide film side wall 6, As shown in 7, it adheres to the substrate surface.

The above-mentioned damage and contamination of the substrate surface is
There is no particular problem in the operation of basic elements such as transistors.
No problem with conventional semiconductor devices
However, when higher performance is required for semiconductor devices, for example,
Dynamic Random Access Memory (DRAM)
And static random access memory (SRA
M) semiconductor devices such as
× 10^-14 mA / μm ^Two Low leakage current
If you try to reduce it, these damage and pollution
It becomes an obstacle.

Regarding the reduction of the leakage current, Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. 306636 proposes to remove the side wall of the oxide film immediately after the ion implantation of the high impurity concentration diffusion layer of the LDD structure is completed. FIG. 8 is a cross-sectional view for explaining this method. In the method proposed in this publication, as shown in FIG. 6D, after forming an n ⁺ -type diffusion layer 7 by ion implantation, Before performing the activation heat treatment, the oxide film side wall 6 is removed by etching, and a thin silicon oxide film 8 covering the gate electrode 4 is formed by high temperature thermal oxidation. According to the publication, this treatment prevents the occurrence of dislocation due to the presence of the oxide film side wall, and prevents contaminants from being taken into this dislocation. However, even if this method has the effect of preventing the occurrence of defects due to the side wall of the oxide film, it has almost no effect of removing the above-mentioned damage and contamination, and further increases the leakage current for the purpose of improving the performance of the semiconductor device. It cannot be expected to be effective as a measure for reduction.

Therefore, the problems to be solved by the present invention are as follows.
The effect of damage and contamination on the silicon substrate due to dry etching is eliminated, and the substrate surface is not damaged or contaminated during the etch back process when forming the sidewall insulating film, so that leakage current is prevented. To achieve higher performance of semiconductor devices.

[0009]

The above-mentioned problems are solved after the gate electrode is formed on the element active region defined by the element isolation oxide film (when the sidewall insulating film is formed, the sidewall insulating film is formed before the formation of the sidewall insulating film). Then, the problem can be solved by thermally oxidizing the surface of the silicon substrate in the element active region not covered by the gate electrode to form a silicon oxide film with a film thickness of 20 to 100 nm.

FIG. 5 is a graph showing the experimental results of the relationship between the film thickness of the silicon oxide film formed in the element active region after the gate electrode is formed and the reverse leakage current of the source / drain region diffusion layer. As shown in FIG. 5, the leak current decreases as the thickness of the silicon oxide film increases.
When the thickness exceeds 20 nm, the decreasing tendency becomes gradual. Therefore, in the present invention, the lower limit of the thermal oxide film to be formed is set to 20 nm. Also, 20
If the film thickness is not less than nm, it is possible to prevent the surface of the silicon substrate from being exposed by accurately determining the end point of the etchback in the etchback process when forming the oxide film side wall. On the other hand, regarding the upper limit of the thermal oxide film to be formed, even if the film thickness is 100 nm or more, the effect of improving the leakage current is not great, and the thermal oxidation time increases, the ion implantation energy increases, and the accuracy of the diffusion layer decreases. This value was selected because of the unfavorable effects such as.

Although the surface of the silicon substrate is damaged and further contaminated by being exposed to the plasma atmosphere by the dry etching for forming the gate electrode, according to the present invention, a relatively thick oxide film of 20 nm or more is formed. As a result, the damaged surface and contaminants are taken into the oxide film and removed from the substrate surface. Also,
In the etch back process when forming the oxide film side wall after that, since the silicon substrate surface can be prevented from being exposed by the thermal oxide film formed relatively thick, the substrate surface is protected from damage or contamination. You can Also in the conventional example shown in FIG. 6, the thermal oxide film is formed after the gate electrode is formed, but this thermal oxide film is performed for the purpose of channeling implanted ions and preventing the subsequent out diffusion. 10n
Generally, it is formed to have a film thickness of m or less. Further, even in the method disclosed in Japanese Patent Laid-Open No. 2-306636 shown in FIG. 8, a thin thermal oxide film is merely formed. As is clear from the graph shown in FIG. 5, the leak current cannot be sufficiently reduced with an oxide film of 10 nm or less.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In a MOS semiconductor device according to the present invention, an element active region electrically insulated by an element isolation insulating film is formed on one main surface of a silicon substrate, and a gate insulating layer is formed in the element active region. A gate electrode is formed through a film, and an impurity diffusion layer is formed in a surface region of the silicon substrate on both sides of the gate electrode, and is not covered with the gate electrode in the element active region. A feature is that a thermal oxide film of 20 to 100 nm is formed on the silicon substrate in contact with the silicon substrate.

The method of manufacturing a MOS type semiconductor device according to the present invention includes (1) a step of forming an element isolation insulating film for partitioning an element active region on one main surface of a silicon substrate,
(2) a step of forming a gate electrode on the silicon substrate in the element active region via a gate insulating film, and (3) introducing impurities into a surface region of the element active region on both sides of the gate electrode. A step of forming an impurity diffusion layer forming a source / drain region, and after the step (2), silicon oxide of 20 to 100 nm is formed on the element active region not covered by the gate electrode. It is characterized in that a thermal oxidation step for forming a film is added.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 1A to 1D are cross-sectional views sequentially showing main steps for explaining a first embodiment of a method for manufacturing a MOS type semiconductor device according to the present invention. It is a thing. First, as shown in FIG. 1A, an element isolation oxide film 2 having a thickness of 400 nm is formed on one main surface of a p-type silicon substrate 1 by selective thermal oxidation in a steam atmosphere at 1000 ° C. Then, the gate oxide film 3 having a thickness of 10 nm is formed by oxidation in a water vapor atmosphere at 800 ° C. After that, phosphorus-doped polysilicon having a film thickness of 500 nm is deposited by LPCVD (Low Pressure CVD), followed by photolithography and reactive ion etching (Re
The gate electrode 4 is formed by applying the active ion etching (RIE) method. Next, as shown in FIG. 1B, the entire surface is oxidized in a steam atmosphere at 900 ° C. to form a silicon oxide film 11 having a film thickness of 30 nm. By this oxidation, the surface of the gate electrode 4 is also covered with the silicon oxide film.

Next, as shown in FIG. 1C, arsenic is applied to the entire surface, acceleration energy: 80 keV, dose: 5 × 1.
Ions are implanted under the condition of 0 ¹⁵ cm ^-2 to form the n ⁺ -type diffusion layer 7, and then the implanted impurities are activated and crystal defects are recovered by heat treatment at 900 ° C. for 1 hour in an N ₂ atmosphere. I do. Next, as shown in FIG. 1D, a BPSG film is deposited by a CVD method to form an interlayer insulating film 9, a contact hole is opened at a predetermined place, and an aluminum wiring 10 is formed. The manufacturing process of the n-channel MOS transistor according to the example is completed.

[Second Embodiment] FIGS. 2A to 2D show
6A to 6C are sectional views sequentially showing main steps for explaining a second embodiment of the method for manufacturing a MOS semiconductor device according to the present invention. This embodiment is an LDD (Lightly Doped Dr
The present invention relates to an example in which the present invention is applied to the manufacture of a transistor having an ain structure. First, as shown in FIG. 2A, an element isolation oxide film 2 having a thickness of 400 nm is formed on one main surface of the p-type silicon substrate 1 by selective thermal oxidation in a steam atmosphere at 1000 ° C.
Then, the gate oxide film 3 having a thickness of 10 nm is formed,
It is formed by oxidation in a steam atmosphere at 800 ° C., and then the gate electrode 4 is formed. Subsequently, as shown in FIG. 2B, the entire surface is oxidized in a steam atmosphere at 900 ° C. to form a silicon oxide film 11 having a thickness of 30 nm. Then, phosphorus is ion-implanted into the entire surface under the conditions of an acceleration energy of 50 keV and a dose amount of 5 × 10 ¹⁴ cm ⁻² , and n ^−.
A mold diffusion layer 5 is formed.

Next, as shown in FIG. 2C, CVD
Then, a silicon oxide film having a film thickness of 200 nm is deposited by an etching method and then etched back by anisotropic etching to form an oxide film side wall 6 on the side surface of the gate electrode 4. In etching back when forming the oxide film side wall 6, the silicon oxide film 1 is used.
Etching is terminated in the middle of 1 so that the surface of the silicon substrate is not exposed. After that, arsenic is applied to the entire surface, acceleration energy: 80 keV, dose: 5 × 1
Ions are implanted under the condition of 0 ¹⁵ cm ^-2 to form the n ⁺ -type diffusion layer 7, and then the implanted impurities are activated and the crystal defects are recovered by heat treatment at 900 ° C. for 1 hour in an N ₂ atmosphere. To do. Next, as shown in FIG. 2D, an interlayer insulating film 9 is formed, a contact hole is formed at a predetermined position, and then an aluminum wiring 10 is formed to manufacture the n-channel MOS transistor of this embodiment. Is completed.

[Third Embodiment] FIGS. 3A to 3D show
6A to 6C are sectional views sequentially showing main steps for explaining a third embodiment of a method for manufacturing a MOS type semiconductor device according to the present invention. First, as shown in FIG. 3A, an element isolation oxide film 2 having a thickness of 400 nm is formed on one main surface of a p-type silicon substrate 1 by selective thermal oxidation in a steam atmosphere at 1000 ° C. Next, a gate oxide film 3 having a thickness of 10 nm is formed by oxidation in a steam atmosphere at 800 ° C.
Then, a 400 nm-thick polysilicon doped with phosphorus at a concentration of 1 × 10 ¹⁹ cm ⁻³ is deposited on the entire surface by LPCVD, and then a 100 nm-thick silicon nitride film 15 is formed on the entire surface by CVD. Then, the silicon nitride film 15 and the polysilicon film are sequentially etched by using the photolithography method and the RIE method which are usually used to form the gate electrode 4 with the silicon nitride film.

Subsequently, a 100 nm-thickness silicon nitride film is newly deposited on the entire surface and then etched back by anisotropic etching to form a nitride film sidewall 12 on the side surface of the gate electrode 4. After that, the silicon nitride film 1 on the gate electrode 4
Using 5 and the nitride film side wall 12 as a mask, thermal oxidation is performed in a water vapor atmosphere at 900 ° C. to form a 30 nm silicon oxide film 11.

Next, as shown in FIG. 3B, 130 ° C.
Then, the silicon nitride film 15 and the nitride film side wall 12 on the gate oxide film are removed by immersing the silicon oxide film in the phosphoric acid. After that, phosphorus is applied to the entire surface, acceleration energy: 50 keV, dose amount: 5 ×
The n ⁻ type diffusion layer 5 is formed by ion implantation under the condition of 10 ¹⁴ cm ^−2.
To form Then, as shown in FIG.
After depositing a silicon oxide film having a film thickness of 200 nm by the VD method, etching back is performed by anisotropic etching to form an oxide film sidewall 6 on the side surface of the gate electrode 4. In the etch back when forming the oxide film side wall 6, the etching is finished in the middle of the silicon oxide film 11 so that the surface of the silicon substrate is not exposed.

Next, arsenic is applied to the entire surface, and the acceleration energy is 8
Ions are implanted under the conditions of 0 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type diffusion layer 7, and then heat treatment is performed in an N ₂ atmosphere at 900 ° C. for 1 hour to implant. Activate impurities and recover crystal defects. Next, FIG.
As shown in (d), an interlayer insulating film 9 is formed, a contact hole is opened at a predetermined position, and an aluminum wiring 10 is formed, and the manufacturing process of the n-channel MOS transistor according to the present embodiment is completed.

[Fourth Embodiment] FIGS. 4A to 4D show
FIG. 9 is a sectional view sequentially showing main steps for explaining a fourth embodiment of the method for manufacturing a MOS semiconductor device according to the present invention. First, as shown in FIG. 4A, an element isolation oxide film 2 having a thickness of 400 nm is formed on one main surface of the p-type silicon substrate 1 by selective thermal oxidation in a steam atmosphere at 1000 ° C. Next, a gate oxide film 3 having a thickness of 10 nm is formed by thermal oxidation in a water vapor atmosphere at 800 ° C., and then a poly-silicon film having a thickness of 400 nm in which phosphorus is doped at a concentration of 1 × 10 ¹⁹ cm ^−3. LPCVD of silicon
Formed by the CVD method, and then a thickness of 1 on the entire surface by the CVD method.
A silicon nitride film 15 having a thickness of 00 nm is formed, and a silicon nitride film and a polysilicon film are sequentially etched by a photolithography method and an RIE method which are commonly used to form a gate electrode 4 having a silicon nitride film 15 on the surface.

Then, a second silicon nitride film having a film thickness of 20 nm and a silicon oxide film having a thickness of 100 nm are sequentially deposited on the entire surface, and then etched back by anisotropic etching to form a silicon oxide film on the side surface of the gate electrode 4. An oxide film / nitride film sidewall 13 made of a laminated film of silicon oxide and silicon nitride film is formed, and then, as shown in FIG. 4B, a treatment with buffered hydrofluoric acid is performed to form the oxide film / nitride film sidewall 13. The silicon oxide film is removed by etching to form the nitride film side wall 14. Then, using the silicon nitride film 15 on the gate electrode and the nitride film side wall 14 as a mask, the entire surface is oxidized in a steam atmosphere at 900 ° C. to form a 30 nm silicon oxide film 11.

Then, as shown in FIG.
The silicon nitride film 15 and the nitride film side wall 14 on the gate oxide film are removed by immersing in phosphoric acid at ℃, and then phosphorus is applied to the entire surface with acceleration energy: 50 keV, dose amount: 5
Ions are implanted under the condition of × 10 ¹⁴ cm ⁻² to form the n ⁻ type diffusion layer 5. Next, a 200 nm-thickness silicon oxide film is deposited by the CVD method and then etched back by anisotropic etching to form an oxide film side wall 6 on the side surface of the gate electrode 4. In the etching back when forming the oxide film side wall 6, the etching is finished at least in the middle of the silicon oxide film 11 so that the surface of the silicon substrate is not exposed. Next, arsenic is ion-implanted on the entire surface under the conditions of an acceleration energy: 80 keV and a dose amount: 5 × 10 ¹⁵ cm ⁻² to form an n ⁺ type diffusion layer 7, and then N ₂
Heat treatment is performed at 900 ° C. for 1 hour in the atmosphere to activate the implanted impurities and recover the crystal defects. next,
As shown in FIG. 4D, an interlayer insulating film 9 is formed, contact holes are opened at predetermined locations, and aluminum wiring 1 is formed.
By forming 0, the manufacturing process of the n-channel MOS transistor of this embodiment is completed.

In the step of forming the silicon oxide film 11 formed in the above-described first to fourth embodiments of the present invention, after forming the gate electrode 4, the silicon for forming the oxide film side wall 6 on the side surface of the gate electrode 4 is formed. It suffices if it is before the oxide film etch back step, and within this range, the effects of the present invention can be enjoyed. That is, the ion implantation step for forming the diffusion layer is
This means that there is no particular problem even before or after the step of forming the silicon oxide film 11.

In the first and second embodiments, since no oxidation resistant film is provided on the gate electrode 4, oxidation progresses in the gate electrode 4 itself or in the downward direction of the gate electrode 4, thus hindering device characteristics. May come. The above-mentioned third and fourth embodiments deal with such inconvenience, and it is possible to suppress the film reduction of the gate electrode by performing thermal oxidation after covering the gate electrode with the silicon nitride film. It is possible to suppress the growth of the silicon oxide film below the gate electrode. Although the third and fourth embodiments relate to the method of manufacturing the transistor having the LDD structure, the source / drain having the single structure may be formed before or after the formation of the silicon oxide film 11. Also,
The present invention can also be applied to a transistor having a gate electrode having a silicide structure.

[0027]

As described above, according to the present invention, the gate electrode is covered after the gate electrode is formed (when the side wall insulating film is formed on the side surface of the gate electrode, before the side wall insulating film is formed). According to the present invention, a thermal oxide film of 20 nm to 100 nm is formed on the active region of the element which is not present. Therefore, according to the present invention, damages and contaminants introduced into the substrate near the surface during the steps up to that of forming the gate electrode. And the like can be incorporated into a relatively thick oxide film formed in the element active region, and these can be removed from the substrate surface.

Further, in the etch back process for forming the sidewall insulating film on the side surface of the gate electrode, the silicon active substrate is directly exposed to the etching atmosphere because the element active region is already covered with the relatively thick oxide film. Therefore, it is possible to prevent the silicon substrate from being damaged by etching species and the substrate surface from being contaminated. In addition,
For example, when the gate electrode has a polycide structure using W silicide or the like, even if W in the W silicide layer exposed at the upper part of the gate electrode may be knocked out by etching species, this should adhere to the surface of the silicon substrate. Can be prevented.

Therefore, according to the present invention, as shown in FIG. 5, the leakage current of the MOS device can be reduced to about 5 × 10 ⁻¹⁴ mA / μm ⁻² or less at the operating voltage thereof. When the device is used in a device such as a semiconductor device such as a DRAM or an SRAM, which is intended to improve leakage characteristics and achieve high performance, the requirement can be satisfied.

[Brief description of drawings]

FIG. 1 is a process order cross-sectional view showing in sequence the main steps of a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a process order cross-sectional view showing in sequence main steps of a manufacturing method according to a second embodiment of the present invention.

FIG. 3 is a process order cross-sectional view showing in sequence main steps of a manufacturing method according to a third embodiment of the present invention.

FIG. 4 is a process order cross-sectional view sequentially showing main steps of a manufacturing method according to a fourth example of the present invention.

FIG. 5 is a graph showing the relationship between the film thickness of the formed thermal oxide film and the leak current, for explaining the effect achieved by the present invention.

6A to 6C are cross-sectional views in order of the processes, for illustrating a conventional method for manufacturing a general MOS type semiconductor device.

FIG. 7: M having a conventional gate electrode having a polycide structure
7A and 7B are cross-sectional views each illustrating a problem of an OS transistor.

FIG. 8 is a sectional view of another conventional example.

[Explanation of symbols]

1 p-type silicon substrate 2 element isolation oxide film 3 gate oxide film 4 gate electrode 5 n ^- type diffusion layer 6 oxide film side wall 7 n ⁺ type diffusion layer 8, 8a, 8b, 11 silicon oxide film 9 interlayer insulating film 10 aluminum wiring 12, 14 Nitride film side wall 13 Oxide film / Nitride film side wall 15 Silicon nitride film

Claims (6)

[Claims] 1. An element active region electrically insulated by an element isolation insulating film is formed on one main surface of a silicon substrate, and a gate electrode is formed in the element active region via a gate insulating film. In a MOS semiconductor device in which an impurity diffusion layer is formed in a surface region of the silicon substrate on both sides of a gate electrode, a silicon substrate not covered with the gate electrode in the element active region is in contact with the silicon substrate. A MOS type semiconductor device having a thermal oxide film of 20 to 100 nm formed thereon. 2. A sidewall insulating film is formed on a side surface of the gate electrode, and the impurity diffusion layer is an LDD (Lightly Doped) layer.
The MOS type semiconductor device according to claim 1, wherein the MOS type semiconductor device is formed in a Drain structure. 3. A step of (1) forming an element isolation insulating film for partitioning an element active region on one main surface of a silicon substrate, and (2) a gate insulating film on the silicon substrate in the element active region via a gate insulating film. And forming a gate electrode by forming impurities into the surface region of the element active region on both sides of the gate electrode to form an impurity diffusion layer forming a source / drain region. In the method for manufacturing a MOS semiconductor device, a thermal oxidation step of forming a silicon oxide film having a film thickness of 20 to 100 nm on the element active region not covered by the gate electrode is added after the step (2). MO characterized by being
A method for manufacturing an S-type semiconductor device. 4. The thermal oxidation step performed after the second step is performed with the upper surface and the side surface of the gate electrode covered with a silicon nitride film mask, and the thermal oxidation step is performed after the thermal oxidation step. 4. The method of manufacturing a MOS semiconductor device according to claim 3, wherein the silicon nitride film mask is removed. 5. The silicon nitride film mask has a silicon nitride film formed on the upper surface of the gate electrode when the gate electrode is formed, and a silicon nitride film, or a silicon nitride film and a silicon oxide film are formed on the entire surface after the gate electrode is formed. 5. The MO according to claim 4, wherein the MO film is formed by depositing a film and performing etch back, or by performing etch back and etching of a silicon oxide film.
A method for manufacturing an S-type semiconductor device. 6. The sub-step of the third step, which comprises introducing a low concentration impurity using the gate electrode as a mask, the sub-step of forming a sidewall insulating film on a side surface of the gate electrode, the gate electrode and the Sub-step of introducing a high concentration of impurities using the sidewall insulating film as a mask,
6. The method of manufacturing a MOS semiconductor device according to claim 3, 4 or 5, wherein the thermal oxidation step is performed before the first step.