JPH09307008A - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a memory cell, without restriction by punch- through of a thin film transistor, etc., by forming element isolating insulation films between parallel diffused layers wirings on a semiconductor substrate and laminating the thin film transistors on the diffused layer wirings. SOLUTION: The nonvolatile semiconductor memory device 1 comprises parallel diffused layer wirings 13 with an element isolating insulation film 12 between on a semiconductor substrate 11 and thin film transistors 2 laminated on these wirings 13. With the reduction of the cell area of the thin film transistor 2, it is never restricted by the region of each wiring 13 to form bit lines and source lines, punch-through between the wirings 13, short channel effect of the transistor 2, etc. A first insulation film 14 is formed on one of the wirings 13 so as to be continuous to the insulation film 12 and channel regions 18 of the transistors 2 extend thereon to increase the channel length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the recent widespread development of portable information terminals, the need for a large-capacity flash memory as an external storage device is increasing. Conventionally, as a small memory cell for use in the above-mentioned mass storage device, as shown in FIG. 5 and IEDM, (1986) J. Esquivel, A. Mitchell, J. Paterso.
A memory cell structure as shown in n.B.Riemenschnieder, H.Tieglaar, p.592-595 has been proposed. In this specification, it is called "contactless type".

In the "contactless type" memory cell shown in FIG. 5, the diffusion layers 112 to 114 formed in parallel on the semiconductor substrate 111 are provided with bit lines and source lines, and the diffusion layers 112 to 114 are formed. Memory cell transistors 115 and 116 are provided so as to be sandwiched by 114. Then, the semiconductor substrate 1 between the diffusion layers 112 to 114 is formed.
11 by providing the impurity layers 117 and 118 to the diffusion layers 112 to
114 are separated. As a result, since the bit line (for example, the diffusion layer 112) also serves as the drain diffusion layer in the memory cell transistor (for example, the memory cell transistor 115), the contact area between the bit line and the drain diffusion layer is reduced, and the memory cell is reduced. The area has been reduced.

[0004]

However, in the memory cell described in the prior art, the diffusion layers are separated from each other only by the impurity layer formed by ion implantation. There was a problem of punch through. In particular, in the process of growing the thermal oxide film on the diffusion layer, the impurities in the diffusion layer diffuse in the channel direction and the depth direction of the substrate due to the accelerated diffusion of the impurities. for that reason,
The above problem is further exacerbated. At the same time, punch-through of memory cell transistors becomes a problem. Further, in the above-mentioned conventional technique, the cell size in the word line direction is uniquely determined by the diffusion layer width and the channel length. Therefore, there is a limit to the reduction of the cell area due to the restrictions of diffusion layer resistance, cell transistor punch-through, and short channel effect.

[0005]

SUMMARY OF THE INVENTION The present invention is a nonvolatile semiconductor memory device and a method of manufacturing the same, which have been made to solve the above problems.

That is, in the nonvolatile semiconductor memory device, the diffusion layer wiring is formed in parallel on the semiconductor substrate. Further, an element isolation insulating film is formed between the diffusion layer wirings, and a thin film transistor in which a source / drain region is connected on each diffusion layer wiring and a channel length direction is formed in a direction crossing each diffusion layer wiring is provided. There is something.

In the above nonvolatile semiconductor memory device, since the diffusion layer wirings arranged in parallel on the semiconductor substrate become the bit lines and the source lines, and the element isolation insulating film is formed between the diffusion layer wirings, Punch through does not occur between the diffusion layer wirings. Further, since a thin film transistor in which a source / drain region is connected on each diffusion layer wiring and a channel length direction is formed in a direction traversing each diffusion layer wiring is provided, the source / drain region width and the channel length are different from each other. The dimension of the cell size in the word line direction that is uniquely determined becomes the interval between the diffusion layer wirings, and the cell area is reduced. Further, since the thin film transistor is formed in a state of being stacked on each diffusion layer wiring to be a bit line or a source line, the resistance of each diffusion layer wiring, the punch through of the thin film transistor, as the cell area of the thin film transistor is reduced. There is no restriction such as short channel effect.

Further, in the above-mentioned nonvolatile semiconductor memory device, an insulating film formed continuously with the element isolation insulating film is provided on one side of each diffusion layer wiring, and the channel region of the thin film transistor is formed on the insulating film. It is formed by extension. As described above, the insulating film is provided so as to be continuous with the element isolation insulating film, and the channel region of the thin film transistor is extended and formed on the insulating film, so that the channel length becomes long. Therefore, in the thin film transistor, the occurrence of punch through is suppressed.

Further, in the above nonvolatile semiconductor memory device, a floating gate is provided between the channel region of the thin film transistor and the gate electrode with an insulating film interposed, and the floating gate is offset on the channel region and to one side. It is what is formed. Since the floating gate is provided as described above and the floating gate is formed on the channel region and offset to one side, depletion is prevented even when the cell transistor (thin film transistor) is overerased. .

In the method of manufacturing a non-volatile semiconductor memory device, in the first step, after forming an element isolation insulating film for isolating a diffusion layer region on a semiconductor substrate, the semiconductor substrate separated by this element isolation insulating film is formed. Diffusion layer wiring is formed in parallel. Next, in a second step, after forming a first insulating film on each diffusion layer wiring, the first insulating film on a part of each diffusion layer wiring is removed to form an opening, and then the entire upper surface of the semiconductor substrate is formed. A semiconductor layer is formed on. Then, in a third step, a second insulating film is formed on the surface of the semiconductor layer, and impurities are diffused from the diffusion layer wirings to the semiconductor layer above the opening to form source / drain regions. Further, in a fourth step, a gate pattern to be a floating gate is formed on the semiconductor layer between the source / drain regions. Next, in a fifth step, after forming a third insulating film on the surface of the gate pattern, a conductive layer is formed on the upper side of the semiconductor substrate. Then, in a sixth step, patterning is performed from the conductive layer to the semiconductor layer to form a word line in a direction crossing the diffusion layer wiring in the conductive layer, and a floating gate is formed below the word line in a gate pattern via a third insulating film. And a channel region is formed below the word line in the semiconductor layer between the source / drain regions via the third insulating film, the floating gate, and the second insulating film to solve the problem.

In the above manufacturing method, after forming the element isolation insulating film on the semiconductor substrate, the diffusion layer wirings are formed in parallel on the semiconductor substrate separated by the element isolation insulating film.
Each diffusion layer wiring is to be separated by the element isolation insulating film, and each diffusion layer wiring serves as a bit line and a source line. Therefore, punch through does not occur between the diffusion layer wirings. Further, since each diffusion layer wiring is formed after forming the element isolation insulating film, the diffusion layer wiring does not cause accelerated diffusion, and the element isolation insulating film should be formed by a method utilizing a thermal oxidation method. Will be possible. Further, a first insulating film is formed on each diffusion layer wiring, an opening is formed in the first insulating film, a semiconductor layer is further formed, and source / drain regions are formed in the semiconductor layer above the opening. Therefore, the diffusion layer wiring serving as the bit line or the source line and the semiconductor layer serving as the thin film transistor are formed in a stacked state. for that reason,
The width of the source / drain region is narrowed to increase the channel length without increasing the resistance of each diffusion layer wiring.

Further, in the above manufacturing method, the opening is formed by removing the first insulating film on the first and second diffusion layer wirings on the element isolation insulating film side. In such a manufacturing method, since the opening is formed on the element isolation insulating film side, the source / drain regions are also formed on the element isolation insulating film side. Therefore, the semiconductor layer over the first insulating film functions as a channel region, so that a thin film transistor with a long channel length is formed.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment according to the present invention will be described with reference to the schematic configuration diagram shown in FIG. In FIG. 1, as an example, the nonvolatile semiconductor memory device 1 is shown in a perspective sectional view.

An element isolation insulating film 12 is formed on the semiconductor substrate 11.
Are formed in parallel. The semiconductor substrate 11 is made of, for example, a silicon substrate, and the element isolation insulating film 12 is made of, for example, a silicon oxide film. Diffusion layer wiring 13 is formed on the semiconductor substrate 11 between the element isolation insulating films 12. The diffusion layer wiring 13 becomes a bit line and a source line. Each diffusion layer wiring 13 is formed by doping phosphorus or arsenic, for example.

A first insulating film 14 is formed on each of the diffusion layer wirings 13 so as to be continuous with the element isolation region 12. The first insulating film 14 is made of, for example, silicon oxide and has a thickness of, for example, 50 nm. An opening 15 is formed in a part of one side of each of the first insulating films 14.

Further, a semiconductor layer 16 is formed on the semiconductor substrate 11 so as to traverse each diffusion layer wiring 13 via each element isolation insulating film 12 and each first insulating film 14. The semiconductor layer 16 is made of polycrystalline silicon obtained by crystallizing amorphous silicon, and has a thickness of, for example, 100 n.
m. A source / drain region 17 is formed in each of the semiconductor layers 16 on each of the openings 15.
Are formed. Each source / drain region 17 is formed by diffusing impurities (for example, phosphorus, arsenic, etc.) from the diffusion layer wiring 13. The semiconductor layer 16 between the source / drain regions 17 is formed into the channel region 18
become. Therefore, the channel region 18 is formed not only on the element isolation insulating film 12 but also on a part of the first insulating film 14.

A second insulating film 19 is formed on the semiconductor layer 16. The second insulating film 19 serves as a gate insulating film and is made of, for example, silicon oxide having a thickness of 10 nm. Further above the channel region 18 and at the source
The floating gate 20 is formed on the second insulating film 19 on one side between the drain regions 17. The floating gate 20 is made of, for example, polycrystalline silicon. A third insulating film 21 is formed so as to cover the floating gate 20. This third
The insulating film 21 is formed of, for example, a laminated film of silicon oxide / silicon nitride / silicon oxide. Furthermore the third
The word line 22 is formed on the insulating film 21. The word line 22 is made of polycide, for example.

Therefore, with the word line 22 as a gate electrode, the word line 22, the third insulating film 21, the floating gate 20, the second insulating film (gate insulating film) 19, the channel region 18, and the source / drain region 17 are used. The thin film transistor 2 is configured.

In the nonvolatile semiconductor memory device 1, since the diffusion layer wiring 13 is formed in parallel on the semiconductor substrate 11 with the element isolation insulating film 12 interposed therebetween, the diffusion layer wiring 13 becomes a bit line or a source line. Punch-through does not occur between the diffusion layer wirings 13. Further, since the diffusion layer wirings 13 and the thin film transistors 2 are formed in a stacked state, the resistance and diffusion of the diffusion layer wirings 13 serving as bit lines and source lines are reduced as the cell area of the thin film transistor 2 is reduced. There is no restriction such as punch-through between the layer wirings 13 and the short channel effect of the thin film transistor 2.

Further, a first insulating film 14 is formed on one side of each diffusion layer wiring 13 so as to be continuous with the element isolation insulating film 12, and the channel region of the thin film transistor 2 is provided on the first insulating film 14. Since it is formed by extending 18, the channel length Lc becomes long. Therefore, in the thin film transistor 2, the occurrence of punch through is suppressed.

Further, a floating gate 20 is provided between the channel region 18 and the word line 22 serving as a gate electrode via a third insulating film 21, and the floating gate 20 is on the channel region 18 and on one side. Since they are formed on one side, depletion is prevented even if the thin film transistor 2 (cell transistor) is overerased.

Next, an equivalent circuit diagram of the nonvolatile semiconductor memory device 1 having the above structure will be described with reference to FIG. As shown in FIG. 2, memory cells 3 to 8 are arranged vertically and horizontally, the memory cells 3 to 5 are connected by a word line 22 (22a), and the memory cells 6 to 8 are connected by a word line 22 (22b). .
The diffusion layers (source / drain regions) of the memory cells 3 and 6 are connected to the diffusion layer wirings 13 (13a) and 13 (13b), and the diffusion layers (source / drain regions) of the memory cells 4 and 7 are diffusion layer wirings. The diffusion layers (source / drain regions) of the memory cells 5 and 8 connected to 13 (13b) and 13 (13c) are diffusion layer wirings 13 (13c) and 13 (13d).
It is connected to the.

For example, when writing data to the memory cell 4, the word line 22 (22a), which is the selected word line, is set to a high potential of, for example, 12V, and the other word line 22 (22b).
To ground. Further, the diffusion layer wiring 13 (13c) connected to the drain of the selected cell and the diffusion layer wiring 1 on the right side of the drawing.
3 (13d) is set to 5V, and the remaining diffusion layer wiring 13 on the left side
Ground all a and 13b. As a result, current flows only in the selected cell, and writing is performed by hot electron injection.

On the other hand, when reading the same cell, the word line 22a which is the selected word line is set to 5V, for example, and the other word line 22b is grounded. Further, the wiring 13c connected to the drain of the selected cell and the wiring 13d on the right side thereof are equalized to 2V, and the remaining wirings 13a and 13b on the left side are all grounded. In this state, if the memory cell 4 is in the erased state,
The diffusion layer wiring 13c is connected to the diffusion layer wiring 1 via the memory cell 4.
The electric charge is discharged to 3b, and the electric potential thereof is lowered to an intermediate electric potential between 2V and 0V and is read.

Erasing may be performed, for example, on all word lines 2 in the array.
2 to 0V, and each diffusion layer wiring 13 to be a bit / source line
Is set to 12 V, and electrons are extracted from the floating gate to the diffusion layer wiring 13.

Next, an example of the embodiment of the manufacturing method according to the present invention will be described with reference to the manufacturing process diagrams of FIGS. 3 and 4, the same components as those described with reference to FIG. 1 are designated by the same reference numerals, and FIGS.
(1) and (2) are shown in a sectional view, and (3) in FIG. 4 is shown in a perspective sectional view.

As shown in FIG. 3A, in the first step, a local oxidation method [eg, LOCOS (Local Oxidatio) is used.
n of Silicon) method]
An element isolation insulating film 12 that electrically isolates a diffusion layer region is formed on a semiconductor substrate 11. Then, by ion implantation, phosphorus or arsenic is ion-implanted into the diffusion layer region to form the diffusion layer wiring 13 serving as a bit line and a source line.
(13a to 13c) are formed in parallel so as to be sandwiched between the element isolation insulating films 12.

Further, the second step is carried out. In the second step, each diffusion layer wiring 13 is formed by an oxide film forming technique.
The first insulating film 14 is formed of a silicon oxide film having a thickness of 50 nm on the surface of the. As an example of the film forming technique, a chemical vapor deposition method or a thermal oxidation method is adopted.

Next, as shown in FIG. 3B, an opening 15 is formed in the first oxide film 14 on one side of each diffusion layer wiring 13 by lithographic technique and etching. The opening 15 becomes a connection between the source / drain region of the thin film transistor to be formed later and the diffusion layer wiring 13. After that, an amorphous silicon layer 31 to be a semiconductor layer of a thin film transistor is formed on the entire upper surface of the semiconductor substrate 11 by, for example, 1 by chemical vapor deposition.
It is formed to a thickness of 00 nm.

Subsequently, the third step is performed. In this process,
As shown in (3), the amorphous silicon layer 31 (see FIG. 3B) is crystallized by a process such as sacrificial oxidation and annealing to form a semiconductor layer 16 made of polycrystalline silicon. Further, the second insulating film 19 is formed on the surface of the semiconductor layer 16 by using a thermal oxidation method or a high temperature oxidation (HTO) method. The second insulating film 19 is made of a silicon oxide film having a thickness of 10 nm, for example, and functions as a gate oxide film. At this time, impurities are diffused from the diffusion layer wiring 13 to the semiconductor layer 16 through the opening 15 to form the source / drain regions 17 of the cell transistor. Then, the semiconductor layer 16 between the source / drain regions 17
Becomes the channel region 18.

Next, the fourth step is performed. In this step, a polycrystalline silicon film is formed on the entire surface of the second insulating film 19 [see (3) of FIG. 3] by a chemical vapor deposition method, and then by a lithographic technique and etching.
As shown in FIG. 4A, a gate pattern 32 for forming a floating gate is formed so as to cover only a part of the thin film transistor on the channel region 18 via the second insulating film 19. The gate pattern 32 is formed on one side of the channel region 18 between the source / drain regions 17 so as to be offset.

Then, the fifth step is performed. In this step, as shown in (2) of FIG. 4, by chemical vapor deposition,
The third insulating film 21 is formed so as to cover the gate pattern 32. The third insulating film 21 is, for example, a silicon oxide film /
It is formed of a laminated film including a silicon nitride film / silicon oxide film. Then, a conductive layer 33 is formed on the entire upper surface of the semiconductor substrate 11 so as to cover the third insulating film. The conductive layer 33 is formed of, for example, a polycide structure, and a chemical vapor deposition method is adopted as a film forming method thereof.

Further, a sixth step is carried out. In this step, as shown in FIG. 4C, patterning is performed from the conductive layer 33 to the semiconductor layer 16 by lithographic technique and etching. Then, the word line 22 is formed in the direction crossing the diffusion layer wiring 13 with the conductive layer 33. Further, using the same mask, the floating gate 20 is formed below the word line 22 with the gate pattern 32 (see FIG. 4B) through the third insulating film 21. Further, the semiconductor layer 16 is patterned below the word line 22 via the third insulating film 21, the floating gate 20 and the second insulating film 19, and the source / drain region 17 and the semiconductor layer 16 between the source / drain regions 17 are patterned. The channel region 18 is formed by.

In the above manufacturing method, the etching mask (not shown) formed by the lithographic technique is removed after etching. Further, the ion implantation mask (not shown) used in the ion implantation method is also removed after the ion implantation. Furthermore, the film thickness used in the above description is an example, and any film thickness that satisfies the function of each film may be used.

In the above manufacturing method, since the diffusion layer wirings 13 are formed in parallel with each other with the element isolation insulating film 12 sandwiched therebetween, the diffusion layer wirings 13 are separated by the element isolation insulating film 12. The diffusion layer wiring 13 becomes a bit line and a source line. Therefore, punch through does not occur between the diffusion layer wirings 13. Further, since each diffusion layer wiring 13 is formed after the element isolation insulating film 12 is formed, the diffusion layer wiring 13 does not cause accelerated diffusion, and the element isolation insulating film 12 is formed by a method utilizing a thermal oxidation method. Can be formed. Further, after the source / drain regions 17 are formed, there is no thermal process that causes accelerated diffusion, so that the source / drain regions 17 do not expand and the channel region 18 does not narrow. Therefore, the short channel effect and punch through do not occur.

A first insulating film 14 is formed on each diffusion layer wiring 13.
To form the opening 15 in the first insulating film 14, further form the semiconductor layer 16, and form the source / drain region 17 in the semiconductor layer 16 on the opening 15.
Diffusion layer wiring 13 serving as a bit line and a source line and semiconductor layer 16 serving as thin film transistor 2 are formed in a stacked state. Further, since the openings 15 are formed on the element isolation insulating film 12 side, the source / drain regions 17 are also formed on the element isolation insulating film 12 side. for that reason,
Since the semiconductor layer 16 on the first insulating film 14 also functions as the channel region 18, the thin film transistor 2 has a long channel length Lc without narrowing each diffusion layer wiring 13 and increasing its resistance. Therefore, there is no restriction due to punch through of the thin film transistor 2, and as a result, the cell area can be reduced.

The first insulating film 14 prevents the diffusion layer wirings 13 serving as bit lines and word lines from being broken even if the semiconductor substrate 11 is dug when over-etching is performed during processing of the word lines 22 and the floating gates 20. To compensate. That is, since the portion covered with the first insulating film 14 is not etched, the diffusion layer wiring 13 remains in that portion.

Further, the floating gate 20 is replaced by the channel region 18
Since only a part of the cell transistor is formed so as to be covered with the second insulating film 19, the depletion is prevented even if the cell transistor is overerased.

[0039]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the element isolation insulating film is formed between the diffusion layer wirings arranged in parallel on the semiconductor substrate. It is possible to prevent punch-through between layer wirings. Further, since the thin film transistors are formed on each diffusion layer wiring to be a bit line and a source line, the resistance of each diffusion layer wiring, the thin film transistor punch through, as the cell area of the thin film transistor is reduced. There is no restriction such as short channel effect. for that reason,
The memory cell can be downsized, and the unit price per bit can be reduced. Further, an insulating film is formed on the diffusion layer wiring in a state of being continuous with the element isolation insulating film, and according to the insulating film formed by extending the channel region of the thin film transistor, the channel length becomes long, It is possible to suppress punch through in the thin film transistor.
Further, the floating gate formed on the channel region and offset to one side can prevent depletion even if the cell transistor (thin film transistor) is overerased.

According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, after the element isolation insulating film is formed on the semiconductor substrate, the diffusion layer wirings are formed in parallel by separating with the element isolation insulating film. The layer wiring can be electrically separated by an element isolation insulating film. Further, after forming the source / drain regions, there is no thermal process for causing accelerated diffusion, so that the source / drain regions do not expand and the channel region does not narrow. Therefore, the short channel effect and punch through do not occur, so that the transistor characteristics can be improved. Further, since the diffusion layer wiring that becomes the bit line or the source line and the semiconductor layer that becomes the thin film transistor are formed in a stacked state, the width of the source / drain region can be increased without reducing the width of each diffusion layer wiring and increasing the resistance. Can be narrowed to increase the channel length. Further, according to the method of forming the opening formed in the first insulating film on each diffusion layer wiring on the element isolation insulating film side, the gap between the source / drain regions formed in the semiconductor layer on each opening is increased. Since it is longer, the channel region can be formed longer.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment related to a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is an equivalent circuit diagram of the nonvolatile semiconductor memory device according to the embodiment.

FIG. 3 is a manufacturing process diagram of the nonvolatile semiconductor memory device.

FIG. 4 is a manufacturing process diagram of a nonvolatile semiconductor memory device (continued)
It is.

FIG. 5 is a schematic configuration diagram of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1 Non-Volatile Semiconductor Storage Device 2 Thin Film Transistor 11 Semiconductor Substrate 12 Element Isolation Insulating Film 13 Diffusion Layer Wiring 17
Source / drain region Lc Channel length

Claims (8)

[Claims] 1. A diffusion layer wiring formed in parallel on a semiconductor substrate, an element isolation insulating film formed between the diffusion layer wirings, a source / drain region connected to each of the diffusion layer wirings, and A nonvolatile semiconductor memory device comprising: a thin film transistor having a channel length direction formed in a direction crossing over a diffusion layer wiring. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising an insulating film formed on one side of each diffusion layer wiring so as to be continuous with the element isolation insulating film, and the insulating film formed on the insulating film. A non-volatile semiconductor memory device characterized in that a channel region of a thin film transistor is extended and formed. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the thin film transistor includes a floating gate between a channel region of the thin film transistor and a gate electrode via an insulating film, and the floating gate includes the channel region. A method of manufacturing a non-volatile semiconductor memory device, which is formed above and offset to one side. 4. The nonvolatile semiconductor memory device according to claim 2, wherein the thin film transistor includes a floating gate between a channel region of the thin film transistor and a gate electrode via an insulating film, and the floating gate includes the channel region. A method of manufacturing a non-volatile semiconductor memory device, which is formed above and offset to one side. 5. An element isolation insulating film for isolating a diffusion layer region is formed on a semiconductor substrate, and then diffusion layer wiring is formed on the semiconductor substrate separated by the element isolation insulating film with the element isolation insulating film interposed therebetween. A first step of forming in parallel, and after forming a first insulating film on each of the diffusion layer wirings, the first insulating film on a part of each of the diffusion layer wirings is removed to form an opening, and then A second step of forming a semiconductor layer on the entire upper surface of the semiconductor substrate, and forming a second insulating film on the surface of the semiconductor layer,
A third step of forming a source / drain region by diffusing impurities from the respective diffusion layer wirings into the semiconductor layer above the opening; and forming a second insulating film on the semiconductor layer between the source / drain regions. A fourth step of forming a gate pattern for forming a floating gate via a third insulating film on the surface of the gate pattern,
Fifth step of forming a conductive layer on the entire upper surface of the semiconductor substrate, patterning from the conductive layer to the semiconductor layer, forming a word line across the diffusion layer wiring in the conductive layer, the gate In a pattern, a floating gate is formed below the word line via the third insulating film, and the source / drain is formed below the word line via the third insulating film, the floating gate and the second insulating film. A sixth step of forming a channel region in the semiconductor layer between the regions, the method for manufacturing a nonvolatile semiconductor memory device. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the opening is formed on the first side of one side of each diffusion layer wiring.
A method for manufacturing a non-volatile semiconductor memory device, which is formed by removing an insulating film. 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the gate pattern is formed on one side of the semiconductor layer between the source / drain regions via the second insulating film. A method of manufacturing a nonvolatile semiconductor memory device, comprising: 8. The method of manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein the gate pattern is formed on one side of the semiconductor layer between the source / drain regions with the second insulating film interposed therebetween. A method of manufacturing a nonvolatile semiconductor memory device, comprising: