JP2876974B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to an electrically writable / erasable nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a nonvolatile semiconductor memory device, EPR is used.
OM and EEPROM are widely used. FIG.
2 shows a partial cross section of a conventional flash EEPROM. This EEPROM includes a p-type silicon substrate 1 on which a channel region (p-type diffusion layer) 2, an n-type drain region 3 and a source region 4 are formed, a control gate electrode 8 and a floating gate electrode formed on the silicon substrate 1. 9 is provided. A first gate insulating layer 5 is provided between the floating gate electrode 9 and the silicon substrate 1, and a second gate insulating layer 6 is provided between the floating gate electrode 9 and the control gate electrode 8. These electrodes 8 and 9 correspond to the silicon oxide film 1
Covered by 0. The bit line 12 runs on the silicon oxide film 10 so as to connect to the drain region 3 through a contact hole provided in the silicon oxide film 10.

FIG. 11 shows one non-volatile memory cell (or memory cell transistor) of a non-volatile semiconductor memory device. In reality, a large number of memory cells exist on the silicon substrate 1. . Each memory cell is electrically isolated by an element isolation film 15 such as LOCOS formed in a predetermined region of the silicon substrate 1.

[0004] Storage of information in the nonvolatile semiconductor memory device is achieved by accumulation / non-accumulation of charges in the floating gate electrode 9. Since the accumulation / non-accumulation of the charge in the floating gate electrode 9 affects the magnitude of the inversion threshold of the transistor, the stored information is read depending on the magnitude of the drain current.

[0005]

However, the above-mentioned prior art has the following problems.

When an operation of injecting or releasing charges into or from the floating gate electrode 9 is performed, the control gate electrode 8 or the bit line 1
2 is given a relatively high potential. Therefore, a parasitic MOS structure of word line (control gate electrode 8) / element isolation film 15 / silicon substrate 1 is formed between adjacent memory cells, and as a result, a conduction channel is formed on the surface of silicon substrate 1. Sometimes. Such a conduction channel destroys the isolation of adjacent memory transistors. In order to maintain element isolation, the element isolation film 15 needs to be thick and wide. This is against high integration of memory transistors.

In general, it is necessary to increase the operating current (eg, drain current) of a transistor in order to improve the reading speed. However, in the conventional nonvolatile semiconductor memory device, when the channel width of the transistor is reduced for further miniaturization, the operating current is reduced.

Further, according to the above-described configuration, the inversion threshold voltage (Vt) between the memory cell transistors is likely to vary in magnitude. Therefore, it is necessary to perform batch writing before the erasing operation or to repeat the erasing operation (or the writing operation) and the verification of the threshold voltage (the verifying operation). This increases the time required for erasing (or writing).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to secure electrical isolation between adjacent memory cell transistors.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of miniaturizing and highly integrating a memory cell, and a method of manufacturing the same.

Another object of the present invention is to provide a nonvolatile semiconductor memory device in which the reading speed is improved and the erasing time is reduced, and a method of manufacturing the same.

[0011]

According to the present invention, there is provided a nonvolatile semiconductor memory cell comprising: a first conductivity type semiconductor substrate having an upper surface; a first conductivity type annular channel region formed on the upper surface of the semiconductor substrate; A second conductive type drain region formed in a region of the upper surface of the semiconductor substrate surrounded by the annular channel region; and a second conductive type drain region formed in the upper surface of the semiconductor substrate outside the annular channel region. A type source region;
A first gate insulating layer formed on the upper surface of the semiconductor substrate so as to cover a boundary between the annular channel region and the drain region; an annular floating gate electrode formed on the first gate insulating layer; A second gate insulating layer formed on the surface of the annular floating gate electrode; and a control gate electrode capacitively coupled to the annular floating gate electrode via the second gate insulating layer, wherein the control gate electrode is electrically connected to the semiconductor substrate. And a control gate electrode that is insulated and separated, thereby achieving the above object.

In one embodiment, the control gate electrode comprises:
The upper surface of the annular floating gate electrode is covered.

In one embodiment, the annular floating gate electrode covers at least a part of the upper surface of the control gate electrode and the inner side surface of the opening.

In one embodiment, the annular floating gate electrode is a sidewall provided on an inner surface of the control gate electrode opening.

In a preferred embodiment, there is provided a third gate insulating layer formed on an upper surface of the semiconductor substrate so as to cover a boundary between the annular channel region and the source region,
The semiconductor device further includes a third gate insulating layer for insulating and separating the semiconductor substrate and the control gate electrode, and the control gate electrode faces the boundary via the third gate insulating layer.

In a preferred embodiment, the first gate insulating layer is thinner than the third gate insulating layer.

According to the nonvolatile semiconductor memory device of the present invention,
A first conductivity type semiconductor substrate having an upper surface, a memory cell array region provided on the upper surface of the semiconductor substrate, a plurality of nonvolatile memory cells arranged in the memory cell array region, and a plurality of nonvolatile memory cells. A non-volatile semiconductor memory device comprising a word line and a bit line for interconnection, wherein each of the plurality of non-volatile memory cells includes a first conductive type annular channel formed on the top surface of the semiconductor substrate. A region, a second conductivity type drain region formed in a region surrounded by the annular channel region on the top surface of the semiconductor substrate, and a second conductivity type drain region formed outside the annular channel region on the top surface of the semiconductor substrate. A first conductive type source region formed on the upper surface of the semiconductor substrate so as to cover a boundary between the circular channel region and the drain region.
A gate insulating layer, an annular floating gate electrode formed on the annular first gate insulating layer, a second gate insulating layer formed on the surface of the annular floating gate electrode, and the second gate insulating layer. A control gate electrode capacitively coupled to the annular floating gate electrode, and a control gate electrode electrically insulated and separated from the semiconductor substrate; at least a part of the plurality of nonvolatile memory cells , The source region is shared, and each of the plurality of word lines partially includes the control gate electrode, thereby achieving the above object.

In one embodiment, the control gate electrode comprises:
The upper surface of the annular floating gate electrode is covered.

In one embodiment, the annular floating gate electrode covers at least a part of the upper surface of the control gate electrode and the inner side surface of the opening.

In one embodiment, the annular floating gate electrode is a sidewall provided on an inner surface of the control gate electrode opening.

In a preferred embodiment, a third gate insulating layer formed on the upper surface of the semiconductor substrate so as to cover a boundary between the annular channel region and the source region,
The semiconductor device further includes a third gate insulating layer for insulating and separating the semiconductor substrate and the control gate electrode, and the control gate electrode faces the boundary via the third gate insulating layer.

In a preferred embodiment, an element isolation region for isolating the memory cell is not provided in the memory cell array region.

In a preferred embodiment, an insulating film is provided between the semiconductor substrate and a portion other than the control gate electrode in each of the plurality of word lines, and the insulating film is formed on the third gate line. Thicker than the insulating layer.

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention, comprising the steps of: forming a second conductivity type diffusion layer to be a source region on an upper surface of a first conductivity type semiconductor substrate; (3) a step of forming a first insulating layer to be a gate insulating layer on the semiconductor substrate; a step of depositing a first conductive film to be a control gate electrode on the first insulating layer; Patterning the first insulating layer, thereby obtaining an outer shape of the control gate electrode; and depositing a second insulating layer on the semiconductor substrate so as to cover the patterned first conductive film. Providing openings in the patterned first conductive film and the first and second insulating layers, thereby exposing a portion of the semiconductor substrate and removing the third gate insulating layer from the first insulating layer; Forming a layer and the semiconductor substrate Forming a first conductivity type diffusion layer serving as a channel region in a portion exposed through the opening; forming a first gate insulating layer on the semiconductor substrate in the opening; forming a layer on the first over the conductive film, forming a cyclic floating gate electrode on the first gate insulating layer, the floating gate portion of the first conductivity type diffusion layer serving as the channel region Second through the electrode opening
Forming a second conductivity type diffusion layer that becomes a drain region by doping with a conductivity type impurity, thereby achieving the above object.

In one embodiment, the step of forming the annular floating gate electrode includes a step of depositing a second conductive film to be the annular floating gate electrode on the semiconductor substrate and an anisotropic etching of the second conductive film. by etching back by law, the second electrically to the inner wall surface of the opening portion of the first conductive film
Leaving a portion of the electrofilm and thereby forming an annular floating gate electrode.

In one embodiment, the method further includes a step of forming a sidewall insulating layer on the inner side surface of the ring-shaped free gate electrode after forming the second conductivity type diffusion layer serving as a drain region.

In a preferred embodiment, the first gate insulating layer and the second gate insulating layer are formed simultaneously.

Another method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a first conductivity type diffusion layer to be a channel region on an upper surface of a first conductivity type semiconductor substrate; Forming a first insulating layer on the semiconductor substrate, depositing a first conductive film to be a floating gate electrode on the first insulating layer, and forming the first conductive film and the first conductive film on the first insulating layer.
Patterning the insulating layer, the thereby obtaining a outer shape of the floating gate electrode, which is the patterning
Forming a second gate insulating layer on the first conductive film , forming a third gate insulating layer on the semiconductor substrate, and forming the second conductive layer on the semiconductor substrate so as to cover the patterned first conductive film ; Depositing on the substrate, the patterned first
So as to cover the conductive film, depositing a second insulating layer on said semiconductor substrate, said second insulating layer, the second conductive layer, said first electrically
Patterning the conductive film and the first insulating layer, thereby obtaining an annular floating gate electrode having an opening and a control gate electrode; and using the control gate electrode as a mask to deposit a second conductivity type impurity in the semiconductor substrate. And thereby forming a source region and a drain region, whereby the above object is achieved.

In one embodiment, after the step of forming the source region and the drain region, the method further includes the step of forming a sidewall insulating layer on the inner side surface of the opening of the annular floating gate electrode and the control gate electrode. ing.

In a preferred embodiment, the second gate insulating layer and the third gate insulating layer are formed simultaneously.

[0031]

The nonvolatile semiconductor memory cell according to the present invention has an annular channel region formed on the upper surface of a semiconductor substrate, a drain region formed in a region surrounded by the annular channel region, and an outer region formed outside the annular channel region. Source region. By adopting such an annular structure as the shape of the channel region, the effective channel width in each memory cell is increased, thereby increasing the current (drain current) flowing between the source region and the drain region. be able to. Since the information stored in the nonvolatile memory cell is detected by the drain current, the increase in the drain current increases the read speed.

According to the present invention, the floating gate electrode also has an annular structure, and this floating gate electrode is provided at the boundary (drain junction) between the annular channel region and the drain region via the first gate insulating layer. Are facing each other. As a result, the floating gate electrode can effectively apply an electric field to the drain junction.

A second gate insulating layer is formed on the surface of the annular floating gate electrode, and a control gate electrode is provided so as to be capacitively coupled to the floating gate electrode via the second gate insulating layer. The control gate electrode of each memory cell may be formed integrally with the word line as part of the word line interconnecting each memory cell.

According to the present invention, the above structure eliminates the need for providing an element isolation region between adjacent nonvolatile memory cells. Further, electric interference does not occur between adjacent memory cells via the parasitic MOS transistor.

Various configurations can be adopted as the arrangement relationship between the annular floating gate electrode and the control gate electrode, and the degree of capacitive coupling can be adjusted. Also, if the annular floating gate electrode is provided as a sidewall on the inner side surface of the opening provided in the control gate electrode, the annular floating gate electrode can be formed in a self-aligned manner, and the manufacturing process is simplified, And,
Fine memory cells can be obtained with good yield.

Further, by providing the control gate electrode at the boundary (source junction) between the annular channel region and the source region via the third gate insulating layer, an electric field is applied from the control gate electrode to the source junction. Effect efficiently,
Since the inversion threshold voltage (Vt) of the memory cell transistor can be controlled, it is possible to suppress the variation of Vt in the erase operation (or the write operation), and the verify operation becomes unnecessary.

[0037]

The present invention will be described below with reference to examples.

Embodiment 1 A first embodiment of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to FIGS. 1A and 1B and FIGS. 2 and 3. These figures show a part of the memory cell array region of the present nonvolatile semiconductor memory device.

In this embodiment, a p-type silicon substrate 1 is used as a semiconductor substrate. p-type silicon substrate 1
As shown most clearly in FIG. 3, a plurality of p-type annular channel regions 2 and a plurality of n-type drain regions (each having a diameter of about 0.
9 μm) 3 and a common n-type source region 4 formed outside the annular channel region 2. In this embodiment, the channel length is set to 0.3 μm and the channel width is set to 3.14 μm (= 0.5 μm × 2π).

The nonvolatile semiconductor memory device of this embodiment includes a number of nonvolatile memory cells (memory cell transistors) corresponding to the number of the drain regions 3 in the memory cell array region. Includes peripheral circuits such as a drive circuit for driving these nonvolatile memory cells.

As shown in FIG. 1B, an annular channel region 2 and a drain region 3 are formed on the upper surface of a silicon substrate 1.
An annular first gate insulating layer (thickness: 10 nm) 5 is formed so as to cover the boundary (pn junction) between the first gate insulating layer and the gate insulating layer. On this annular first gate insulating layer 5, an annular floating gate electrode (thickness measured in parallel with the upper surface of the substrate 1: about 200 nm) 9
Are formed. A second gate insulating layer (thickness: 20 nm) 6 is formed on the outer surface of the annular floating gate electrode 9.

On the third gate insulating layer (thickness: 30 nm) 7 formed on the silicon substrate 1, a control gate electrode 8
Is provided. The control gate electrode 8 is insulated from the annular floating gate electrode 9 by the second gate insulating layer 6. In other words, the control gate electrode 8 is capacitively coupled to the annular floating gate electrode 9 via the second gate insulating layer 6.

FIG. 2 shows a plan layout of the control gate electrode 8, the floating gate electrode 9, and the like. As can be seen from FIG. 2, the control gate electrode 8 of each nonvolatile memory cell
Are integrated with the word line as a part of the word line, and surround the outer surface of the annular floating gate electrode 9.
As described above, between each annular floating gate electrode 9 and the control gate electrode 8 surrounding it, the second
A gate insulating layer 6 (not shown in FIG. 2) is provided.

A pair of adjacent word lines may be electrically interconnected in a region not shown in FIG. 2 (outside the memory cell array region). In that case, it is not necessary to provide a space between the pair of word lines in the memory cell array region. Therefore, a planar layout in which each pair of word lines is one word line may be adopted, thereby further improving the degree of integration.

As shown in FIG. 1B, a silicon oxide film (thickness: 350 nm) 10 is formed on the control gate electrode 8.
Is provided, and the inner side surface of the annular floating gate electrode 9 is covered with a sidewall insulating film (thickness: 250 nm) 11. The silicon oxide film 10 and the side wall insulating film 11 are composed of a control gate electrode 8 and an annular floating gate electrode 9.
Is electrically separated from the bit line 12 (FIG. 1).
(See (a) and (b)).

The control gate electrode 8 is opposed to the boundary between the annular channel region 2 and the source region 4 (pn junction on the upper surface of the silicon substrate 1) via the third gate insulating layer 7 in FIG. doing.

Hereinafter, the operation method of this embodiment will be described.
When writing information to a memory cell, bit lines 12,
Voltages of 5 volts, -8 volts, and 0 volts are applied to the word line (control gate electrode 8) and the silicon substrate 1, respectively. When erasing information from the memory cell, voltages of -8 volts, 8 volts, and -8 volts are applied to the bit line 12, the word line (control gate electrode 8), and the silicon substrate 1, respectively. During the write / erase operation, the source region 4 is put in a floating state. When reading information from the memory cell, voltages of 1 volt, 3 volts, 0 volt and 0 volt are applied to the bit line 12, the word line (control gate electrode 8), the source region 4 and the silicon substrate 1, respectively. I do. During the information reading operation, a drain current flowing between the source region 4 and the drain region 3 is detected.

The following effects can be obtained from the above configuration. (1) An insulating isolation region (for example, a LOCOS region) for isolating each transistor is unnecessary. For this reason,
A large number of transistors can be integrated at a high density in a limited area.

(2) The channel width of each transistor is
Since it is determined by the average circumference length of the annular channel region 2, a channel width relatively long with respect to the area occupied by one transistor can be obtained.

(3) By adjusting the thickness of the third gate insulating layer 7, the electric field effect exerted on the annular channel region 2 from the control gate electrode 8 can be controlled with high precision. V in write operation)
The variation in t can be suppressed, and the verify operation becomes unnecessary.

(4) Since the first gate insulating layer 5 is thinner than the third gate insulating layer 7, charge transfer is easily performed during writing / erasing, so that efficient writing / erasing is performed. On the other hand, the electric field acting on the third gate insulating layer 7 becomes relatively small, and the third
The deterioration of the gate insulating layer 7 is prevented.

Hereinafter, the manufacturing method of this embodiment will be described with reference to FIGS.

First, phosphorus (P) ions are implanted into the memory cell array region of the silicon substrate 1 in which the p-type impurity is lightly doped, and as shown in FIG. An n ⁺ type diffusion layer 4 ′ to be the type source region 4 is formed. An example of the injection condition is acceleration energy 4
The dose is 0 keV and the dose is 2 × 10 ¹⁴ cm ⁻² .

Next, an oxide film (thickness: 30 nm) to be the third gate insulating layer 7 is formed on the upper surface of the silicon substrate 1 by subjecting the upper surface of the silicon substrate 1 to thermal oxidation (for example, pyro oxidation at 900 ° C.). 7 'is formed. The oxide film 7 '
A polycrystalline silicon film (thickness: 350 n)
m) After depositing 8 ', the polysilicon film 8' is doped with an impurity (for example, phosphorus), thereby giving the polysilicon film 8 'high conductivity.

Next, the resist layer 1 having a pattern for defining the shape and position of the outer surface of the control gate electrode 8
3 is formed on the polycrystalline silicon film 8 'by photolithography. Using the resist layer 13 as a mask, the exposed portions of the polycrystalline silicon film 8 'and the oxide film 7' are selectively etched away by anisotropic etching (for example, RIE). Thus, as shown in FIG. 4B, the outer shapes of the control gate electrode (word line) 8 and the third gate insulating layer 7 are formed. However, at this stage, an opening has not yet been formed in the control gate electrode 8.

After removing the resist 13, a silicon oxide film (thickness: 350 nm) 10 is formed on the polycrystalline silicon film 8 ′.
Is deposited on the entire surface of the silicon substrate 1 so as to cover.

Thereafter, a resist layer 14 having a pattern defining an opening (corresponding to the drain region 3) of the polycrystalline silicon film 8 'is formed by photolithography.
It is formed on the silicon oxide film 10. Using the resist layer 14 as a mask, the exposed portions of the silicon oxide film 10 and the polycrystalline silicon film 8 'are selectively etched and removed by anisotropic etching to form openings in the polycrystalline silicon film 8'. A region to be the drain region 3 of the substrate 1 is exposed.

Thus, as shown in FIG.
The control gate electrode 8 whose upper surface is covered with the silicon oxide film 10 and has an opening is obtained.

Thereafter, p-type ions are implanted into portions (a plurality of disk-shaped portions) exposed on the upper surface of the silicon substrate 1, thereby first forming a channel region (p-type diffusion layer).
Form 2 At this time, the conditions for implanting boron ions are adjusted so that the layer thickness of the channel region 2 is larger than the layer thickness of the n ⁺ -type diffusion layer serving as the source region 4. The channel region 2 is formed so as to be electrically connected to the p-type silicon substrate 1. In order to form the channel region 2, for example, boron ions of 1 × 10 ¹⁵ cm ⁻² are implanted at 50 keV and then BF ₂ ions of 1 × 10 ¹⁵ cm ⁻² are implanted at 40 keV.
V may be implanted.

Thereafter, the silicon substrate 1 and the gate electrode 8
Of the first gate insulating layer (thickness: 10 nm) by simultaneously thermally oxidizing (pyro-oxidizing at 800 ° C.)
And a second gate insulating layer (thickness: 20 nm) 6. Next, after a conductive polycrystalline silicon film serving as the floating gate electrode 9 is deposited on the entire surface of the silicon substrate 1 by the CVD method, the polycrystalline silicon film and the first gate insulating layer 5 are etched back by the RIE method. Thereby, an annular floating gate electrode 9 is formed (without a mask process). As shown in FIG. 4D, the polycrystalline silicon film is completely removed from the silicon oxide film 10 by this etch back, and as a result, each annular floating gate electrode 9 is formed.
Are electrically separated from each other. Further, inside the opening of the control gate electrode 8, the surface of the p-type diffusion layer 2 is exposed except for the vicinity of the inner wall of the opening.

Next, by implanting arsenic (As) ions into the exposed surface of the channel region 2, an n ⁺ -type drain region 3 is formed in a self-aligned manner with respect to the opening.
At this time, the implantation conditions are adjusted so that the layer thickness of the drain region 3 is smaller than the thickness of the channel region. For example, arsenic of 1 × 10 ¹⁶ cm ⁻² is implanted at 30 keV.

Next, after a silicon oxide film (thickness: 250 nm) to be the side wall oxide film 11 is deposited on the entire surface of the silicon substrate 1 by the CVD method, the silicon oxide film is formed by the anisotropic etching method. Etchback is performed, thereby forming a sidewall oxide film 11 as shown in FIG. This side wall oxide film 11 is
Has a structure that completely covers the inner side surface of the substrate and secures stable contact between the drain region 3 and the bit line 12 (not shown in FIG. 4E).

Thereafter, a bit line 12 shown in FIGS. 1A and 1B is formed by a metallization process.
Is formed. Each bit line 12 connects a plurality of drain regions of transistors arranged along the horizontal direction in FIG. 1A to a peripheral circuit (not shown). Bit line 1
As 2, those having a TiN / Al structure are preferable. Before the bit line 12 is brought into direct contact with the drain region 3, the opening may be buried using, for example, a high melting point structure of a W / TiN / Ti structure.

The method shown in FIGS. 4A to 4E achieves the following effects. (1) The floating gate electrode 9 and the sidewall oxide film 11 are formed in a self-aligned manner with respect to the opening of the control gate electrode 8 by film deposition and etchback without a mask. As a result, mask alignment in the photolithography step for forming the floating gate electrode 9 and the side wall oxide film 11 becomes unnecessary.

(2) The channel length (the distance between the source region 4 and the drain region 3) is controlled by adjusting the thickness of the polycrystalline silicon film serving as the annular floating gate electrode 9. As a result, according to the above method, the channel length can be reduced beyond the resolution limit of photolithography.

(3) The size of the drain contact region (the region where each drain region 3 is in contact with the corresponding bit line 12) is controlled by adjusting the thickness of the silicon oxide film serving as the sidewall oxide film 11. . As a result, according to the above method, the drain contact region can be miniaturized beyond the resolution limit of photolithography.

(Embodiment 2) A non-volatile semiconductor memory device according to a second embodiment of the present invention will be described below with reference to FIGS. These figures show a part of the memory cell array region of the present nonvolatile semiconductor memory device. The components of the second embodiment corresponding to the components of the first embodiment are denoted by the same reference numerals as those of the first embodiment.

Also in this embodiment, a p-type silicon substrate 1 is used as a semiconductor substrate. p-type silicon substrate 1
As shown most clearly in FIG. 7, a p-type channel region 2 having a plurality of openings and a plurality of n-type drain regions formed in the openings of the channel region 2 (diameter: 0.6 μm) 3 and an n-type source region 4 formed outside the channel region 2. Although the plurality of source regions 4 are shown separately in FIG. 5, these source regions 4 may be continuous in a region not shown so as to have a common potential.

The nonvolatile semiconductor memory device of this embodiment is similar to the first embodiment in that the memory cell array region has
It includes a number of nonvolatile memory cells corresponding to the number of the drain regions 3, and in a region not shown,
A peripheral circuit such as a drive circuit for driving these nonvolatile memory cells is included.

As shown in FIG. 5, on the upper surface of the silicon substrate 1, an annular first gate insulating layer (having a thickness: 100 nm) is formed so as to cover the boundary (pn junction) between the channel region 2 and the drain region 3. 10 nm) 5. On this annular first gate insulating layer 5, an annular floating gate electrode (thickness:
(200 nm) 9 is formed. On the surface of the annular floating gate electrode 9, a second gate insulating layer 6 is formed.

As shown in FIG. 5, a control gate electrode 8 is provided on the third gate insulating layer 7 and the second gate insulating layer 6 formed on the silicon substrate 1. Thus, the control gate electrode 8 covers the outer surface and the upper surface of the annular floating gate electrode 9 via the second gate insulating layer 6. That is, the control gate electrode 8 is capacitively coupled to the annular floating gate electrode 9 via the second gate insulating layer 6.

FIG. 6 shows a plan layout of the control gate electrode 8, the floating gate electrode 9, and the like. Each control gate electrode 8 is integrated with the word line as a part of the word line, and completely covers the annular floating gate electrode 9. As described above, the second gate insulating layer 6 (not shown in FIG. 6) for insulating separation is provided between each annular floating gate electrode 9 and the control gate electrode 8 covering the ring floating gate electrode 9.

As shown in FIG. 5, the control gate electrode 8
A silicon oxide film (thickness: 350 nm) 10 is provided thereon, and a sidewall insulating film (thickness: 250 nm) is provided on the inner side surfaces of the silicon oxide film 10, the control gate electrode 8, and the annular floating gate electrode 9. 11 are provided.

The control gate electrode 8 covers the boundary between the channel region 2 and the source region 4 in FIG. 7 via the third gate insulating layer 7.

Hereinafter, the manufacturing method of this embodiment will be described with reference to FIGS. 8 (a) to 8 (d).

First, boron (B) ions are implanted into the entire surface of the memory cell array region of the silicon substrate 1 lightly doped with p-type impurities.
As shown in FIG. 1A, a p-type diffusion layer 2 'serving as a channel region 2 is formed. The threshold value of the transistor is adjusted by adjusting the impurity concentration on the surface of the p-type diffusion layer 2 '. A part of the p-type diffusion layer 2 ′
Later, it also functions as a punch-through stop. For controlling the threshold voltage, 4 × 10 ¹³ cm ⁻² boron is used.
At 0 keV, boron of 1 × 10 ¹³ cm ⁻² was implanted at 80 keV to form a punch-through stop.

Next, the upper surface of the silicon substrate 1 is thermally oxidized (9
By performing pyro-oxidation at 00 ° C., an oxide film (thickness: 10 nm) 5 ′ to be the first gate insulating layer 5 is formed on the upper surface of the silicon substrate 1. CVD on the oxide film
After depositing a polycrystalline silicon film (thickness: 200 nm) 9 'by the method, the polycrystalline silicon film 9' is doped with an impurity (for example, phosphorus), thereby giving the polycrystalline silicon film 9 'high conductivity. give.

Next, the resist layer 1 having a pattern for defining the shape and position of the outer surface of the floating gate electrode 9
3 is formed on the polycrystalline silicon film 9 'by a photolithography technique. Using the resist layer 13 as a mask, the exposed portions of the polycrystalline silicon film 9 'and the oxide film 5' are selectively removed by anisotropic etching (for example, RIE). Thus, as shown in FIG. 8B, the floating gate electrode 9 and the first gate insulating layer 5 are formed.

After removing the resist 13, the second gate insulating layer 6 and the third gate insulating layer 7 are simultaneously formed by thermal oxidation. These insulating films may have an oxide film / nitride film / oxide film (ONO) structure (equivalent oxide film thickness: 25 nm).

Next, a polycrystalline silicon film (thickness: 250 nm) to be a control gate electrode 8 and a silicon oxide film 10
A silicon oxide film (thickness: 350 nm) to be formed is deposited on the entire surface of the silicon substrate 1 so as to cover the floating gate electrode 9.

Thereafter, a resist layer 14 having a pattern defining the shape of control gate electrode 8 is formed on the silicon oxide film by photolithography. Using the resist layer 14 as a mask, the exposed portions of the silicon oxide film and the polycrystalline silicon film are selectively etched and removed by RIE, thereby forming the control gate electrode 8 and the silicon oxide film as shown in FIG. The film 10 is formed (see FIG. 6). By this etching, the regions to be the drain region 3 and the source region 4 of the silicon substrate 1 are exposed.

Thereafter, arsenic (As) ions are implanted into portions exposed on the upper surface of silicon substrate 1, thereby forming drain region 3 and source region 4 in a self-aligned manner with control gate electrode 8. . At this time, arsenic ion implantation conditions are adjusted such that the layer thickness of the drain region 3 and the source region 4 is larger than the layer thickness of the p-type diffusion region 2 '. For example, arsenic of 4 × 10 ¹⁵ cm ⁻² is supplied at 30 keV.
Inject with. The shapes of the formed drain region 3 and source region 4 are as shown in FIG.

Thereafter, an oxide film is deposited on the entire surface of the silicon substrate 1 by the CVD method, and then the oxide film is etched back by the RIE method.
Then, a sidewall insulating film 11 is formed in the inner wall of the opening provided in the floating gate electrode 9, and the space between the control gate electrodes 8 is buried with the insulating film. Thus, FIG.
Is obtained.

Thereafter, as shown in FIG. 5, a bit line lead electrode 11 made of an n-type polycrystalline silicon film is formed on the drain region 3, and then a BPSG film (thickness: 60
0 nm) and reflow at 850 ° C. for 30 minutes. After that, the metallization process is used to
Is formed. Each bit line 12 connects a plurality of drain regions 3 of transistors arranged along the horizontal direction in FIGS. 6 and 7 to a peripheral circuit (not shown).

The method shown in FIGS. 8A to 8D provides the following effects. (1) The drain region 3 and the source region 4 are formed simultaneously and self-aligned with the control gate electrode 8.

(2) Due to the lateral diffusion, the junction (drain junction) between the drain region 3 and the channel region 2 moves directly below the first gate insulating layer 5, and as a result, the first gate insulating layer 5 Opposes the floating gate electrode 9 through the gate electrode.

(3) Similarly, a junction between the source region 4 and the channel region 2 (source junction) is formed by lateral diffusion.
Moves to a position directly below the third gate insulating layer 7 and consequently faces the control gate electrode 8 via the third gate insulating layer 7.

(Embodiment 3) A third embodiment of the nonvolatile semiconductor memory device according to the present invention will be described below with reference to FIG. FIG. 9 shows a part of the memory cell array region of the nonvolatile semiconductor memory device. The configuration of the present embodiment is substantially the same as the configuration of the first embodiment except for the points described below. The components of the fourth embodiment corresponding to the components of the second embodiment are denoted by the same reference numerals as those of the first embodiment.

Hereinafter, only the portions different from the first embodiment will be described. In the nonvolatile semiconductor memory device of this embodiment, the floating gate electrode 9 is formed not only on the side wall of the annular control gate electrode 8 but also on the upper surface thereof. That is, the control gate electrode 8 is covered with the annular floating gate electrode 9, and as a result, the facing area between the control gate electrode 8 and the floating gate electrode 9 increases, and the degree of capacitive coupling between them increases. I have. For this reason, it is possible to further reduce the write / erase voltage to be applied to the control gate electrode 8.

(Embodiment 4) Referring to FIG. 10, a fourth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described below. FIG. 10 shows a part of the memory cell array region of the nonvolatile semiconductor memory device. The configuration of the present embodiment is substantially the same as the configuration of the second embodiment except for the points described below. The components of the third embodiment corresponding to the components of the second embodiment are denoted by the same reference numerals as those of the second embodiment.

Hereinafter, only the portions different from the second embodiment will be described. In the nonvolatile semiconductor memory device according to the present embodiment, the silicon oxide film 15 is selectively provided under a portion of the word line that does not function as the control gate electrode 8 (that is, a wiring portion interconnecting the control gate electrode 8). It is provided in. The thickness of the silicon oxide film 15 is
It is sufficiently thicker than the thickness of the first gate insulating layer 5 (for example,
100 nm or more). As a result, the parasitic capacitance between the silicon substrate 1 and the word line is reduced. Reducing the parasitic capacitance leads to an increase in operation speed. Silicon acid film 1
5 is a device isolation (for example, LO
When forming COS), it can be formed simultaneously. In this case, there is no need to increase the number of manufacturing steps.

[0092]

According to the present invention, electrical interference does not occur between adjacent nonvolatile memory cells via a parasitic MOS transistor. For this reason, it is possible to avoid malfunction due to electrical interference while promoting the integration of the nonvolatile memory cell. Further, since no element isolation region is provided between the nonvolatile memory cells, the nonvolatile memory cells can be integrated at a high density. Further, by adopting the annular structure, the effective channel width can be sufficiently secured while reducing the area occupied by the nonvolatile memory cells. Therefore, the operating current of the memory cell transistor can be kept high. For this reason, without lowering the reading speed of information from the nonvolatile memory cells,
The area occupied by the nonvolatile memory cells can be reduced.

According to the manufacturing method of the present invention, a nonvolatile semiconductor memory device having fine nonvolatile memory cells can be manufactured with high accuracy. By omitting the masking process as much as possible and adopting a self-aligned process,
As a result of simplifying the manufacturing process, a highly integrated nonvolatile semiconductor memory device can be provided with a high yield.

[Brief description of the drawings]

FIG. 1A is a plan view showing a nonvolatile semiconductor memory device according to the present invention, and FIG. 1B is a sectional view taken along line BB of FIG.

FIG. 2 is a plan view showing a layout of a gate electrode of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 3 is a plan view showing a layout of source, channel, and drain regions of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 4 is a process cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 5 is a sectional view of another nonvolatile semiconductor memory device according to the present invention;

FIG. 6 is a plan view showing a gate electrode layout of the nonvolatile semiconductor memory device of FIG. 5;

FIG. 7 is a plan view showing a layout of source, channel, and drain regions of the nonvolatile semiconductor memory device of FIG. 5;

8 is a process cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device of FIG. 5;

FIG. 9 is a sectional view of still another nonvolatile semiconductor memory device according to the present invention.

FIG. 10 is a sectional view of still another nonvolatile semiconductor memory device according to the present invention;

FIG. 11 is a sectional view of a conventional nonvolatile semiconductor memory device (flash EEPROM).

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate 2 p-type diffusion layer 3 n-type drain region 4 n-type source region 5 first gate insulating layer 6 second gate insulating layer 7 third gate insulating layer 8 control gate electrode 9 floating gate electrode 10 silicon oxide film DESCRIPTION OF SYMBOLS 11 Side wall oxide film 12 Bit line 13 Resist layer 14 Resist layer 15 Element isolation film

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yohei Ichikawa 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-3-132079 (JP, A) 79369 (JP, A) JP-A-4-192565 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/115 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (20)

(57) [Claims] A first conductive type semiconductor substrate having an upper surface; a first conductive type annular channel region formed on the upper surface of the semiconductor substrate; and a first conductive type annular channel region surrounded by the annular channel region on the upper surface of the semiconductor substrate. A second conductivity type drain region formed in the region formed, a second conductivity type source region formed outside the annular channel region on the upper surface of the semiconductor substrate, the annular channel region and the drain region, A first gate insulating layer formed on the upper surface of the semiconductor substrate so as to cover the boundary of the semiconductor substrate; an annular floating gate electrode formed on the first gate insulating layer; and a surface formed on the surface of the annular floating gate electrode. A second gate insulating layer, a control gate electrode capacitively coupled to the annular floating gate electrode via the second gate insulating layer, the control gate electrode being electrically insulated and separated from the semiconductor substrate; Equipped Nonvolatile semiconductor memory cell. 2. The nonvolatile semiconductor memory cell according to claim 1, wherein said control gate electrode covers an upper surface of said annular floating gate electrode. 3. The nonvolatile semiconductor memory cell according to claim 1, wherein said annular floating gate electrode covers at least a part of an upper surface of said control gate electrode and an inner surface of an opening. 4. The nonvolatile semiconductor memory cell according to claim 1, wherein said annular floating gate electrode is a side wall provided on an inner side surface of said control gate electrode opening. 5. A third gate insulating layer formed on an upper surface of the semiconductor substrate so as to cover a boundary between the annular channel region and the source region, wherein the third gate insulating layer insulates the semiconductor substrate from the control gate electrode. 2. The non-volatile semiconductor memory cell according to claim 1, further comprising a third gate insulating layer for isolation, wherein said control gate electrode faces said boundary via said third gate insulating layer. . 6. The nonvolatile semiconductor memory cell according to claim 5, wherein said first gate insulating layer is thinner than said third gate insulating layer. 7. A first conductivity type semiconductor substrate having an upper surface, a memory cell array region provided on the upper surface of the semiconductor substrate, a plurality of nonvolatile memory cells arranged in the memory cell array region, and the plurality of nonvolatile memory cells. A nonvolatile semiconductor memory device comprising: a word line and a bit line for interconnecting nonvolatile memory cells, wherein each of the plurality of nonvolatile memory cells is formed on the upper surface of the semiconductor substrate. A first conductivity type annular channel region; a second conductivity type drain region formed in a region of the upper surface of the semiconductor substrate surrounded by the annular channel region; and an annular channel of the upper surface of the semiconductor substrate A second conductivity type source region formed outside the region, and an annular first region formed on the upper surface of the semiconductor substrate so as to cover a boundary between the annular channel region and the drain region. A gate insulating layer, and an annular floating gate electrode formed on the annular first gate insulating layer, a second formed on the surface of the annular floating gate electrode
A gate insulating layer; and a control gate electrode capacitively coupled to the annular floating gate electrode via the second gate insulating layer, the control gate electrode being electrically insulated and separated from the semiconductor substrate. A nonvolatile semiconductor memory, wherein at least a part of the plurality of nonvolatile memory cells share the source region, and each of the plurality of word lines includes the control gate electrode in a part thereof; apparatus. 8. The nonvolatile semiconductor memory device according to claim 7, wherein said control gate electrode covers an upper surface of said annular floating gate electrode. 9. The nonvolatile semiconductor memory device according to claim 7, wherein said annular floating gate electrode covers at least a part of an upper surface of said control gate electrode and an inner surface of an opening. 10. The nonvolatile semiconductor memory device according to claim 7, wherein said annular floating gate electrode is a sidewall provided on an inner side surface of said control gate electrode opening. 11. A third gate insulating layer formed on an upper surface of the semiconductor substrate so as to cover a boundary between the annular channel region and the source region, wherein the third gate insulating layer insulates the semiconductor substrate from the control gate electrode. 8. The nonvolatile semiconductor memory device according to claim 7, further comprising a third gate insulating layer for separating, wherein said control gate electrode is opposed to said boundary via said third gate insulating layer. . 12. The nonvolatile semiconductor memory device according to claim 7, wherein an element isolation region for isolating said memory cell is not provided in said memory cell array region. 13. An insulating film is provided between a portion of each of the plurality of word lines other than the control gate electrode and the semiconductor substrate, wherein the insulating film is formed of a material other than the third gate insulating layer. The nonvolatile semiconductor memory device according to claim 11, wherein the thickness is also large. 14. A step of forming a second conductivity type diffusion layer to be a source region on an upper surface of a first conductivity type semiconductor substrate, and forming a first insulating layer to be a third gate insulating layer on the semiconductor substrate. Forming a first conductive film to be a control gate electrode on the first insulating layer; and patterning the first conductive film and the first insulating layer, thereby forming an outer shape of the control gate electrode. obtaining a, so as to cover the first conductive film which is the patterning, depositing a second insulating layer on the semiconductor substrate, the first conductive film and the first and second insulating layer which is the patterned Forming an opening in the semiconductor substrate, thereby exposing a part of the semiconductor substrate, and forming the third gate insulating layer from the first insulating layer; and forming the third gate insulating layer through the opening in the semiconductor substrate. In the exposed part,
Forming a first conductivity type diffusion layer serving as a channel region, a step of the first gate insulating layer formed on the semiconductor substrate in the opening, forming a second gate insulating layer on the first over the conductive film Forming an annular floating gate electrode on the first gate insulating layer; and implanting a second conductivity type impurity into a part of the first conductivity type diffusion layer serving as the channel region through an opening of the floating gate electrode. Doping, thereby forming a second conductivity type diffusion layer that becomes a drain region, thereby manufacturing a nonvolatile semiconductor memory device. 15. The step of forming the annular floating gate electrode comprises: depositing a second conductive film to be the annular floating gate electrode on the semiconductor substrate; and forming the second conductive film by an anisotropic etching method. by etching back said to leaving a portion of the second conductive film on the first inner wall surface of the opening of the conductive film, thereby encompasses forming an annular floating gate electrode, A method for manufacturing a nonvolatile semiconductor memory device according to claim 14. 16. The method according to claim 14, further comprising the step of forming a sidewall insulating layer on an inner side surface of said annular floating gate electrode after forming said second conductivity type diffusion layer to be a drain region.
3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 17. The method according to claim 14, wherein the first gate insulating layer and the second gate insulating layer are simultaneously formed. 18. A step of forming a first conductivity type diffusion layer to be a channel region on an upper surface of a first conductivity type semiconductor substrate, and forming a first insulating layer to be a first gate insulating layer on the semiconductor substrate. Depositing a first conductive film to be a floating gate electrode on the first insulating layer; patterning the first conductive film and the first insulating layer, thereby forming an outer shape of the floating gate electrode And forming a second gate insulating layer on the patterned first conductive film , forming a third gate insulating layer on the semiconductor substrate, and covering the patterned first conductive film . Depositing a second conductive layer on the semiconductor substrate, covering the patterned first conductive film , and depositing a second insulating layer on the semiconductor substrate so as to cover the patterned first conductive film . layer, the second conductive layer, the first conductive film and the 1
Patterning an insulating layer, thereby obtaining an annular floating gate electrode having an opening and a control gate electrode; and doping a second conductivity type impurity into the semiconductor substrate using the control gate electrode as a mask, A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a source region and a drain region. 19. The method according to claim 19, further comprising, after the step of forming the source region and the drain region, a step of forming a sidewall insulating layer on an inner surface of an opening of the annular floating gate electrode and the control gate electrode. A method for manufacturing the nonvolatile semiconductor memory device according to claim 18. 20. The method according to claim 18, wherein said second gate insulating layer and said third gate insulating layer are simultaneously formed.