JPH09306960A - Evaluating adhesion of resist to semiconductor substrate and manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and correctly evaluate the adhesion of a resist by measuring electric characteristics of elements with use of an isolated pattern of the resist to evaluate the adhesion thereof to a semiconductor substrate. SOLUTION: Poor adhesion of a resist to a semiconductor substrate 1 will result in peeling of an isolated fine resist pattern 3 when this pattern is formed. If this pattern 3 peels, ions will are implanted into the entire surface of the substrate. If e.g. As is implanted into the substrate's entire surface, a evaluating electrode forms no diode, resulting in that only characteristics of a resistor come out when the electric characteristics are measured. This indicates the resist peels. Thus it is possible to easily and correctly evaluate the adhesion of the resist to the board 1 and correctly evaluate the adhesive if the pattern is fine.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating the adhesion between a semiconductor substrate and a resist and a method for manufacturing a semiconductor device using the evaluation method. The present invention, when a resist is directly or indirectly formed on the semiconductor substrate to form a resist pattern and the resist pattern is used,
It can be used universally.

[0002]

2. Description of the Related Art It has been adopted in the field of various semiconductor devices to form a resist pattern on a semiconductor substrate and perform various processes using the resist pattern.
In this case, it is general that the photoresist on the semiconductor substrate is exposed to light in a desired pattern and developed to obtain a desired resist pattern.

Thus, when a desired resist pattern is formed on a semiconductor substrate using a photoresist, if the resist and the lower part of the resist are not closely adhered to each other, the resist is peeled off during or after the formation of the resist pattern. The intended semiconductor device cannot be manufactured correctly.

As a method for evaluating the adhesiveness between a semiconductor substrate and a resist, conventionally, a pattern that is easily peeled off is formed on a semiconductor substrate, and the substrate is visually observed with the naked eye or a microscope to confirm whether the adhesiveness is good or bad. I was going to do it. However, with the miniaturization and high integration of the semiconductor device, the miniaturization of the pattern is progressing remarkably, and proper judgment by visual observation is becoming difficult. Further, even with respect to the same type of semiconductor substrate, the adhesiveness varies depending on the type of the resist composition. However, it is not possible to detect such a difference in the adhesiveness with respect to the same semiconductor substrate depending on the type of the resist composition. It was difficult. On the contrary, although the same resist composition has different adhesiveness depending on the type of the semiconductor substrate and the surface state of the semiconductor substrate, it is extremely difficult to detect the difference in the adhesiveness with the conventional technique. In any case, it was difficult to quantitatively evaluate the adhesion with the conventional technology.

[0005]

As described above, in the prior art, it is difficult to make a judgment by visual observation due to the miniaturization of the pattern, and in the prior art, the surface condition of the semiconductor substrate and the resist are difficult to judge. It is extremely difficult to detect the difference in adhesion due to the difference in species. Moreover, it is extremely difficult to quantitatively evaluate the adhesiveness in the conventional technique.

The present invention solves the above-mentioned problems of the prior art, and when the resist is directly or indirectly formed on the semiconductor substrate, the adhesion of the resist on the semiconductor substrate can be easily and properly evaluated. It is possible to easily and correctly evaluate even if the pattern is miniaturized, and it is also possible to easily and appropriately detect the difference in adhesion due to the difference in the type of the resist, the type of the semiconductor substrate, the surface state, etc. An object of the present invention is to provide a method for evaluating the adhesion between a semiconductor substrate and a resist, which enables quantitative evaluation of the adhesion, and a method for manufacturing a semiconductor device using the evaluation method.

[0007]

A method for evaluating the adhesion between a semiconductor substrate and a resist according to the present invention is applied to a semiconductor substrate when a resist pattern is formed by directly or indirectly forming a resist on the semiconductor substrate. Is a method of evaluating the adhesion between a semiconductor substrate and a resist by forming an element using an isolated pattern of the resist and measuring the electrical characteristics of the element. It is characterized by evaluation. In the present specification, the “isolated pattern of resist” is a pattern that is independent of other resist patterns, and a pattern in which an element formed using this isolated pattern exhibits independent electrical characteristics. Say

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a resist directly or indirectly on a semiconductor substrate to form a resist pattern, and processing using the resist pattern. Method,
An element using an isolated pattern of a resist is formed, and the electrical characteristics of the element are measured to evaluate the adhesion between the semiconductor substrate and the resist formed on the semiconductor substrate. It is a thing.

According to the method for evaluating the adhesiveness between the semiconductor substrate and the resist according to the present invention, an element using an isolated pattern of the resist is formed and the electrical characteristics of the element are measured. If so, the device exhibits appropriate electrical characteristics. If the device does not show proper electrical characteristics,
It can be seen that the adhesion of the resist is poor. Thereby, the adhesiveness between the semiconductor substrate and the resist can be evaluated. Since this evaluation is based on the electrical characteristics, unlike the case of visual inspection, there is no oversight, and an easy and reliable evaluation is possible. Quantitative evaluation is also possible, and it is easy to devise various ways to measure the electrical characteristics of the device.Therefore, the difference in adhesion due to the difference in resist type, semiconductor substrate type, surface condition, etc. It is also easy to configure to detect. As the evaluation element, various elements such as a diode, a conductive material (resistor), a capacitance element, and a transistor can be arbitrarily adopted as appropriate according to the situation.

According to the method of manufacturing a semiconductor device of the present invention, the semiconductor device can be manufactured based on the evaluation of the adhesion between the semiconductor substrate and the resist according to the above-described evaluation method, so that the processing with the proper resist can be realized. Therefore, a high-quality semiconductor device with high reliability can be obtained by an appropriate process.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in more detail below, and specific examples of preferred embodiments of the present invention will be described with reference to the drawings. However, needless to say, the present invention is not limited to the illustrated embodiment.

In the present invention, an element using an isolated pattern of a resist is formed, and the electrical characteristics of the element are measured to evaluate the adhesion between the semiconductor substrate and the resist formed on the semiconductor substrate. The configuration. In this case, as an isolated pattern of the resist for evaluating the adhesion between the resist and the semiconductor substrate, a plurality of elements are formed by using a plurality of patterns having mutually different dimensions, and the electrical characteristics of the plurality of elements are measured. Aspect can be adopted.

Further, it is possible to adopt a mode in which a plurality of elements are formed by using a plurality of patterns as isolated patterns of the resist, the plurality of elements are electrically connected in parallel, and the electrical characteristics thereof are measured.

Specific examples of the embodiments of the present invention will be described in detail below. It should be noted that the specific description below shows a case where the present invention is applied in the manufacture of a silicon semiconductor device, but is not limited to this, of course,
It is applicable in the field of various other semiconductor devices.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS. 1 and 2. In this embodiment, the adhesiveness between the semiconductor substrate and the resist formed on the semiconductor substrate is improved by forming an element using an isolated pattern of the resist on the semiconductor substrate.
A method of evaluating by examining the electrical characteristics will be described in an example of forming and evaluating a diode as an example of a production flow of the evaluation element.

In this example, as the semiconductor substrate, for example, as shown in FIG. 1A, a silicon semiconductor substrate 1 of the first conductivity type (for example, N type here) having a resistivity of 1 Ω · cm is used. A resist pattern 2 is formed on this semiconductor substrate 1. The formation of the resist pattern can be performed by using a general method of forming a photoresist, exposing, and developing.

Next, the second conductivity type (here, P type) impurities are ion-implanted by using an ion implantation device. For example, boron at a concentration of 1E15 / cm ² and 50 ke
Ion implantation is performed under V acceleration conditions. Ion implantation at this stage is schematically indicated by reference numeral I in FIG. An impurity introduction part formed by ion-implanting the second conductivity type impurity;
In the figure, reference numeral 41 is used.

Next, after removing the resist pattern 2,
As shown in FIG. 1B, an isolated resist pattern 3 is formed.
To form This is the resist pattern 3 for evaluation of adhesion. Therefore, the resist pattern 3 is formed using a resist composition whose adhesiveness is to be evaluated. In this example, as the adhesiveness evaluation resist pattern 3, an isolated pattern of about 10 μm square (10 μm × 10 μm) was formed.

With the adhesiveness evaluation resist pattern 3 formed, first conductivity type (here, N type) impurities are ion-implanted. Here, for example, arsenic is added to 5E15.
Ion implantation is performed at a concentration of / cm ² under an acceleration condition of 50 keV. Ion implantation at this stage is schematically indicated by reference numeral II in FIG. An impurity introduction portion formed by ion-implanting the first conductivity type impurity is indicated by reference numeral 42 in the drawing.

After removing the resist pattern 3, heat treatment (for example, heat treatment at 1000 ° C., about 30) is performed to activate the ion-implanted impurities.

Next, an insulating film 5 is formed as shown in FIG. 2 (as an insulating material, an appropriate material such as silicon oxide or nitride may be used), and the electrode lead-out portions 61 and 62 are further formed. By forming and forming the wirings 71 and 72 of metal or the like, an element structure capable of evaluating the electrical characteristics of the diode formed as the evaluation element is completed.

In the process flow described above, FIG.
If the adhesiveness between the semiconductor substrate 1 and the resist is poor during the formation of the resist pattern 3 shown in 1), the isolated resist pattern 3 which is a fine pattern is peeled off. When the resist pattern 3 is peeled off, ion implantation is performed on the entire surface of the substrate. In the case of this example, arsenic is implanted over the entire surface of the substrate. When arsenic is implanted over the entire surface, no diode is formed. Therefore, when the electrical characteristics are measured in the state of FIG. 2, only the characteristics as a resistor appear. This shows that the resist was peeled off. In this way, it is possible to confirm whether or not the resist has peeled off, and thus the adhesiveness of the resist on the semiconductor substrate 1 can be easily and reliably evaluated.

According to this example, the adhesion between the semiconductor substrate and the resist can be evaluated by measuring the electrical characteristics, and not the visual judgment, so that the adhesion can be surely evaluated without oversight.

Further, it is possible to evaluate the resist peeling which cannot be visually discerned. Therefore, even if the resist pattern is miniaturized, reliable evaluation can be easily achieved.

Embodiment 2 In Embodiment 1 described above, one type of resist pattern 3 for evaluation was formed, but in this example, a plurality of isolated patterns having different dimensions are formed by the resist to be evaluated. These were used as evaluation resist patterns. By doing so, a plurality of elements corresponding to the resist pattern having the changed dimensions are formed for adhesion evaluation.

In this example, since the electrical characteristics of each of the plurality of elements having the dimensions changed as described above are examined, it is possible to know which dimension of the element is not properly formed. . This indicates which size of resist has peeled off. Therefore, it is possible to easily know the difference in adhesiveness depending on the size of the resist.

This example can be preferably used when evaluating the adhesiveness between a plurality of types of semiconductor substrates and resists.
That is, since it is possible to detect which size of the resist is peeled off from each semiconductor substrate, it is possible to confirm the difference in the adhesiveness of the resist to be evaluated for each semiconductor substrate by comparing the maximum peeled size.

On the contrary, this example can be preferably used when evaluating the difference in adhesion between a specific type of semiconductor substrate and various resists. That is, with respect to a semiconductor substrate, a plurality of evaluation patterns having different dimensions are formed from the first resist composition to evaluate the adhesion, and a plurality of evaluation patterns are similarly formed using the second and third resist compositions. By forming the evaluation pattern and performing the same evaluation, it is possible to know the adhesion of each resist to the semiconductor substrate. That is, by comparing the peeled maximum dimensions of the respective resists, the difference in the adhesiveness of the respective resists of the semiconductor substrate can be confirmed.

According to the present example, similar to the first embodiment, it is possible to realize a reliable adhesion evaluation without oversight, and it is possible to evaluate the resist peeling which cannot be visually discriminated. Even if the resist pattern is miniaturized, Certain evaluation can be easily achieved. Furthermore, in this example, in addition to this, the adhesiveness between a plurality of semiconductor substrates and a resist, or the adhesiveness between a certain semiconductor substrate and a plurality of resists can be evaluated with a reduced number of steps, without requiring special man-hours. As a result, the difference in the adhesiveness between the semiconductor substrates and the resist (the difference in the adhesiveness between the semiconductor substrates and the resist) can be easily known. Moreover, it becomes possible to quantitatively evaluate these by knowing the maximum peeled dimension.

Third Embodiment In the third embodiment, as shown in the circuit diagram of FIG.
A resist pattern was used to obtain an element structure in which a plurality of evaluation elements (here, diodes as in each of the examples) can be connected in parallel.

According to this example, even if the probability of resist peeling is low, the diode D1, as shown in the circuit diagram of FIG.
Since a plurality of D2 ... Are connected in parallel and the electrical characteristics are examined, if there is a diode that is not formed normally even at one place, it can be determined by measuring the electrical characteristics.
In order to obtain an element structure in which a plurality of diodes D1, D2 ... Are connected in parallel in this way, it is only necessary to form an isolated resist pattern so that a plurality of the diodes described in the first embodiment are formed. Good and easy.

If a plurality of patterns in which a plurality of elements are electrically connected are formed on the semiconductor substrate as in this example, it is possible to determine the peeling of the resist by the occurrence rate. At the same time, by forming a plurality of the element pattern groups on the entire surface of the semiconductor substrate, it becomes possible to evaluate the peeling of the resist (adhesion between the semiconductor substrate and the resist) on the entire surface of the semiconductor substrate.

According to this example, in addition to the same effects as those of the above-described respective embodiments, proper evaluation can be realized even when the resist peeling probability is low, and the resist peeling is determined by the occurrence rate. Quantitative evaluation becomes possible, and evaluation on the entire surface of the semiconductor substrate becomes possible.

Embodiment 4 In each of the embodiments described above, the case where a diode is formed as an element has been described, but of course the evaluation element is not limited to a diode, and any element can be formed as long as it can be evaluated. But it's okay. In this example, as shown in FIG. 4, isolated patterns 81, 82 ... Of conductive material were used as the evaluation elements. The conductive material patterns 81, 82, ... Are, for example, 10 μm square (10 μm ×
An isolated resist pattern of about 10 μm) was formed, and this was used. In FIG. 4, reference numeral 1 is a semiconductor substrate, and the same silicon semiconductor substrate as in the first embodiment is used here. Reference numeral 51 is an insulating film (the insulating material is an appropriate material such as silicon oxide or nitride), and 71.72 ... Wirings made of metal or the like.
R1 of the circuit diagram corresponding to the above cross-sectional view of the device structure
R2 ... Represents the resistance formed by the conductive material patterns 81, 82.

In the present example, the isolated pattern of the conductive material formed as described above is used as an evaluation element, and wiring for connecting this in series is formed to examine the characteristics. When the resist peels off, the conductive material is partially missing, resulting in no conduction. As a result, it becomes possible to easily and surely detect the presence or absence of the resist peeling. Therefore, by this, the adhesiveness of the resist can be evaluated by measuring the electrical characteristics.

By adopting the method of this example instead of using the diode as the evaluation element, the same effect as each of the above examples can be obtained.

Embodiment 5 In this embodiment, a capacitance element, especially a MIS capacitance element, is used as an evaluation element. The evaluation element in this example has the configuration shown in FIG. 5 as a single element. As shown in FIG. 5, an insulating film A indicated by reference numeral 5a was formed on the semiconductor substrate 1, and this was used as a dielectric material (dielectric material for forming a capacitor). On top of that, the wiring 7 made of a conductive material is provided.
Here, a metal wiring is formed as a. Thus, the MIS capacitor element structure of the wiring 7a (metal wiring) -insulating film A (dielectric 5a) -semiconductor substrate 1 (here, silicon substrate) was formed.

In such a MIS capacitor element structure,
By using an isolated pattern as the resist for patterning the insulating film A (dielectric 5a), the presence or absence of resist peeling can be determined.
This can be confirmed by conducting a continuity check of the capacitance of the MIS structure.

That is, when the resist is peeled off, the insulating film A is etched and does not remain.
Therefore, in such a case, the wiring 7a (metal wiring) and the semiconductor substrate 1 (silicon substrate) are short-circuited. This makes it possible to evaluate the presence or absence of resist peeling.

When the above MIS capacitive element structure is formed of a plurality of capacitive element structures C1, C2, ... As shown in FIG. 6 and connected in parallel, the above detection can be performed with higher sensitivity.

In FIG. 5, reference numeral 5b indicates another insulating film, and reference numeral 7b indicates another wiring (metal wiring). Code 42
Is the N ⁺ region.

Sixth Embodiment Referring to FIG. As illustrated in FIG. 7, the semiconductor substrate 1
A plurality of transistors Tr (for example, a silicon substrate)
When 1 and Tr2 are arranged, the isolated pattern of the resist is used also when the isolation region 10 for isolating each individual transistor from each other is formed. In this embodiment, the present invention is applied in a mode that utilizes such an isolated pattern of resist.

As illustrated in FIG. 7, when two independent transistors Tr1 and Tr2 are arranged, for example, as shown in the figure, a resist pattern 2a shown in FIG. 8 is formed and a portion not masked by the resist pattern 2a. Isolation region 10 for electrical isolation is formed by, for example, implanting impurity II. The resist pattern 2a is an isolated resist pattern for evaluation in the present embodiment. Here, if the resist is peeled off, impurities are injected into the entire surface, and the transistor structure is not formed correctly. Therefore, the presence or absence of resist peeling can be evaluated by examining the characteristics of the transistor.

[0044]

According to the method of evaluating the adhesion between the semiconductor substrate and the resist of the present invention, and the method of manufacturing a semiconductor device using the evaluation method, the case where the resist is formed directly or indirectly on the semiconductor substrate The adhesiveness of the resist on the semiconductor substrate can be easily and properly evaluated, and the adhesiveness can be easily and correctly evaluated even if the pattern is miniaturized, and the type of the resist, the type of the semiconductor substrate, the surface condition, etc. There is an effect that it is possible to easily and properly detect the difference in the adhesiveness due to the difference, and it is also possible to quantitatively evaluate the adhesiveness.

[Brief description of drawings]

FIG. 1 is a sectional view showing a step of the first embodiment of the present invention (1).

FIG. 2 is a sectional view showing a step of the first embodiment of the present invention (2), and is a completed view of the evaluation element of the example.

FIG. 3 is a diagram showing an evaluation connection structure according to a third embodiment.

FIG. 4 is a diagram showing an evaluation connection structure according to a fourth embodiment.

FIG. 5 is a diagram showing an evaluation structure according to a fifth embodiment.

FIG. 6 is a diagram showing an evaluation method according to a fifth embodiment.

FIG. 7 is a diagram showing an evaluation structure according to a sixth embodiment.

FIG. 8 is a diagram showing an evaluation method according to a sixth embodiment.

[Explanation of symbols]

1 ... Semiconductor substrate (silicon semiconductor substrate), 2 ...
Resist pattern, 3, 2a ... Isolated resist pattern (evaluation pattern), 41, 42 ... Impurity introduction part, 5, 51 ... Insulating film, 61, 62 ... Electrode extraction part, 71 ... 74 ... Wiring, 81-83 ...
Conductive material pattern (forming evaluation element), 91, 92
..Element regions, 10 ... Separation regions D1, D2 ...
A diode (forming an evaluation element). Tr1, Tr2 ...
-Transistor (forming evaluation element). 5a ... (Insulating film (dielectric material)) forming the MIS structure (forming an evaluation element). 7a ... Conductive material (wiring) forming the MIS structure (which constitutes an evaluation element).

Claims (7)

[Claims] 1. A method for evaluating adhesion, which comprises directly or indirectly forming a resist on a semiconductor substrate to form a resist pattern and evaluating the adhesion between the semiconductor substrate and the resist. A method for evaluating the adhesion between a semiconductor substrate and a resist, which comprises evaluating an adhesion between the semiconductor substrate and the resist by forming an element using a pattern and measuring the electrical characteristics of the element. 2. The method according to claim 1, wherein a plurality of elements are formed by using a plurality of patterns having different dimensions as the isolated pattern of the resist, and the electrical characteristics of the plurality of elements are measured. The method for evaluating the adhesion between the semiconductor substrate and the resist according to 1. 3. The device according to claim 1, wherein a plurality of elements are formed by using a plurality of patterns as isolated patterns of the resist.
The method for evaluating the adhesiveness between a semiconductor substrate and a resist according to claim 1, wherein the plurality of elements are electrically connected in parallel and the electrical characteristics thereof are measured. 4. The plurality of same or different semiconductor substrates according to claim 1, wherein a plurality of isolated patterns are formed on each semiconductor substrate by a plurality of same or different resists, and a plurality of elements are formed by using the isolated patterns. Then, the electrical property of the device is measured, and the method for evaluating the adhesion between the semiconductor substrate and the resist according to claim 1. 5. A method of manufacturing a semiconductor device, comprising the steps of directly or indirectly forming a resist on a semiconductor substrate, forming a resist pattern, and processing using the resist pattern, wherein the resist pattern is an isolated pattern. A semiconductor device characterized by being configured to evaluate the adhesion between a semiconductor substrate and a resist formed on the semiconductor substrate by forming an element using Method. 6. The structure according to claim 5, wherein a plurality of elements are formed by using a plurality of patterns having mutually different dimensions as isolated patterns of the resist, and electrical characteristics of the plurality of elements are measured and evaluated. The method for manufacturing a semiconductor device according to claim 5, wherein 7. The device according to claim 5, wherein a plurality of elements are formed by using a plurality of patterns as isolated patterns of the resist.
The method for manufacturing a semiconductor device according to claim 5, wherein the plurality of elements are electrically connected in parallel, and the electrical characteristics are measured and evaluated.