JP3179938B2 - Semiconductor protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor protection circuit having a circuit to be separated from another circuit by blowing a fuse.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a circuit used in a test process such as burn-in is electrically separated from an input terminal after the test process. The input end of the circuit to be separated is connected to an external input terminal by a fuse formed of polysilicon or the like, and the separation is performed by cutting the fuse.
As a method for cutting a fuse, cutting by applying a voltage (current) to a fuse portion is used.

FIG. 10 shows an example of a semiconductor device used for a method of blowing a fuse by applying a voltage (current). A fuse 302 is connected in series between the input terminal 301 and the circuit to be separated 304, and one end of an input protection element 305 for suppressing an excessive voltage is connected to a connection point between the input terminal 301 and the fuse 302. The other end of the input protection element 305 is connected to the ground. The connection point between the fuse 302 and the circuit to be separated 304 is connected to the emitter of the fuse cutting transistor 303, and the collector is connected to ground.

Then, the breakdown voltage of the input protection element 305 is set to V3, the breakdown voltage of the fuse cutting transistor 303 is set to V4, and V3> V4 is set. When the fuse is cut, only the fuse cutting transistor 303 breaks down by applying an applied voltage V5 (V3>V5> V4) to the input terminal 301.
A current path is formed from the input terminal 301 to the ground via the fuse 302 and the fuse cutting transistor 303.
The current blows the fuse. Thus, even after packaging, it is possible to intentionally apply a voltage (current) to the fuse 302 and cut it.

[0005]

However, the input terminal 1
When an accidental high voltage (surge voltage) V1 (V1 ≥ V3) is instantaneously applied to 01, both the input protection element 105 and the fuse cutting transistor 103 break down, and the fuse 102 is cut. I will.

In view of the above problems, in the present invention, disconnection of a circuit to be separated by fuse cutting is performed after packaging without being affected by accidental high voltage such as static electricity.
It is an object of the present invention to provide a semiconductor protection circuit capable of performing the operation accurately.

[0007]

In order to achieve the above object, a semiconductor protection circuit according to the present invention comprises an input terminal, a circuit to be separated, and a fuse connected between the input terminal and the circuit to be separated. An input protection element connected to a connection point between the input terminal and the fuse; a fuse cutting transistor connected to a connection point between the fuse and the circuit to be separated; and an input protection element connected to the input terminal and the fuse. Connection, a capacitance element connected between the input terminal and the connection between the base terminal of the fuse cutting transistor, and a resistance element connected to a connection point between the capacitance element and the base terminal of the fuse cutting transistor. It is characterized by having.

[0008]

According to the present invention, the breakdown voltage V1 of the input protection element and the breakdown voltage V2 of the fuse cutting transistor are adjusted so as to satisfy the relationship of V1> V2. Because of the connection, electrostatic breakdown (ESD) occurs, and if an accidental high voltage is applied, the breakdown of the fuse-cutting transistor is delayed, and a current path is formed first in the input protection element. The fuse can be intentionally cut by the fuse cutting transistor, and erroneous cutting of the fuse due to electrostatic breakdown can be prevented.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. FIG.
FIG. 1 shows an example of a circuit of the semiconductor device of this embodiment. A fuse 102 is connected in series between the input terminal 101 and the circuit to be separated 104, and one end of an input protection element 105 for suppressing an excessive voltage is connected to a connection point between the input terminal 101 and the fuse 102. The other end of the input protection element 105 is connected to the ground. The connection point between the fuse 102 and the circuit to be separated 104 is connected to the emitter of the fuse cutting transistor 103, and the collector is connected to ground. The base input terminal of the fuse cutting transistor 103 is connected to the connection point of the capacitance element 106 and the resistance element 107 connected in series, and the other end of the capacitance element 106 is connected to the input terminal 101. Is grounded.

In such a circuit configuration, the breakdown voltage of the input protection element 105 is V1, the breakdown voltage of the fuse cutting transistor 103 is V2,
It is assumed that V1> V2. When the surge voltage is applied to the input terminal 101, the potential of the emitter of the fuse cutting transistor 103 rises and the potential of one electrode of the capacitor 106 also rises.

FIG. 3 is a table showing how the potential of the other electrode of the capacitor 106 changes when a high voltage V3 such as a surge voltage is applied to one electrode of the capacitor 106 for a short time. It is the graph which did. The potential of the other electrode is
Once the voltage rises to the surge voltage V3, it gradually falls over time. Since the other electrode is connected to the base of the fuse cutting transistor 103, the potential of the other electrode is equal to the base potential of the fuse cutting transistor 103. That is, it takes time for the potential difference between the emitter and the base to reach the breakdown voltage V2 of the fuse cutting transistor 103. If V3.gtoreq.V1, the input protection element 105 breaks down during that time, so that the fuse is not erroneously blown. The time t0 until the potential of the other electrode of the capacitor 106 becomes 0 (V) depends on the time constant T. The time constant T is expressed as T = RC if the resistance value of the resistance element 107 is R and the capacitance of the capacitance element 106 is C, and depends on R if C is constant. Therefore, by increasing R, the fuse cutting transistor 10
The time required for the potential difference between the base 3 and the emitter 3 to reach V2 becomes longer. When cutting the fuse, V1> V
By setting to 2, only the fuse cutting transistor 103 is started without activating the input protection element 105, and the fuse can be cut.

FIG. 2 shows the structure of the semiconductor device of the present invention which realizes the functions of the circuit of FIG. 2A is a top view of the semiconductor device of the present invention, and FIG. 2B is a cross-sectional view taken along a dotted line connecting A and A ′ in FIG. 2A.

As shown in FIG. 2A, a p-type first well region 202a for forming an input protection element and a p-type first well region for forming a fuse cutting transistor are formed in a surface region of an n-type semiconductor substrate 201. A two-well region 202b is formed.

In the first well region 202a, an n-type diffusion layer 203 serving as an emitter / collector region is formed on the surface of the semiconductor substrate 201 between the field oxide film patterns 210.
A p-type high concentration region 204 serving as a base electrode is formed.
A PSG film 209 is formed on the surface of the semiconductor substrate 201, and the PSG film 209 is formed on the n-type diffusion layer 203 and the p-type high concentration region 204.
A through hole is formed in the G film 209, and electrode wirings 220a and 220b are formed in the through hole of the n-type diffusion layer 203, and are connected to an input terminal and the ground, respectively.

In the second well region 202b, on the surface of the semiconductor substrate 201 between the field oxide film patterns 210, one of the capacitive elements is disposed via an emitter region 207, a collector region 208, a p-type high concentration region, and a silicon oxide film 211. An electrode 205a is formed. This electrode 205a has a U-shape as shown in FIG. 2A, and the second well region 20 between the emitter region 207 and the collector region 208 is formed.
The potential of 2b uniformly rises. A through hole is formed in the PSG film 209 on the emitter region 207, the collector region 208, the p-type high-concentration region, and the one electrode 205a of the capacitor, and the electrode wiring 220c is formed in the through hole on the one electrode 205a of the capacitor. However, in the through holes on the emitter region 207 and the collector region 208, the electrode wiring 220
The electrode wiring 220f is formed in each of the through holes on the p-type high concentration region. The electrode wiring 220c is connected to the connection point between the input terminal 101 and the fuse 102, the electrode wiring 220d is connected to the ground, the electrode wiring 220e is connected to the connection point between the fuse 102 and the circuit to be separated 104, and the electrode wiring 220f is connected to the resistance element 107, respectively.

Next, a method of manufacturing a device for separating a circuit to be separated according to a second embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 4, a p-type impurity such as boron is ion-implanted and diffused on an n-type semiconductor substrate 201, which is a semiconductor substrate of one conductivity type, so that an input protection element formation area and a fuse blow A p-type first well region 202a and a second well region 202b, which are regions of the opposite conductivity type, are formed in the region where the transistor is to be formed.

Next, as shown in FIG. 5, a field oxide film pattern 210 as an element isolation region is formed by a LOCOS process. After forming the field oxide film pattern 210, as shown in FIG. 6, a thin silicon oxide film 211, which is an insulating film, is formed on the exposed surface of the n-type semiconductor substrate 201 by the CVD method, and the field oxide film pattern 210 is formed. A polysilicon film 215 as a conductive film is formed to a thickness of about 0.5 μm on the surface of the silicon oxide film 211 including the silicon oxide film 211 by a CVD method.

After that, as shown in FIG. 7, the polysilicon film 215 is patterned by a lithography process.
One electrode 205a of the capacitor 106 is formed in a U-shape.

After the formation of the one electrode 205a, as shown in FIG. 8, the first well region 202a and the second well region 202
An emitter region 207 and a collector region 208 of the fuse cutting transistor 103 and an n-type diffusion layer 203 of the input protection element 105 are formed by ion-implanting and diffusing an n-type impurity such as phosphorus, which is one conductivity type impurity, into b. I do.

Further, as shown in FIG. 9, a p-type impurity such as boron is ion-implanted into a portion of the exposed surface of the p-well region 202 where the surface is not n-type, and is diffused. A high concentration region 204 of the mold is formed.

After the formation of the p-type high concentration region 204, as shown in FIG. 2, a PSG (Phospho-Silicate Glass) film 20 as an interlayer film is formed on the surface of the n-type semiconductor substrate 201 by the CVD method.
9 is formed and the surface is flattened by reflow. After reflow, a contact hole for wiring is opened. After forming the contact hole, an aluminum layer for wiring is formed so as to fill the contact hole, and the aluminum layer for wiring is patterned by lithography to form an electrode wiring 220.

In the above embodiment, a bipolar transistor is used for both the input protection element and the fuse cutting transistor. However, a MOS transistor may be used as long as the transistor operates in a bipolar operation region.

[0023]

According to the present invention, erroneous cutting of a fuse due to accidental application of a high voltage can be prevented, and the fuse can be intentionally cut by applying a voltage from an input terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a top view and a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a graph showing a temporal change in the potential of the other electrode of the capacitor.

FIG. 4 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 7 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 8 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 9 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention;

FIG. 10 is a circuit diagram of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 input terminal 102 fuse 103 fuse cutting transistor 104 circuit to be separated 105 input protection element 106 capacitance element 107 resistance element 201 semiconductor substrate 202 p-well region 202a first well region 202b second well region 203 n-type diffusion layer 204 p-type High-concentration region 205a One electrode of the capacitor element 205b The other electrode of the capacitor element 207 Emitter region 208 Collector region 209 PSG film 210 Field oxide film pattern 211 Silicon oxide film 215 Polysilicon film 220 Electrode wiring

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 21/8234-21/8238 H01L 27/04 H01L 27/08-27 / 092

Claims (2)

(57) [Claims] An input terminal; a circuit to be separated; a fuse connected between the input terminal and the circuit to be separated; an input protection terminal connected to a connection point between the input terminal and the fuse; A fuse disconnecting transistor connected to a connection point between the fuse and the circuit to be separated; a capacitor connected between a connection point between the input terminal and the fuse; and a control terminal of the fuse cutting transistor. A semiconductor protection circuit comprising: an element; and a resistance element having one end connected to a connection point between the capacitance element and a control terminal of the fuse cutting transistor. 2. The breakdown voltage of the input protection element is
V1 and the breakdown voltage of the fuse cutting transistor
Is set to V2 which is less than V1.
2. The semiconductor protection circuit according to claim 1, wherein: