JP3398077B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3398077B2 JP3398077B2 JP36583998A JP36583998A JP3398077B2 JP 3398077 B2 JP3398077 B2 JP 3398077B2 JP 36583998 A JP36583998 A JP 36583998A JP 36583998 A JP36583998 A JP 36583998A JP 3398077 B2 JP3398077 B2 JP 3398077B2
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- Prior art keywords
- concentration
- type semiconductor
- semiconductor region
- low
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＩＳ型半導体装
置のゲート酸化膜を過大電圧から保護するための静電保
護装置と、その製造方法に関するものであり、特にＣＭ
ＯＳプロセス等で作製する場合に、静電保護のために半
導体基板上に形成されるサイリスタの特性改善を目的と
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection device for protecting a gate oxide film of a MIS type semiconductor device from an excessive voltage and a manufacturing method thereof, and particularly to a CM.
It is intended to improve the characteristics of a thyristor formed on a semiconductor substrate for electrostatic protection when it is manufactured by an OS process or the like.
【０００２】[0002]
【従来の技術】半導体装置は年々微細化されており、そ
れに伴い、外部からの望まない静電破壊（Ｅｌｅｃｔｒ
ｏ Ｓｔａｔｉｃ Ｄｉｓｃｈａｒｇｅｓ：ＥＳＤ）に
対する、保護装置を半導体回路の入出力部に組み込むの
が、一般的になっている。また、それらの保護装置の特
性も、保護すべき対象となる半導体装置の微細化に応じ
た、適切な特性を必要とされている。2. Description of the Related Art Semiconductor devices have been miniaturized year by year, and along with this, unwanted electrostatic breakdown from outside (Electr).
For static discharges (ESD), it is general to incorporate a protection device in the input / output section of a semiconductor circuit. Further, the characteristics of these protection devices are also required to have appropriate characteristics according to the miniaturization of the semiconductor device to be protected.
【０００３】これら保護装置として、ＭＯＳ型半導体装
置のプロセスにおいては、サイリスタとよばれる半導体
装置がよく用いられる。サイリスタはＰＮ接合を２つ以
上含む半導体装置で、典型的には、Ｐ−Ｎ−Ｐ−Ｎの構
造をもち、一方の端部となるＰ型半導体をアノード、も
う一方の端部のＮ型半導体をカソードと呼んでいる。こ
のようなサイリスタにおける従来構造と製造方法を、Ｐ
型シリコン基板に作製する場合を例にとり、図１１の
（ａ）から（ｆ）に従って説明する。As these protection devices, a semiconductor device called a thyristor is often used in the process of MOS type semiconductor device. A thyristor is a semiconductor device including two or more PN junctions, and typically has a P-N-P-N structure, in which a P-type semiconductor at one end is an anode and an N-type at the other end. The semiconductor is called the cathode. The conventional structure and manufacturing method of such a thyristor are described in
Taking as an example a case where it is formed on a mold silicon substrate, description will be given according to (a) to (f) of FIG.
【０００４】まず、図１１（ａ）に示すように、Ｐ型シ
リコン基板１に、基板面にフォトレジストを塗布し、素
子分離領域を形成する部分のレジストを取り除き、シリ
コン基板をエッチング後、酸化物埋め込みを行い、その
後、化学的機械的研磨（ＣＭＰ）を実施し、素子分離領
域２を形成する。First, as shown in FIG. 11 (a), a photoresist is applied to the surface of a P-type silicon substrate 1 to remove the resist in a portion forming an element isolation region, and the silicon substrate is etched and then oxidized. After embedding a material, chemical mechanical polishing (CMP) is performed to form the element isolation region 2.
【０００５】次に、図１１（ｂ）に示すように、フォト
レジストを塗布し、低濃度Ｎ型半導体領域を形成する部
分のレジストを除去し、Ｎ型不純物を低濃度にイオン注
入して低濃度Ｎ型半導体領域４を形成する。その後、再
度フォトレジストを塗布し、低濃度Ｐ型半導体領域を形
成する部分のレジストを除去しした後、Ｐ型不純物を低
濃度にイオン注入し、低濃度Ｐ型半導体領域３を形成す
る。Next, as shown in FIG. 11B, a photoresist is applied, the resist in the portion forming the low-concentration N-type semiconductor region is removed, and N-type impurities are ion-implanted at a low concentration to reduce the concentration. A concentration N-type semiconductor region 4 is formed. Then, the photoresist is applied again to remove the resist in the portion forming the low-concentration P-type semiconductor region, and then P-type impurities are ion-implanted at a low concentration to form the low-concentration P-type semiconductor region 3.
【０００６】続いて、図１１（ｃ）に示すように、フォ
トレジスト５を塗布し、低濃度Ｎ型半導体領域上の一部
と、低濃度Ｐ型半導体領域上の一部を開口し、Ｐ型不純
物を基板表面に対して、ほぼ垂直方向から、高濃度にイ
オン注入を行い、高濃度Ｐ型半導体領域６、７を形成す
る。Subsequently, as shown in FIG. 11C, a photoresist 5 is applied, and a part of the low concentration N type semiconductor region and a part of the low concentration P type semiconductor region are opened to form P. High-concentration ion implantation of type impurities is performed from the direction substantially perpendicular to the substrate surface to form high-concentration P-type semiconductor regions 6 and 7.
【０００７】次に、図１１（ｄ）に示すように、レジス
トを除去後、再びフォトレジスト８を塗布し、低濃度Ｎ
型半導体領域上の一部と、低濃度Ｐ型半導体領域上の一
部を開口し、Ｎ型不純物を基板表面に対して、ほぼ垂直
方向から、高濃度にイオン注入を行い、高濃度Ｎ型半導
体領域９、１０を形成する。Next, as shown in FIG. 11 (d), after removing the resist, a photoresist 8 is applied again, and a low concentration N
A portion of the high-concentration N-type semiconductor region and a portion of the low-concentration P-type semiconductor region are opened, and N-type impurities are ion-implanted at a high concentration from a direction substantially perpendicular to the substrate surface. The semiconductor regions 9 and 10 are formed.
【０００８】次に、図１１（ｅ）に示すように、熱処理
により、図１１（ｃ）及び（ｄ）で示す工程で注入した
不純物を活性化する。その後、図１１（ｆ）に示すよう
に、高濃度Ｎ型半導体領域と高濃度Ｐ型半導体領域の各
領域に、コンタクトを形成し、金属配線１１、１２、１
３等で、電源、グラウンド、もしくは入出力端子のいず
れかに、電気的に接続する。Next, as shown in FIG. 11E, heat treatment activates the impurities implanted in the steps shown in FIGS. 11C and 11D. Thereafter, as shown in FIG. 11F, contacts are formed in the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and the metal wirings 11, 12, 1 are formed.
3 or the like to electrically connect to either the power supply, the ground, or the input / output terminal.
【０００９】以上のような工程により作製された従来技
術の構造では、基板に低濃度Ｎ型半導体領域、及び、低
濃度Ｐ型半導体領域が形成されており、低濃度Ｎ型半導
体領域と低濃度Ｐ型半導体領域は接しており、かつ、低
濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域１０
と、アノード部を形成する高濃度Ｐ型半導体領域７が存
在する。一方、低濃度Ｐ型半導体領域には、高濃度Ｐ型
半導体領域１１と、カソード部を形成する高濃度Ｎ型半
導体領域９が存在する。このような従来技術の構造を有
するサイリスタにおいて、オン状態における抵抗は図６
（サイリスタの等価回路）に示すように、低濃度Ｐ型半
導体領域３に形成された、高濃度Ｎ型半導体領域９（カ
ソード部）と低濃度Ｎ型半導体領域４の間に存在する、
低濃度Ｐ型半導体領域の不純物濃度、及び、低濃度Ｎ型
半導体領域４に形成された、高濃度Ｐ型半導体領域７
（アノード部）と低濃度Ｐ型半導体領域の間に存在す
る、低濃度Ｎ型半導体領域の不純物濃度に大きく依存す
る。以上の説明は、Ｐ型基板にサイリスタを作製する場
合であるが、Ｎ型基板に作製する場合も、プロセス的に
は、全く同様である。In the structure of the prior art manufactured by the above steps, the low concentration N type semiconductor region and the low concentration P type semiconductor region are formed in the substrate, and the low concentration N type semiconductor region and the low concentration N type semiconductor region are formed. The P-type semiconductor region is in contact with the low-concentration N-type semiconductor region, and the high-concentration N-type semiconductor region 10 is included in the low-concentration N-type semiconductor region.
Then, there is a high-concentration P-type semiconductor region 7 forming the anode portion. On the other hand, the low-concentration P-type semiconductor region has a high-concentration P-type semiconductor region 11 and a high-concentration N-type semiconductor region 9 forming a cathode portion. In the thyristor having such a structure of the related art, the resistance in the ON state is as shown in FIG.
As shown in (Equivalent circuit of thyristor), it exists between the high-concentration N-type semiconductor region 9 (cathode part) and the low-concentration N-type semiconductor region 4 formed in the low-concentration P-type semiconductor region 3.
Impurity concentration in the low concentration P-type semiconductor region and high concentration P-type semiconductor region 7 formed in the low concentration N-type semiconductor region 4
It largely depends on the impurity concentration of the low-concentration N-type semiconductor region existing between the (anode portion) and the low-concentration P-type semiconductor region. The above description is for the case of manufacturing the thyristor on the P-type substrate, but the process is exactly the same for the case of manufacturing the N-type substrate.
【００１０】[0010]
【発明が解決しようとする課題】サイリスタの特性は、
一般的に図５に示すような電流ー電圧特性を示す。ここ
で示された特性に於いて、ホールディング電圧は、静電
保護素子としての重要な値となる。サイリスタをＭＯＳ
型半導体の保護素子として用いる場合、高電界がかかっ
た場合に、サイリスタを介して電荷を逃がすことになる
が、このホールディング電圧が、保護したいＭＯＳ型半
導体素子のゲート酸化膜の耐圧より低いことが求められ
る。この酸化膜の耐圧は、プロセスの微細化に伴い、ま
すます低下しており、サイリスタのホールディング電圧
（オン電圧）を低くすることが求められている。The characteristics of thyristors are as follows:
Generally, it exhibits a current-voltage characteristic as shown in FIG. In the characteristics shown here, the holding voltage has an important value as an electrostatic protection element. MOS thyristor
When used as a protective element for a MOS type semiconductor, electric charges are released through a thyristor when a high electric field is applied. However, this holding voltage may be lower than the breakdown voltage of the gate oxide film of the MOS type semiconductor element to be protected. Desired. The breakdown voltage of this oxide film is further decreasing with the miniaturization of the process, and it is required to lower the holding voltage (ON voltage) of the thyristor.
【００１１】そのためサイリスタのホールディング電圧
（オン電圧）を低くするには、図６に示した等価回路の
バイポーラトランジスタのオン電圧をどちらか一方、あ
るいは両方のオン電圧を低くすればよく、この為にはベ
ース領域、つまりアノード部とカソード部の間に存在す
る低濃度Ｎ型半導体領域もしくは低濃度Ｐ型半導体領域
の不純物濃度を低くすればよい。しかしながら、上述し
たような従来構造のサイリスタの構造では、低濃度Ｎ型
半導体領域、もしくは低濃度Ｐ型半導体領域の不純物濃
度を低下させると、図６のＲｓｐおよびＲｓｎで示した
抵抗値も変化させてしまい、結果的にスイッチング電圧
を低下させてしまうという問題がある。即ち、サイリス
タのスイッチング電圧（図５参照）は、これらの抵抗Ｒ
ｓｐおよびＲｓｎに依存しており、また、スイッチング
電圧も、保護すべきプロセスに応じて適切に定める必要
があるために、従属的に変更されるのは望ましくない。Therefore, in order to lower the holding voltage (ON voltage) of the thyristor, one or both of the ON voltages of the bipolar transistors of the equivalent circuit shown in FIG. 6 may be lowered. The base region, that is, the low-concentration N-type semiconductor region or the low-concentration P-type semiconductor region existing between the anode part and the cathode part may have a low impurity concentration. However, in the structure of the conventional thyristor as described above, when the impurity concentration of the low concentration N-type semiconductor region or the low concentration P-type semiconductor region is lowered, the resistance values shown by Rsp and Rsn in FIG. 6 are also changed. Therefore, there is a problem that the switching voltage is lowered as a result. That is, the switching voltage of the thyristor (see FIG. 5) is
Depending on sp and Rsn, and also the switching voltage has to be determined appropriately depending on the process to be protected, it is not desirable for it to be changed dependently.
【００１２】本発明の目的は、ＣＭＯＳプロセスを用い
てつくられ、ＭＯＳ型半導体の保護素子として用いられ
る、サイリスタのホールディング電圧が、プロセスに合
った適切な値を持つようにし、静電保護素子として有効
に機能させることにある。An object of the present invention is to make a holding voltage of a thyristor, which is formed by using a CMOS process and used as a protection element for a MOS type semiconductor, have an appropriate value suitable for the process, and is effective as an electrostatic protection element. To make it work.
【００１３】[0013]
【課題を解決するための手段】上記問題を解決するため
に、請求項１に記載の発明は、Ｐ型半導体基板に低濃度
Ｎ型半導体領域、及び、低濃度Ｐ型半導体領域が形成さ
れ、前記低濃度Ｎ型半導体領域と前記低濃度Ｐ型半導体
領域に挟まれてＰ型半導体基板領域が存在し、かつ、前
記低濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域
と、アノード部を形成する高濃度Ｐ型半導体領域が存在
し、一方、前記低濃度Ｐ型半導体領域には、高濃度Ｐ型
半導体領域が存在すると共に、前記低濃度Ｐ型半導体領
域と基板領域の両領域に接するように、カソード部を形
成する高濃度Ｎ型半導体領域が存在することを特徴とす
るものである。In order to solve the above problems, the invention according to claim 1 forms a low concentration N type semiconductor region and a low concentration P type semiconductor region on a P type semiconductor substrate. A P-type semiconductor substrate region exists between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region, and the low-concentration N-type semiconductor region has a high-concentration N-type semiconductor region and an anode portion. A high-concentration P-type semiconductor region is formed, while a high-concentration P-type semiconductor region is present in the low-concentration P-type semiconductor region, and both the low-concentration P-type semiconductor region and the substrate region are present. It is characterized in that a high-concentration N-type semiconductor region that forms the cathode portion is present so as to be in contact with it.
【００１４】また、請求項２に記載の発明は、請求項１
に記載のＰ型半導体基板の代わりにＮ型半導体基板に適
用したことを特徴とするものである。The invention described in claim 2 is the same as claim 1
It is characterized in that it is applied to an N-type semiconductor substrate instead of the P-type semiconductor substrate described in (1).
【００１５】また、請求項３に記載の発明は、基板表面
に第１の低濃度Ｎ型半導体領域、及び、第１の低濃度Ｐ
型半導体領域が形成され、前記第１の低濃度Ｎ型半導体
領域と前記第１の低濃度Ｐ型半導体領域に挟まれ、前記
第１の低濃度Ｐ型半導体領域よりも不純物濃度が低い、
第２の低濃度Ｐ型半導体領域が存在し、かつ、前記第１
の低濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域
と、アノード部を形成する高濃度Ｐ型半導体領域が存在
し、一方、前記第１の低濃度Ｐ型半導体領域には、高濃
度Ｐ型半導体領域が存在すると共に、前記第１の低濃度
Ｐ型半導体領域と前記第２の低濃度Ｐ型半導体領域の両
領域に接するように、カソード部を形成する高濃度Ｎ型
半導体領域が存在することを特徴とするものである。According to a third aspect of the invention, the first low concentration N-type semiconductor region and the first low concentration P are formed on the surface of the substrate.
A type semiconductor region is formed, is sandwiched between the first low concentration N-type semiconductor region and the first low concentration P-type semiconductor region, and has an impurity concentration lower than that of the first low concentration P-type semiconductor region,
There is a second low-concentration P-type semiconductor region, and the first
In the low-concentration N-type semiconductor region, a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming the anode portion are present, while in the first low-concentration P-type semiconductor region, a high-concentration N-type semiconductor region is formed. A high-concentration N-type semiconductor region forming a cathode portion is formed so that the P-type semiconductor region is present and is in contact with both the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region. It is characterized by the existence.
【００１６】また、請求項４に記載の発明は、基板表面
に第１の低濃度Ｎ型半導体領域、及び、第１の低濃度Ｐ
型半導体領域が形成され、前記第１の低濃度Ｎ型半導体
領域と前記第１の低濃度Ｐ型半導体領域に挟まれ、前記
第１の低濃度Ｎ型半導体領域よりも、不純物濃度が低
い、第２の低濃度Ｎ型半導体領域が存在し、かつ、前記
低濃度Ｐ型半導体領域には、高濃度Ｐ型半導体領域と、
カソード部を形成する高濃度Ｎ型半導体領域が存在し、
一方、前記第１の低濃度Ｎ型半導体領域には、高濃度Ｎ
型半導体領域が存在すると共に、前記第１のＮ型半導体
領域と前記第２のＮ型半導体領域の両領域に接するよう
に、アノード部を形成する高濃度Ｐ型半導体領域が存在
することを特徴とするものである。According to a fourth aspect of the present invention, the first low concentration N-type semiconductor region and the first low concentration P are formed on the surface of the substrate.
A type semiconductor region is formed, sandwiched between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region, and has a lower impurity concentration than the first low-concentration N-type semiconductor region. A second low-concentration N-type semiconductor region exists, and the low-concentration P-type semiconductor region includes a high-concentration P-type semiconductor region;
There is a high-concentration N-type semiconductor region forming the cathode portion,
On the other hand, in the first low concentration N-type semiconductor region, a high concentration N type
And a high-concentration P-type semiconductor region forming an anode portion so as to be in contact with both the first N-type semiconductor region and the second N-type semiconductor region. It is what
【００１７】また、請求項５に記載の発明は、Ｐ型半導
体基板表面に素子分離領域を形成する部分をエッチ後、
絶縁物を埋め込み、平坦化のためのＣＭＰ処理をして素
子分離領域を形成する工程と、低濃度Ｎ型半導体領域を
形成する部分を開口し、Ｎ型不純物を低濃度にイオン注
入し低濃度Ｎ型半導体領域を形成し、続いて前記Ｎ型半
導体領域と所定の距離を離しＰ型半導体基板領域が存在
するように、低濃度Ｐ型半導体領域を形成する部分を開
口し、Ｐ型不純物を低濃度にイオン注入し、低濃度Ｐ型
半導体領域を形成する工程と、前記低濃度Ｎ型半導体領
域上の一部と、前記低濃度Ｐ型半導体領域上の一部を開
口し、Ｐ型不純物を高濃度にイオン注入し、高濃度Ｐ型
半導体領域を形成する工程と、前記低濃度Ｎ型半導体領
域上の一部と、前記低濃度Ｐ型半導体領域と前記Ｐ型半
導体基板領域の接面上の一部を開口し、Ｎ型不純物を高
濃度にイオン注入を行い、高濃度Ｎ型半導体領域を形成
する工程と、熱処理により、注入した不純物を活性化さ
せる工程と、前記高濃度Ｎ型半導体領域と前記高濃度Ｐ
型半導体領域の各領域に、コンタクトを形成し、金属配
線等で、電源、グラウンド、もしくは入出力端子のいず
れかに、電気的に接続する工程とを含むことを特徴とす
るものである。According to a fifth aspect of the invention, after etching a portion for forming an element isolation region on the surface of the P-type semiconductor substrate,
A step of burying an insulator and performing a CMP process for planarization to form an element isolation region, and opening a portion for forming a low-concentration N-type semiconductor region, and ion-implanting an N-type impurity at a low concentration An N-type semiconductor region is formed, and subsequently, a portion where a low-concentration P-type semiconductor region is formed is opened so that a P-type semiconductor substrate region exists at a predetermined distance from the N-type semiconductor region, and a P-type impurity is added. Forming a low concentration P-type semiconductor region by low-concentration ion implantation; opening a portion on the low-concentration N-type semiconductor region and a portion on the low-concentration P-type semiconductor region; Forming a high-concentration P-type semiconductor region by high-concentration ion implantation, a part of the low-concentration N-type semiconductor region, and a contact surface between the low-concentration P-type semiconductor region and the P-type semiconductor substrate region. Ion implantation of high concentration of N-type impurities by opening a part of the top Performed, forming a high-concentration N-type semiconductor region, by heat treatment, a step of activating the implanted impurities, the heavily doped P and the high-concentration N-type semiconductor region
And a step of forming a contact in each region of the type semiconductor region and electrically connecting to a power supply, a ground, or an input / output terminal with a metal wiring or the like.
【００１８】また、請求項６に記載の発明は、請求項５
に記載のＰ型半導体基板の代わりにＮ型半導体基板に適
用したことを特徴とするものである。The invention described in claim 6 is the same as claim 5
It is characterized in that it is applied to an N-type semiconductor substrate instead of the P-type semiconductor substrate described in (1).
【００１９】また、請求項７に記載の発明は、基板表面
に素子分離領域を形成する部分をエッチ後、絶縁物を埋
め込み、平坦化のためのＣＭＰ処理をして素子分離領域
を形成する工程と、低濃度Ｎ型半導体領域を開口し、Ｎ
型不純物を低濃度にイオン注入を行い、第１の低濃度Ｎ
型半導体領域を形成し、続いて前記第１の低濃度Ｎ型半
導体領域と所定の距離を離し、低濃度Ｐ型半導体領域を
開口し、Ｐ型不純物を低濃度にイオン注入を行い、第１
の低濃度Ｐ型半導体領域を形成し、次いで、前記第１の
低濃度Ｎ型半導体領域と前記第１の低濃度Ｐ型半導体領
域に挟まれた領域を開口し、前記第１の低濃度Ｐ型半導
体領域より低濃度のＰ型不純物をイオン注入して、第２
の低濃度Ｐ型半導体領域を形成する工程と、前記第１の
低濃度Ｐ型半導体領域と前記第２の低濃度Ｐ型半導体領
域の接面上の一部と、低濃度Ｎ型半導体領域上の一部を
開口し、Ｎ型不純物を高濃度にイオン注入を行い、高濃
度Ｎ型半導体領域を形成する工程と、前記第１の低濃度
Ｐ型半導体領域上の一部と、前記第１の低濃度Ｎ型半導
体領域上の一部を開口し、Ｐ型不純物を高濃度にイオン
注入を行い、高濃度Ｐ型半導体領域を形成する工程と、
熱処理により、注入した不純物を活性化する工程と、前
記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域の
各領域に、コンタクトを形成し、金属配線等で、電源、
グラウンド、もしくは入出力端子のいずれかに、電気的
に接続する工程とを含むことを特徴とするものである。According to a seventh aspect of the present invention, a step of forming an element isolation region by etching a portion for forming an element isolation region on a substrate surface, burying an insulator, and performing a CMP process for planarization And opening a low concentration N-type semiconductor region,
Type impurities are ion-implanted to a low concentration to obtain a first low-concentration N
Forming a low-concentration P-type semiconductor region, forming a low-concentration P-type semiconductor region at a predetermined distance from the first low-concentration N-type semiconductor region, and ion-implanting a low-concentration P-type impurity into the first low-concentration P-type semiconductor region;
A low-concentration P-type semiconductor region is formed, and a region sandwiched between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region is opened to form the first low-concentration P-type semiconductor region. A second concentration of P-type impurities is ion-implanted from the type-type semiconductor region,
Forming a low-concentration P-type semiconductor region, a part of a contact surface between the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region, and a low-concentration N-type semiconductor region. A part of the first low-concentration P-type semiconductor region is formed by performing high-concentration ion implantation of N- type impurities to form a high-concentration N- type semiconductor region; Forming a high-concentration P- type semiconductor region by opening a part of the low-concentration N-type semiconductor region and performing high-concentration ion implantation of P- type impurities.
A step of activating the implanted impurities by heat treatment, a contact is formed in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and a metal wiring or the like is used to supply power.
And the step of electrically connecting to either the ground or the input / output terminal.
【００２０】また、請求項８に記載の発明は、請求項７
に記載の第２の低濃度Ｐ型半導体領域の代わりに、第２
の低濃度Ｎ型半導体領域を形成することを特徴とするも
のである。結果として、請求項１と請求項５、あるい
は、請求項２と請求項６によれば、サイリスタのオン状
態におけるホールディング電圧は、従来技術に比べ、低
濃度Ｎ型半導体領域もしくは低濃度Ｐ型半導体領域より
も、不純物濃度が低いＮ型もしくはＰ型半導体基板領域
が存在しているために、より低いホールディング電圧と
なる。かつ、この場合、工程の追加を必要としない。ま
た請求項３、請求項７によれば、サイリスタのオン状態
におけるホールディング電圧は、第１の低濃度Ｐ型半導
体領域よりも不純物濃度の低い、第２の低濃度Ｐ型半導
体領域が存在しており、従来技術に比べ、ホールディン
グ電圧は低下する。また、請求項４、請求項８によれ
ば、サイリスタのオン状態におけるホールディング電圧
は、第１の低濃度Ｎ型半導体領域よりも不純物濃度の低
い、第２の低濃度Ｎ型半導体領域が存在しており、従来
技術に比べ、ホールディング電圧は低下する。上記の請
求項のいずれにおいても、低濃度Ｎ型半導体領域中に形
成された、高濃度Ｎ型半導体領域、及び、低濃度Ｐ型半
導体領域中に形成された高濃度Ｐ型半導体領域は、従来
技術と同等の不純物濃度の領域を抵抗領域として、サイ
リスタを形成するために、ホールディング電圧以外の電
気特性、特にスイッチング電圧に影響を及ぼさない。The invention according to claim 8 is the same as claim 7
Instead of the second low-concentration P-type semiconductor region described in
The low-concentration N-type semiconductor region is formed. As a result, according to claim 1 and claim 5, or claim 2 and claim 6, the holding voltage in the ON state of the thyristor is lower than that of the prior art in the low-concentration N-type semiconductor region or the low-concentration P-type semiconductor. Since there is an N-type or P-type semiconductor substrate region having a lower impurity concentration than the region, the holding voltage becomes lower. Moreover, in this case, no additional process is required. According to Claims 3 and 7, the holding voltage in the ON state of the thyristor has the second low-concentration P-type semiconductor region whose impurity concentration is lower than that of the first low-concentration P-type semiconductor region. Therefore, the holding voltage is lower than that of the conventional technique. Further, according to claim 4 and claim 8, the holding voltage in the ON state of the thyristor has a second low concentration N-type semiconductor region having an impurity concentration lower than that of the first low concentration N-type semiconductor region. Therefore, the holding voltage is lower than that of the conventional technique. In any of the above claims, the high-concentration N-type semiconductor region formed in the low-concentration N-type semiconductor region and the high-concentration P-type semiconductor region formed in the low-concentration P-type semiconductor region are Since the region having the same impurity concentration as that of the technology is used as the resistance region to form the thyristor, the electrical characteristics other than the holding voltage, particularly the switching voltage are not affected.
【００２１】[0021]
【発明の実施の形態】以下、実施の形態に基づいて、本
発明について詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail based on the embodiments.
【００２２】Ｐ型シリコン基板に作製する場合を例にと
り、本発明の構造と製造方法を、図１に従って説明す
る。The structure and manufacturing method of the present invention will be described with reference to FIGS.
【００２３】まず、図１（ａ）に示すように、Ｐ型シリ
コン基板（不純物濃度〜２．０×１０15／ｃｍ3）１４
に、基板面にフォトレジストを塗布し、パターニングに
より、素子分離領域を形成する部分のレジストを取り除
く。続いて、シリコン基板をエッチングし、酸化物埋め
込みを行い、化学的機械的研磨（ＣＭＰ）処理を実施
し、素子分離領域１５を形成する。First, as shown in FIG. 1A, a P-type silicon substrate (impurity concentration: 2.0 × 10 15 / cm 3 ) 14 is formed.
Then, a photoresist is applied to the surface of the substrate, and the resist is removed by patterning at the portion forming the element isolation region. Then, the silicon substrate is etched, an oxide is embedded, and a chemical mechanical polishing (CMP) process is performed to form an element isolation region 15.
【００２４】次に、図１（ｂ）に示すように、再度、フ
ォトレジストを塗布し、パターニングにより、低濃度Ｎ
型半導体領域を形成する部分のレジストを除去し、続い
て、リン（31Ｐ+）等のＮ型不純物を低濃度にイオン注
入し、低濃度Ｎ型半導体領域（不純物濃度〜５．０×１
０17／ｃｍ3）１７を形成する。その後、フォトレジス
トを除去し、再びフォトレジストを塗布して、低濃度Ｐ
型半導体領域を形成する部分のレジストを除去し、ボロ
ン（11Ｂ+）等のＰ型不純物を低濃度にイオン注入し、
低濃度Ｐ型半導体領域（不純物濃度〜２．０×１０17／
ｃｍ3）１６を形成する。Next, as shown in FIG. 1B, a photoresist is applied again, and patterning is carried out to obtain a low concentration N.
The resist of the portion forming the type semiconductor region is removed, and then N type impurities such as phosphorus ( 31 P + ) are ion-implanted at a low concentration to reduce the concentration of the low concentration N type semiconductor region (impurity concentration to 5.0 × 1).
0 17 / cm 3 ) 17 is formed. After that, the photoresist is removed, the photoresist is applied again, and the low concentration P
The resist in the portion forming the type semiconductor region is removed, and P type impurities such as boron ( 11 B + ) are ion-implanted at a low concentration,
Low-concentration P-type semiconductor region (impurity concentration-2.0 × 10 17 /
cm 3 ) 16 is formed.
【００２５】次に、図１（ｃ）に示すように、フォトレ
ジスト１８を塗布し、パターニングにより低濃度Ｎ型半
導体領域上の一部と、低濃度Ｐ型半導体領域上の一部を
開口し、ボロン（ＢＦ2+）等のＰ型不純物を基板表面に
対して、ほぼ垂直方向から、高濃度に（〜２．０×１０
15／ｃｍ2、４０ｋｅＶ）イオン注入を行い、高濃度Ｐ
＋半導体領域１９、２０を形成する。ここで領域２０は
サイリスタのアノードとなる領域である。Next, as shown in FIG. 1C, a photoresist 18 is applied and patterned to open a portion on the low concentration N-type semiconductor region and a portion on the low concentration P-type semiconductor region. , P-type impurities such as boron (BF 2+ ) from the direction substantially perpendicular to the substrate surface to a high concentration (up to 2.0 × 10
(15 / cm 2 , 40 keV) ion implantation to obtain high concentration P
+ Semiconductor regions 19 and 20 are formed. Here, the region 20 is a region which becomes an anode of the thyristor.
【００２６】次に、図１（ｄ）に示すように、フォトレ
ジストを除去後、再び塗布し、パターニングにより低濃
度Ｎ型半導体領域上の一部と、低濃度Ｐ型半導体領域と
基板領域の接面上の一部を開口し、ヒ素（75Ａｓ+）等
のＮ型不純物を基板表面に対して、ほぼ垂直方向から、
高濃度に（〜３．０×１０15／ｃｍ2、５０ｋｅＶ）イ
オン注入を行い、高濃度Ｎ型半導体領域２２、２３を形
成する。ここで領域２２はサイリスタのカソードとなる
領域である。Next, as shown in FIG. 1D, after removing the photoresist, it is coated again, and a part of the low concentration N type semiconductor region, the low concentration P type semiconductor region and the substrate region are patterned by patterning. A part of the contact surface is opened, and N-type impurities such as arsenic ( 75 As + ) are formed in a direction substantially perpendicular to the substrate surface.
Ion implantation is performed at a high concentration (up to 3.0 × 10 15 / cm 2 , 50 keV) to form high concentration N-type semiconductor regions 22 and 23. Here, the region 22 is a region which becomes the cathode of the thyristor.
【００２７】次に、図１（ｅ）に示すように、熱処理に
より、図１（ｃ）及び（ｄ）に示す工程で注入した不純
物を活性化する。その後、図１（ｆ）に示すように、高
濃度Ｎ型半導体領域と高濃度Ｐ型半導体領域の各領域
に、コンタクトを形成し、金属配線等２４、２５、２６
で、電源、グラウンド、もしくは入出力端子のいずれか
に、電気的に接続する。Next, as shown in FIG. 1E, heat treatment activates the impurities implanted in the steps shown in FIGS. 1C and 1D. Thereafter, as shown in FIG. 1F, a contact is formed in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region to form metal wirings 24, 25, 26.
Then, it is electrically connected to either the power supply, the ground, or the input / output terminal.
【００２８】以上の工程で作製すると、低濃度Ｎ型半導
体領域と低濃度Ｐ型半導体領域の間に、低濃度Ｐ型半導
体基板が存在するため、オン状態の時のホールディング
電圧が低くなる。本構造によるホールディング電圧の低
減の効果を図９、図１０を用いて説明する。図９は従来
構造による電流電圧特性を示し、図１０は本発明による
電流ー電圧特性を示す。この例では、ホールディング電
圧が約１Ｖ程度低くなっており、一方スイッチング電圧
は従来例と比較してほとんど変化がない。また図２は前
述した図１のＰ型半導体基板に代えて、Ｎ型半導体基板
を用いて形成された、本発明の別の実施例である。この
場合においても、図１と同等の効果がある。When manufactured by the above steps, since the low-concentration P-type semiconductor substrate exists between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region, the holding voltage in the ON state becomes low. The effect of reducing the holding voltage by this structure will be described with reference to FIGS. 9 and 10. FIG. 9 shows current-voltage characteristics according to the conventional structure, and FIG. 10 shows current-voltage characteristics according to the present invention. In this example, the holding voltage is lowered by about 1 V, while the switching voltage is almost unchanged compared to the conventional example. 2 is another embodiment of the present invention formed by using an N-type semiconductor substrate instead of the P-type semiconductor substrate of FIG. 1 described above. Even in this case, the same effect as that of FIG. 1 is obtained.
【００２９】また、図３、図４は本発明による、半導体
装置の別の実施例である。図３では、第１の低濃度Ｎ型
半導体領域４２と第１低濃度Ｐ型半導体領域４０の間
に、第２のＰ型半導体領域４１が存在する。また、図４
では、第１の低濃度Ｐ型半導体領域５２と第１の低濃度
Ｎ型半導体領域５３の間に、第２のＮ型半導体領域５４
が存在する。これら図３と図４に示した実施例では、第
２の低濃度Ｐ型半導体領域、もしくは、第２の低濃度Ｎ
型半導体領域が存在し、この領域の不純物濃度を調整す
ることにより、ホールディング電圧を調整することがで
きる。言い換えれば図３、図４のほうが図１、図２の構
造に比較し、ホールディング電圧をより最適化すること
が可能となる。3 and 4 show another embodiment of the semiconductor device according to the present invention. In FIG. 3, the second P-type semiconductor region 41 exists between the first low-concentration N-type semiconductor region 42 and the first low-concentration P-type semiconductor region 40. Also, FIG.
Then, the second N-type semiconductor region 54 is provided between the first low-concentration P-type semiconductor region 52 and the first low-concentration N-type semiconductor region 53.
Exists. In the embodiment shown in FIGS. 3 and 4, the second low-concentration P-type semiconductor region or the second low-concentration N is used.
There is a type semiconductor region, and the holding voltage can be adjusted by adjusting the impurity concentration of this region. In other words, the holding voltage can be more optimized in FIGS. 3 and 4 than in the structures in FIGS. 1 and 2.
【００３０】次に、本発明によるサイリスタを静電気保
護回路に適用した回路例を図７、及び図８に示す。図７
では電源端子ーグラウンド端子間の保護素子として用い
られ、図８では電源端子ー入出力間の保護素子として用
いられている。上記実施例に示されるように、本発明に
より、従来例よりも低いホールディング電圧を持ち、か
つ、他の特性に影響を与えない、サイリスタが作製可能
となる。このように保護回路としてのサイリスタにおい
て、従来よりも低いホールディング電圧を有するため、
外部から加わった電荷（電圧）は、より低い電圧まで放
電され内部のＩＣやＬＳＩ回路に対して外部電荷（電
圧）の影響が小さくすることが可能となる。Next, FIG. 7 and FIG. 8 show circuit examples in which the thyristor according to the present invention is applied to an electrostatic protection circuit. Figure 7
Is used as a protection element between the power supply terminal and the ground terminal, and is used as a protection element between the power supply terminal and the input / output in FIG. As shown in the above embodiment, according to the present invention, it is possible to manufacture a thyristor having a lower holding voltage than the conventional example and not affecting other characteristics. Thus, in the thyristor as a protection circuit, since it has a lower holding voltage than before,
The charge (voltage) applied from the outside is discharged to a lower voltage, and the influence of the external charge (voltage) on the internal IC or LSI circuit can be reduced.
【００３１】[0031]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、ＣＭＯＳプロセスにより形成されるサイリスタ
において、サイリスタのアノード部とカソード部に挟ま
れた、Ｎ型半導体領域もしくはＰ型半導体領域に相当す
る、第１の低濃度Ｎ型半導体領域と第１の低濃度Ｐ型半
導体領域の間に、第１の低濃度Ｎ型半導体領域よりも不
純物濃度の低い、第２の低濃度Ｎ型半導体領域もしくは
半導体基板領域を形成する、あるいは、第１の低濃度Ｐ
型半導体領域よりも不純物濃度の低い、第２の低濃度Ｐ
型半導体領域もしくは半導体基板領域を形成することに
より、ホールディング電圧を低くすることが可能であ
る。また、スイッチング電圧等のサイリスタの他の電気
特性は、従来構造と同様に決定され、ホールディング電
圧以外の特性には影響を与えない。As described above in detail, according to the present invention, in the thyristor formed by the CMOS process, the N-type semiconductor region or the P-type semiconductor region sandwiched between the anode part and the cathode part of the thyristor is provided. Corresponding to the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region, the second low-concentration N-type having a lower impurity concentration than the first low-concentration N-type semiconductor region. Forming a semiconductor region or a semiconductor substrate region, or a first low concentration P
Second low concentration P having an impurity concentration lower than that of the type semiconductor region
The holding voltage can be lowered by forming the type semiconductor region or the semiconductor substrate region. Further, other electrical characteristics of the thyristor, such as switching voltage, are determined in the same manner as in the conventional structure and do not affect characteristics other than the holding voltage.
【００３２】以上のように、本発明により、微細プロセ
スに適した、低い酸化膜耐圧を持つプロセスに対する、
有効な半導体装置を形成する事が可能である。As described above, according to the present invention, for a process suitable for a fine process and having a low oxide film withstand voltage,
It is possible to form an effective semiconductor device.
【図１】本発明の実施例の工程断面図である。FIG. 1 is a process sectional view of an example of the present invention.
【図２】本発明の別の実施例の断面図である。FIG. 2 is a sectional view of another embodiment of the present invention.
【図３】本発明の別の実施例の断面図である。FIG. 3 is a cross-sectional view of another embodiment of the present invention.
【図４】本発明の別の実施例の断面図である。FIG. 4 is a cross-sectional view of another embodiment of the present invention.
【図５】一般的なサイリスタの電流−電圧特性を示す図
である。FIG. 5 is a diagram showing current-voltage characteristics of a general thyristor.
【図６】サイリスタの等価回路を示す図である。FIG. 6 is a diagram showing an equivalent circuit of a thyristor.
【図７】本発明の保護回路の第１の適用例である。FIG. 7 is a first application example of the protection circuit of the present invention.
【図８】本発明の保護回路の第２の適用例である。FIG. 8 is a second application example of the protection circuit of the present invention.
【図９】従来例の電流ー電圧特性を示す図である。FIG. 9 is a diagram showing current-voltage characteristics of a conventional example.
【図１０】本発明による電流ー電圧特性を示す図であ
る。FIG. 10 is a diagram showing current-voltage characteristics according to the present invention.
【図１１】従来例の工程断面図である。FIG. 11 is a process sectional view of a conventional example.
１４ Ｐ型シリコン基板
１７、３０ 低濃度Ｎ型半導体領域
１６、２９ 低濃度Ｐ型半導体領域
１５、２８、３９、５１ 素子分離絶縁部
２３、３４、４６、５８ Ｎ型高濃度半導体領域
２２、３３、４５、５７ Ｎ型高濃度半導体領域（カソ
ード部）
１９、３１、４３、５５ Ｐ型高濃度半導体領域
２０、３２、４４、５６ Ｐ型高濃度半導体領域（アノ
ード部）
２４、２５、２６、３５、３６、３７、４７、４８、４
９ 、５９、６０、６１ 配線部
２７ Ｎ型シリコン基板
３８、５０ Ｐ型シリコン基板もしくはＮ型シリコン基
板
４２、５３ 第１の低濃度Ｎ型半導体領域
４０、５２ 第１の低濃度Ｐ型半導体領域
５４ 第２の低濃度Ｎ型半導体領域
４１ 第２の低濃度Ｐ型半導体領域14 P-type silicon substrate 17, 30 Low-concentration N-type semiconductor region 16, 29 Low-concentration P-type semiconductor region 15, 28, 39, 51 Element isolation insulating portions 23, 34, 46, 58 N-type high-concentration semiconductor region 22, 33 , 45, 57 N-type high-concentration semiconductor region (cathode part) 19, 31, 43, 55 P-type high-concentration semiconductor region 20, 32, 44, 56 P-type high-concentration semiconductor region (anode part) 24, 25, 26, 35, 36, 37, 47, 48, 4
9, 59, 60, 61 Wiring portion 27 N-type silicon substrate 38, 50 P-type silicon substrate or N-type silicon substrate 42, 53 First low-concentration N-type semiconductor region 40, 52 First low-concentration P-type semiconductor region 54 second low-concentration N-type semiconductor region 41 second low-concentration P-type semiconductor region
Claims (9)
域、及び、低濃度Ｐ型半導体領域が形成され、前記低濃
度Ｎ型半導体領域と前記低濃度Ｐ型半導体領域に挟まれ
てＰ型半導体基板領域が存在し、かつ、前記低濃度Ｎ型
半導体領域には、高濃度Ｎ型半導体領域と、アノード部
を形成する高濃度Ｐ型半導体領域が存在し、一方、前記
低濃度Ｐ型半導体領域には、高濃度Ｐ型半導体領域が存
在すると共に、前記低濃度Ｐ型半導体領域と基板領域の
両領域に接するように、カソード部を形成する高濃度Ｎ
型半導体領域が存在することを特徴とする半導体装置。1. A low-concentration N-type semiconductor region and a low-concentration P-type semiconductor region are formed on a P-type semiconductor substrate, and P-type is sandwiched between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region. There is a semiconductor substrate region, and the low-concentration N-type semiconductor region has a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming an anode portion, while the low-concentration P-type semiconductor region is present. A high-concentration P-type semiconductor region exists in the region, and a high-concentration N forming a cathode portion is in contact with both the low-concentration P-type semiconductor region and the substrate region.
A semiconductor device having a type semiconductor region.
域、及び、低濃度Ｐ型半導体領域が形成され、前記低濃
度Ｎ型半導体領域と前記低濃度Ｐ型半導体領域に挟まれ
てＮ型半導体基板領域が存在し、かつ、前記低濃度Ｐ型
半導体領域には、高濃度Ｐ型半導体領域と、カソード部
を形成する高濃度Ｎ型半導体領域が存在し、一方、前記
低濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域が存
在すると共に、前記低濃度Ｎ型半導体領域と基板領域の
両領域に接するように、アノード部を形成する高濃度Ｐ
型半導体領域が存在することを特徴とする半導体装置。2. A low-concentration N-type semiconductor region and a low-concentration P-type semiconductor region are formed on an N-type semiconductor substrate, and the N-type is sandwiched between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region. There is a semiconductor substrate region, and the low-concentration P-type semiconductor region has a high-concentration P-type semiconductor region and a high-concentration N-type semiconductor region forming a cathode portion, while the low-concentration N-type semiconductor region is present. A high-concentration N-type semiconductor region exists in the region, and a high-concentration P that forms an anode portion is in contact with both the low-concentration N-type semiconductor region and the substrate region.
A semiconductor device having a type semiconductor region.
域、及び、第１の低濃度Ｐ型半導体領域が形成され、前
記第１の低濃度Ｎ型半導体領域と前記第１の低濃度Ｐ型
半導体領域に挟まれ、前記第１の低濃度Ｐ型半導体領域
よりも不純物濃度が低い、第２の低濃度Ｐ型半導体領域
が存在し、かつ、前記第１の低濃度Ｎ型半導体領域に
は、高濃度Ｎ型半導体領域と、アノード部を形成する高
濃度Ｐ型半導体領域が存在し、一方、前記第１の低濃度
Ｐ型半導体領域には、高濃度Ｐ型半導体領域が存在する
と共に、前記第１の低濃度Ｐ型半導体領域と前記第２の
低濃度Ｐ型半導体領域の両領域に接するように、カソー
ド部を形成する高濃度Ｎ型半導体領域が存在することを
特徴とする半導体装置。3. A first low-concentration N-type semiconductor region and a first low-concentration P-type semiconductor region are formed on a substrate surface, and the first low-concentration N-type semiconductor region and the first low-concentration region are formed. There is a second low-concentration P-type semiconductor region sandwiched between P-type semiconductor regions and having a lower impurity concentration than the first low-concentration P-type semiconductor region, and the first low-concentration N-type semiconductor region is present. Has a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming the anode portion, while the first low-concentration P-type semiconductor region has a high-concentration P-type semiconductor region. At the same time, a high-concentration N-type semiconductor region forming a cathode portion is present so as to be in contact with both the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region. Semiconductor device.
域、及び、第１の低度Ｐ型半導体領域が形成され、前記
第１の低濃度Ｎ型半導体領域と前記第１の低濃度Ｐ型半
導体領域に挟まれ、前記第１の低濃度Ｎ型半導体領域よ
りも、不純物濃度が低い、第２の低濃度Ｎ型半導体領域
が存在し、かつ、前記低濃度Ｐ型半導体領域には、高濃
度Ｐ型半導体領域と、カソード部を形成する高濃度Ｎ型
半導体領域が存在し、一方、前記第１の低濃度Ｎ型半導
体領域には、高濃度Ｎ型半導体領域が存在すると共に、
第１のＮ型半導体領域と第２のＮ型半導体領域の両領域
に接するように、アノード部を形成する高濃度Ｐ型半導
体領域が存在することを特徴とする半導体装置。4. A first low-concentration N-type semiconductor region and a first low-concentration P-type semiconductor region are formed on a substrate surface, and the first low-concentration N-type semiconductor region and the first low-concentration region are formed. There is a second low-concentration N-type semiconductor region sandwiched between the P-type semiconductor regions and having a lower impurity concentration than the first low-concentration N-type semiconductor region, and the low-concentration P-type semiconductor region is present. A high-concentration P-type semiconductor region and a high-concentration N-type semiconductor region forming the cathode portion are present, while a high-concentration N-type semiconductor region is present in the first low-concentration N-type semiconductor region,
A semiconductor device comprising a high-concentration P-type semiconductor region forming an anode portion so as to be in contact with both the first N-type semiconductor region and the second N-type semiconductor region.
成する部分をエッチ後、絶縁物を埋め込み、平坦化のた
めのＣＭＰ処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を形成する部分を開口し、Ｎ型不
純物を低濃度にイオン注入し低濃度Ｎ型半導体領域を形
成し、続いて前記Ｎ型半導体領域と所定の距離を離しＰ
型半導体基板領域が存在するように、低濃度Ｐ型半導体
領域を形成する部分を開口し、Ｐ型不純物を低濃度にイ
オン注入し、低濃度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域上の一部と、前記低濃度Ｐ型
半導体領域上の一部を開口し、Ｐ型不純物を高濃度にイ
オン注入し、高濃度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域上の一部と、前記低濃度Ｐ型
半導体領域と前記Ｐ型半導体基板領域の接面上の一部を
開口し、Ｎ型不純物を高濃度にイオン注入を行い、高濃
度Ｎ型半導体領域を形成する工程と、 熱処理により、注入した不純物を活性化させる工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。5. A step of forming an element isolation region by etching a portion for forming an element isolation region on a surface of a P-type semiconductor substrate, and then burying an insulating material and performing a CMP process for planarization, and a low concentration N type A portion for forming a semiconductor region is opened, N-type impurities are ion-implanted at a low concentration to form a low-concentration N-type semiconductor region, and then a predetermined distance is provided from the N-type semiconductor region.
Forming a low-concentration P-type semiconductor region, forming a low-concentration P-type semiconductor region, and forming a low-concentration P-type semiconductor region by ion-implanting P-type impurities at a low concentration. Forming a high-concentration P-type semiconductor region by opening a portion of the N-type semiconductor region and a portion of the low-concentration P-type semiconductor region, and ion-implanting a P-type impurity at a high concentration; A portion of the high concentration N-type semiconductor region and a portion of the contact surface between the low concentration P-type semiconductor region and the P-type semiconductor substrate region are opened to perform high-concentration ion implantation of N-type impurities. Forming an N-type semiconductor region; activating the implanted impurities by heat treatment; forming a contact in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region; Power supply, ground, or input / output terminal And a step of electrically connecting to any one of the children.
成する部分をエッチ後、絶縁物を埋め込み、平坦化のた
めのＣＭＰ処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を形成する部分を開口し、Ｎ型不
純物を低濃度にイオン注入し低濃度Ｎ型半導体領域を形
成し、続いて前記Ｎ型半導体領域と所定の距離を離しＮ
型半導体基板領域が存在するように、低濃度Ｐ型半導体
領域を形成する部分を開口し、Ｐ型不純物を低濃度にイ
オン注入し低濃度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域と前記Ｎ型半導体基板領域の
接面上の一部と、前記低濃度Ｐ型半導体領域上の一部を
開口し、Ｐ型不純物を高濃度にイオン注入を行い、高濃
度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域上の一部と、前記低濃度Ｐ型
半導体領域上の一部を開口し、Ｎ型不純物を高濃度にイ
オン注入を行い、高濃度Ｎ型半導体領域を形成する工程
と、 熱処理により、注入した不純物を活性化させる工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。6. A step of forming an element isolation region by etching a portion where an element isolation region is formed on the surface of an N-type semiconductor substrate, then burying an insulating material, and performing a CMP process for planarization, and a low concentration N type A portion for forming a semiconductor region is opened, N-type impurities are ion-implanted at a low concentration to form a low-concentration N-type semiconductor region, and then a predetermined distance from the N-type semiconductor region is set.
Forming a low-concentration P-type semiconductor region, and forming a low-concentration P-type semiconductor region by opening a portion for forming the low-concentration P-type semiconductor region and ion-implanting P-type impurities at a low concentration; A part of the contact surface between the N-type semiconductor region and the N-type semiconductor substrate region and a part of the low-concentration P-type semiconductor region are opened, and P-type impurities are ion-implanted at a high concentration to obtain a high-concentration P-type impurity. Forming a semiconductor region; opening a portion of the low-concentration N-type semiconductor region and a portion of the low-concentration P-type semiconductor region, and performing high-concentration ion implantation of N-type impurities; Forming an N-type semiconductor region; activating the implanted impurities by heat treatment; forming a contact in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region; Etc., power supply, ground, or input / output And a step of electrically connecting to any of the terminals.
をエッチ後、絶縁物を埋め込み、平坦化のためのＣＭＰ
処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を開口し、Ｎ型不純物を低濃度に
イオン注入を行い、第１の低濃度Ｎ型半導体領域を形成
し、続いて前記第１の低濃度Ｎ型半導体領域と所定の距
離を離し、低濃度Ｐ型半導体領域を開口し、Ｐ型不純物
を低濃度にイオン注入を行い、第１の低濃度Ｐ型半導体
領域を形成し、次いで、前記第１の低濃度Ｎ型半導体領
域と前記第１の低濃度Ｐ型半導体領域に挟まれた領域を
開口し、前記第１の低濃度Ｐ型半導体領域より低濃度の
Ｐ型不純物をイオン注入して、第２の低濃度Ｐ型半導体
領域を形成する工程と、 前記第１の低濃度Ｐ型半導体領域と前記第２の低濃度Ｐ
型半導体領域の接面上の一部と、低濃度Ｎ型半導体領域
上の一部を開口し、Ｎ型不純物を高濃度にイオン注入を
行い、高濃度Ｎ型半導体領域を形成する工程と、 前記第１の低濃度Ｐ型半導体領域上の一部と、前記第１
の低濃度Ｎ型半導体領域上の一部を開口し、Ｐ型不純物
を高濃度にイオン注入を行い、高濃度Ｐ型半導体領域を
形成する工程と、 熱処理により、注入した不純物を活性化する工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。7. CMP for planarization after etching a portion for forming an element isolation region on a substrate surface and burying an insulator.
A step of performing a treatment to form an element isolation region, opening the low-concentration N-type semiconductor region, and ion-implanting an N-type impurity at a low concentration to form a first low-concentration N-type semiconductor region, and subsequently, The first low-concentration N-type semiconductor region is separated from the first low-concentration N-type semiconductor region by a predetermined distance, the low-concentration P-type semiconductor region is opened, and P-type impurities are ion-implanted at a low concentration to form a first low-concentration P-type semiconductor region. Then, a region sandwiched between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region is opened, and the P-type having a lower concentration than the first low-concentration P-type semiconductor region is opened. Forming a second low-concentration P-type semiconductor region by ion-implanting impurities; and the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region.
Forming a high-concentration N- type semiconductor region by opening a part of the contact surface of the type semiconductor region and a part of the low-concentration N-type semiconductor region and performing high-concentration ion implantation of N- type impurities; A part of the first low-concentration P-type semiconductor region and the first
Of a part of the low-concentration N-type semiconductor region is opened, P- type impurities are ion-implanted at a high concentration to form a high-concentration P- type semiconductor region, and a step of activating the implanted impurities by heat treatment And a contact is formed in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and electrically connected to either a power supply, a ground, or an input / output terminal by a metal wiring or the like. A method of manufacturing a semiconductor device, the method comprising:
をエッチ後、絶縁物を埋め込み、平坦化のためのＣＭＰ
処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を開口し、Ｎ型不純物を低濃度に
イオン注入を行い、第１の低濃度Ｎ型半導体領域を形成
し、続いて前記第１の低濃度半導体領域と所定の距離を
離し、低濃度Ｐ型半導体領域を開口し、Ｐ型不純物を低
濃度にイオン注入を行い、第１の低濃度Ｐ型半導体領域
を形成し、次いで、前記第１の低濃度Ｎ型半導体領域と
前記第１の低濃度Ｐ型半導体領域に挟まれた領域を開口
し、前記第１の低濃度Ｎ型半導体領域より低濃度のＮ型
不純物をイオン注入して、第２の低濃度Ｎ型半導体領域
を形成する工程と、 前記第１の低濃度Ｐ型半導体領域上の一部と、前記第１
の低濃度Ｎ型半導体領域上の一部を開口し、Ｎ型不純物
を高濃度にイオン注入を行い、高濃度Ｎ型半導体領域を
形成する工程と、 前記第１の低濃度Ｎ型半導体領域と前記第２の低濃度Ｎ
型半導体領域の接面上の一部と、低濃度Ｐ型半導体領域
上の一部を開口し、Ｐ型不純物を高濃度にイオン注入を
行い、高濃度Ｐ型半導体領域を形成する工程と、 熱処理により、注入した不純物を活性化する工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。8. A CMP for planarization after etching a portion for forming an element isolation region on a surface of a substrate and then burying an insulator.
A step of performing a treatment to form an element isolation region, opening the low-concentration N-type semiconductor region, and ion-implanting an N-type impurity at a low concentration to form a first low-concentration N-type semiconductor region, and subsequently, A predetermined distance from the first low-concentration semiconductor region, a low-concentration P-type semiconductor region is opened, and P-type impurities are ion-implanted at a low concentration to form a first low-concentration P-type semiconductor region, Then, a region sandwiched between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region is opened, and an N-type impurity having a lower concentration than that of the first low-concentration N-type semiconductor region is opened. Ion-implanting to form a second low-concentration N-type semiconductor region; a part of the first low-concentration P-type semiconductor region;
Forming a high-concentration N-type semiconductor region by opening a part of the low-concentration N-type semiconductor region and ion-implanting an N-type impurity at a high concentration, and the first low-concentration N-type semiconductor region. The second low concentration N
Forming a high-concentration P-type semiconductor region by opening a portion of the contact surface of the type semiconductor region and a portion of the low-concentration P-type semiconductor region, and performing high-concentration ion implantation of P-type impurities; A step of activating the implanted impurities by heat treatment, forming contacts in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and using metal wiring or the like to supply power, ground, or input / output. And a step of electrically connecting to any of the terminals.
半導体装置を、スイッチング電圧を低減するための構造
もしくは回路に組み込んだ事を特徴とする半導体装置。9. A semiconductor device in which the semiconductor device according to any one of claims 1 to 4 is incorporated in a structure or a circuit for reducing a switching voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36583998A JP3398077B2 (en) | 1998-12-24 | 1998-12-24 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36583998A JP3398077B2 (en) | 1998-12-24 | 1998-12-24 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000188389A JP2000188389A (en) | 2000-07-04 |
| JP3398077B2 true JP3398077B2 (en) | 2003-04-21 |
Family
ID=18485250
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36583998A Expired - Lifetime JP3398077B2 (en) | 1998-12-24 | 1998-12-24 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3398077B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002037566A2 (en) * | 2000-11-06 | 2002-05-10 | Sarnoff Corporation | Silicon controlled rectifier electrostatic discharge protection device with external on-chip triggering and compact internal dimensions for fast triggering |
| JP4588247B2 (en) * | 2001-04-27 | 2010-11-24 | セイコーインスツル株式会社 | Semiconductor device |
| TWI258838B (en) | 2004-04-23 | 2006-07-21 | Nec Electronics Corp | Electrostatic protection device |
-
1998
- 1998-12-24 JP JP36583998A patent/JP3398077B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000188389A (en) | 2000-07-04 |
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