JPH09306171A - Multi-port memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-port memory circuit which has a circuit constitution in which one contact in a memory cell is not driven simultaneously by two gates and can reduce rewriting time of a memory cell and power consumption. SOLUTION: In this multi-port memory circuit, a memory cell 100b is provided with a first NOR gate and a second NOR gate as a NOR gate 102, an output of the second NOR gate is connected to a first input of the first NOR gate, while an output of the first NOR gate is connected to a first input of the second NOR gate, also, writing bit lines 12, 13 are connected respectively to a second input of the first NOR gate and a second input of the second NOR gate through a MOS transistor 1 of which conduction/non-conduction is controlled by writing word lines 10, 11. Two gates or more are not driven simultaneously for all contacts of the memory cell 100b in writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-port memory circuit which is used mainly in an arithmetic processing unit and which has a plurality of functionally divided ports.

[0002]

2. Description of the Related Art Conventionally, a general arithmetic processing device is provided with a register file for temporarily holding data to be operated, and this register file has a read port for supplying a plurality of data to an arithmetic unit at the same time. A multi-port memory having a plurality of is used. In addition, the register file also has a write port independent of the read port so that writing can be performed simultaneously with reading. Incidentally, a memory with a built-in LSI chip such as a cache memory may be provided with a plurality of ports so that a plurality of data can be simultaneously accessed.

FIG. 7 is a circuit diagram showing the basic structure of a conventional multi-port memory circuit. This multi-port memory circuit is based on the 1995 iTriple, Custom Integrated Circuits Conference (IEEE).
CUSTOMINTEGRATEDCIRCUITSC
ONFERENCE), it is designed as a circuit of a register file and is a memory circuit having two read ports and two write ports.

Referring to FIG. 7, in a memory cell 100a used as a conventional multi-port memory, the input and output of two inverters 101 are connected to each other to form a feedback loop to store a data value therein. The set of write bit lines 12 and 13 is connected via the MOS transistor 1 controlled by the write word lines 10 and 11. The read bit lines 22 and 23 are connected to the ground by two MOS transistors 1 in series, and the gate of one of the MOS transistors 1 is the read word line 2
0 and 21, the gate of the other MOS transistor 1 is connected to two contacts of the feed pack loop (hereinafter, similarly, the connection points in the circuit configuration are also shown). Further, in the pair of inverters 101 of the memory cell 100a, 0 is written in one contact and 1 is written in the other contact.

Therefore, when reading the data value held in the pair of the inverters 101, first, the precharge circuit 1
The precharge signal 30 of 05 is set to the low level, and the precharge circuit 105 reads the read bit line 22,
23 is precharged to a high level. next,
When precharged, the read bit lines 22 and 23 have the same potential. Then, the corresponding address decoder 106 reads the read word line 20 according to the determined address.
21 is set to a high level to turn on the read MOS transistor 1. As a result, the MOS transistor 1 having its gate connected to the contact holding one of the pair of inverters 101 is turned on, and the potential of one of the read bit lines 22 and 23 is lowered to the low level. This is detected by the sense-up 104 and the data value is taken out to the read data lines 24 and 25. Finally, the read word lines 20 and 21 are lowered to the low level to turn on the MOS.
The transistor 1 is turned off.

On the other hand, when writing a data value to the memory cell 100a, it is assumed that 0 is held at the left contact and 1 is held at the right contact of the pair of the inverters 101 of the memory cell 100a in the first state. The operation when writing the reverse pattern will be described. In this case, 0 is first applied to the write data line 14 and the write bit line 1
Of the two pairs of 2, the left side is 1 and the right side is 0. next,
The write word line 10 corresponding to the address designated by the address decoder 106 goes to high level to turn on the MOS transistor 1. As a result, the data value written in the write bit line 12 tries to change the data value at the contact point of the memory cell 100a through the MOS transistor 1. At this time, the inverter 101
Since it is a feedback loop, it tries to retain the original data value, but since the drive capability of the inverter 101 that drives the write bit line 12 is high, the signal on the write side becomes dominant and the data value is rewritten.
Finally, when the data value is rewritten, the write word line 10 is lowered to the low level and the MOS transistor 1 is turned off. Similar writing is performed in the case of the set of the write data line 15, the write word line 11, and the write bit line 13.

FIG. 8 is a timing chart showing a signal change of the memory cell 100a during a write operation in this multiport memory circuit.

Here, the left and right sides of the write bit line are in the state shown in the figure, and the write word line is hi.
At the gh level, the data value of the write bit line is transmitted to the input of the inverter 101 through the MOS transistor 1 controlled by the write word line, and this signal is transmitted to the contacts on the opposite side through the inverter 101, whereby the left write is performed. It shows how the signal from the word line to the inverter input and the upper inverter output signal and the signal from the right write word line to the inverter input and the lower inverter output signal are obtained. Further, here, there is a delay inherent in the inverter 101 before the signal is transmitted, and in reality, the potential generated at the contact point of the feedback loop formed by the pair of the inverters 101 and the signal transmitted from the write bit line through the MOS transistor 1 and the inverter 101. 2 shows that the signal potential change is delayed because it becomes a combined output (signal potential of the left contact of the inverter pair, signal potential of the right contact of the inverter pair).

Incidentally, as other well-known techniques related to the above-mentioned register file, multiport memory circuit, and memory cell, there are a multiport video DRAM disclosed in Japanese Patent Laid-Open No. 2-208890, a Japanese Patent Laid-Open No. 2-208890. 22
A computer equipped with a multiport cache memory disclosed in Japanese Patent No. 7753, a multiport memory device disclosed in Japanese Patent Laid-Open No. 3-122891, and Japanese Patent Laid-Open No. 4-228.
Multiport Bipolar CM disclosed in Japanese Patent No. 181
An OS memory cell, a multiport memory disclosed in Japanese Patent Laid-Open No. 5-151769, and the like can be mentioned.

[0010]

In the case of the above-mentioned multi-port memory circuit, one inverter in the memory cell and two inverters in the memory cell simultaneously drive one contact in the memory cell. When rewriting the data value of the cell, the force of the write bit line inverter to drive the write bit line and the force of the memory cell inverter to hold the data value collide with each other, which causes the data value of the memory cell There is a problem that it takes a considerable amount of time to stabilize.

Further, until the data value stabilizes, the path through which the current flows from the power supply to the ground is saved, so that there is a problem that a large current flows and the power consumption increases.

The present invention has been made to solve such a problem, and its technical problem is to solve the problem of
It is an object of the present invention to provide a multi-port memory circuit which has a circuit configuration in which one contact is not driven by two gates at the same time and which can reduce the rewriting time of a memory cell and the power consumption.

[0013]

According to the present invention, in a multi-port memory circuit having a plurality of ports including a read port and an independent write port and including a memory cell, the memory cell has a NOR gate. The circuit is obtained.

In this multi-port memory circuit, the memory cell has a first NOR gate and a second NOR gate as NOR gates.
NOR gate of the second NOR gate is connected to the first input of the first NOR gate, and the first NO gate is connected to the first input of the second NOR gate.
The output of the R gate is connected to each of the second input of the first NOR gate and the second input of the second NOR gate via a transistor whose opening and closing is controlled by a word line. It is preferable to connect the bit lines.

On the other hand, according to the present invention, in a multi-port memory circuit having a plurality of ports including a read port and an independent write port, and including a memory cell,
A multi-port memory circuit having a NAND gate can be obtained as the memory cell.

In this multi-port memory circuit, the memory cell includes a first NAND gate and a second NAND gate as NAND gates, and the first NAND gate has a first input and an output of the second NAND gate. And an output of the first NAND gate is connected to a first input of the second NAND gate, and a second input of the first NOR gate and the second NAND gate are connected. It is preferable to connect the bit line to each of the second inputs of the bit lines through a transistor whose opening / closing is controlled by the word line.

[0017]

In the multiport memory circuit of the present invention, the memory cell is provided with a NOR gate and a NAND gate. In such a NOR gate and NAND gate, one of two inputs is fed back to hold a data value. It is used to form a loop and the remaining one input is connected to the write bit line and used to rewrite the data value. Therefore, two gates do not drive one contact point in the memory cell at the same time, the time until the held data becomes stable is reduced, and there is no path penetrating from the power supply to the ground. Power consumption becomes unnecessary.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The multi-port memory circuit of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the basic configuration of a multiport memory circuit according to the first embodiment of the present invention.

In this multi-port memory circuit, unlike the memory cell 100a including the pair of inverters 101 shown in FIG. 7, two NOR gates 102 (one of which is the first NOR gate and the other of which is the second NOR gate 102) are provided. (Which may also be referred to as a NOR gate of the above) is used.

In this memory cell 100b, one of the two inputs of the NOR gate 102 is used to form a feedback loop to hold the data value in the feedback loop and the other of the two inputs of the NOR gate is written. MO controlled by word lines 10 and 11
Write bit lines 12 and 13 via the S transistor 1
Connected to The read bit lines 22 and 23 are connected to the ground by two MOS transistors 1 in series, and the gate of one MOS transistor 1 has a read word 2
0 and 21, and the gate of the other MOS transistor 1 is connected to the two contacts of the feedpack loop.

In other words, in other words, the memory cell 1 here
00b includes a first NOR gate and a second NOR gate as the NOR gate 102, connects the output of the second NOR gate to the first input of the first NOR gate, and connects the output of the second NOR gate. First NOR on first input
A MOS transistor 1 which is connected to the output of the gate and whose opening and closing are controlled by the write word lines 10 and 11 to the second input of the first NOR gate and the second input of the second NOR gate, respectively. The write bit lines 12 and 13 are connected via the.

Therefore, the operation of the memory cell 100b here will be described. The read port has the same configuration as the conventional circuit shown in FIG. 7 and operates similarly. That is,
The read bit line on the side of the contact where 1 of the feedback loop is held becomes low level, which is detected by the sense amplifier 104 and read data lines 24, 2
5 is output.

On the other hand, regarding the write operation, of the two contacts of the feedback loop of the memory cell 100b, data is held so that the left side is 0 and the right side is 1, and the write operation is such that the held data is inverted. Will be performed. In this case, first, 0 is applied to the write data line 14, 1 is applied to the bit line on the left side of the write bit line 12, and 0 is applied to the right side. After the data value of the bit line is determined, when the write word line 10 becomes high level by the address recorder 106, the MOS transistor 1 is turned on. NOR gate 102 on the upper side in the figure
Has 0 input on the feedback side and 1 input on the write side
Therefore, the output becomes 0, but the lower NOR gate 1
In 02, both inputs become 0, so the output becomes 1,
The data value held is inverted from that in the initial state. Finally, the write word line 10 becomes low level, and 1 is written in the left contact and 0 is written in the right contact of the loop.
The same write operation is performed on the set of write data line 15, write word line 11, and write bit line 13.

In the operation described above, while the held data is being rewritten in the memory cell 100b, it is arranged that all the contacts are not driven to different data values by two or more gates at the same time.

FIG. 2 is a timing chart showing the signal change of the memory cell during the write operation in this multi-port memory circuit.

Here, when the left and right sides of the write word line rise in the state shown in the figure, the content of the data on the write bit line is transmitted to the NOR gate 102 through the MOS transistor 1, and the NOR gate 102 receives this signal, It is shown that by changing the output, the signal from the left write word line to the NOR gate input and the upper inverter output signal and the signal from the right write word line to the NOR gate input and the lower inverter output signal are obtained. . Further, here, the potential of the contact point of the feedback loop formed by the pair of NOR gates 102 is the output itself of the NOR gate 102. Therefore, as shown in FIG. 8, compared with the change in the potential of the contact point of the feedback loop of the conventional circuit, It can be seen that the potential change in this multi-port memory circuit is fast (the signal potential of the left contact of the NOR gate pair, the signal potential of the right contact of the NOR gate pair).

Further, in the case of this multi-port memory circuit, the number of transistors per cell (the number of MOS transistors 1) is increased by 4 by configuring the memory cell 100b with the NOR gate 102. However, when the multiport memory circuit is actually laid out as an LSI, the number of bit lines and word lines required for reading and writing of the memory is large, and the area of the memory cell 100b is determined by the wiring arrangement. However, even if the number of transistors is increased by 4, the area is hardly affected.

FIG. 3 is a circuit diagram showing a memory cell 100c which is a main part configuration of a multiport memory circuit according to the second embodiment of the present invention.

In this multiport memory circuit, the NOR gate 102 of the memory cell 100b of the first embodiment is NAN.
The circuit configuration is the same as that of the first embodiment except that the memory cell 100c is used instead of the D gate 103.

That is, this memory cell 100c has a NAN
A first NAND gate and a second NAND gate are provided as the D gate 103, and the output of the second NAND gate is connected to the first input of the first NAND gate.
The output of the first NAND gate is connected to the first input of the second NAND gate, and the second input of the first NOR gate and the second input of the second NAND gate are connected to each other. The write bit lines 12 and 13 are connected via the MOS transistor 1 whose opening and closing are controlled by the write word lines 10 and 11.

Since the memory cell 100c uses the NAND gate 103, the operation is almost the same as that when the NOR gate 102 is used, but the operation at the time of writing is different. That is, at the time of writing, when the write word line 10 becomes high level and the MOS transistor 1 is turned on, it is connected to the write bit line to which 0 is given, out of the two NAND gates 103 forming the memory cell 100c. The output of the NAND gate 103 becomes 1, and then the other NAND
When the output of the gate 103 becomes 0, the held data is changed. As in the case of using the NOR gate 102, one contact does not drive two or more gates at the same time.

FIG. 4 is a circuit diagram showing a memory cell 100d which is a main part configuration of a multi-port memory circuit according to the third embodiment of the present invention.

In the memory cell 100d, the write word line and the memory cell 1 are formed by using the NAND gate 103.
The connection in 00d is changed to the p-type MOS transistor 2. The NAND gate 103 is connected to the memory cell 10
When used for 0d, N connected to the write bit line
When the input levels of the AND gates 103 are both low, the outputs of the two NAND gates 103 are both h
It becomes the high level and does not function as a memory. When an n-type MOS transistor is used for connection with the write bit line, the high level is lowered by the threshold voltage of the n-type MOS transistor, and therefore there is a risk that it will be determined to be a low level and the memory cannot operate. For this reason, the p-type MOS transistor 2 is used as the transistor controlled by the write word line,
It is possible to prevent the gh level from decreasing. That is,
Here, there is a difference that the write word line is normally set to the high level and the write word line is set to the low level when the MOS transistor 2 is turned on, but other operations are the same as those in the second embodiment.

The above contents are related to the structure of the write port portion in the memory cell, and the circuit structure of the read port is irrelevant.

FIG. 5 shows a circuit configuration of a memory cell 100e according to the fourth embodiment in which the configuration of the read port is different from that of the memory cell 100b of the first embodiment.

In the read operation of the memory cell 100e, the read bit line 22 is first precharged to an equal potential such as a high level. Next, the read word line 20 is set to the high level and the memory cell 10
The charge precharged to the write bit line by 0e is extracted. Finally, the sense amplifier reads and outputs the potential change.

In FIG. 6, the NOR gate 102 in the memory cell 100e of the fourth embodiment has three inputs, two inputs of the NOR gates 102 are assigned to two write ports, and a feedback loop is provided with the remaining one input. 9 illustrates a circuit configuration of a formed memory cell 100f according to the fifth embodiment.

In the memory cell 100f having this structure, it is necessary to pay attention to the write operation. That is, at the time of writing, the write word line must be set to low level and the write bit line must be set to low level before turning off the MOS transistor 1. If electric charge remains at the input of the NOR gate 102 that forms the feedback loop of the memory cell 100f and even one is fixed at 1, the output of the NAND gate 102 is fixed at 0, so that an attempt is made to write from another port. This is also because the data value of the memory cell 100f is not rewritten, or the levels of the contacts forming feedback are both zero. First, the MOS transistor 1 whose gate is connected to the write word line is turned on, a write pulse is applied to one of the two pairs of write bit lines, and if the content held in the feedback loop is rewritten, Before the MOS transistor 1 connected to the write word line is turned off, both write bit lines are set to low level. The rising edge of the pulse applied to the write bit line may be before or after the MOS transistor 1 controlled by the write word line is turned on. Also in the case of the fifth embodiment, one contact is not driven by two or more gates during the write operation.

[0040]

As described above, according to the multiport memory circuit of the present invention, since the memory cell is constituted by the NOR gate and the NAND gate, the writing operation is being performed on all the contacts in the memory cell. Since two or more gates are not driven in the memory cell, the collision of the signal level is eliminated at the time of writing the memory cell, the writing speed is improved and the rewriting time of the memory cell is shortened. It is possible to reduce the power consumption by reducing the through current to the. Further, in the multi-port memory circuit of the present invention, the number of bit lines and word lines is large in an actual layout, and the area of the memory cell is determined by these wirings. It has an advantage that the circuit can be configured with almost no appearance in the area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a multiport memory circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a signal change of a memory cell during a write operation in the multiport memory circuit shown in FIG.

FIG. 3 is a circuit diagram showing a memory cell that is a main part configuration of a multi-port memory circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a memory cell that is a main part configuration of a multi-port memory circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a memory cell that is a main part configuration of a multi-port memory circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a memory cell that is a main part configuration of a multi-port memory circuit according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a basic configuration of a conventional multi-port memory circuit.

8 is a timing chart showing a signal change of a memory cell during a write operation in the multi-port memory circuit shown in FIG.

[Explanation of symbols]

 1 MOS Transistor 10,11 Write Word Line 12,13 Write Bit Line 14,15 Write Data Line 20,21 Read Word Line 22,23 Read Bit Line 24 Read Data Line 100a-100f Memory Cell 101 Inverter 102 NOR Gate 103 NAND Gate 104 sense amplifier 105 precharge circuit 106 address decoder

Claims (4)

[Claims] 1. A multi-port memory circuit having a plurality of ports including a read port and an independent write port and including a memory cell, wherein the memory cell is N
A multi-port memory circuit having an OR gate. 2. The multiport memory circuit according to claim 1, wherein the memory cell includes a first NOR gate and a second NOR gate as the NOR gate, and further, the first NOR gate has a first NOR gate. Input the second NOR
Connecting the output of the first NOR gate to the first input of the second NOR gate and connecting the output of the first NOR gate to the second input of the first NOR gate.
And a second input of the NOR gate of the multi-port memory circuit is connected to a bit line through a transistor whose opening / closing is controlled by a word line. 3. In a multi-port memory circuit having a plurality of ports including a read port and an independent write port and including a memory cell, the memory cell is N
A multi-port memory circuit having an AND gate. 4. The multi-port memory circuit according to claim 3, wherein the memory cell is a first NAND gate.
NAND gate and a second NAND gate, the second NAND gate being connected to the first input of the first NAND gate.
The output of the NAND gate of
The output of the first NAND gate is connected to the first input of the AND gate, and the second input of the first NOR gate is connected.
And a second input of the second NAND gate are each connected to a bit line through a transistor whose opening and closing is controlled by a word line.