KR0155924B1 - Bus drive circuit saving bus driver number - Google Patents

Abstract

The present invention relates to a microcomputer bus driver circuit, and more particularly to a circuit for reducing the number of bus drivers. The bus driver circuit reduces the number of bus drivers to reduce the overall chip area and reduces power consumption. The bus driver circuit uses a corresponding internal data bus and one bit line of the data bus as input signals and the bus enable signal as an output control signal. A plurality of logic gate blocks output in exclusive logic; A latch input unit configured to input and output the plurality of logic gate block outputs; A latch unit for inverting the latched output value when the level of the signal output from the latch input unit changes; And an inverter driver for inputting and amplifying the output terminal signal of the latch unit. As described above, by reducing the number of drivers having a large size, the effect of reducing the area of the entire chip can be obtained.

Description

Bus Driver Circuit Reduces Number of Bus Drivers

1 is a circuit diagram showing a conventional microcomputer bus driver.

2 is a circuit diagram showing a bus driver of the microcomputer according to the present invention.

The present invention relates to a microcomputer bus driver circuit, and more particularly to a circuit for reducing the number of bus drivers.

In a semiconductor chip, the bus line is composed of very large capacitance and resistance component, and the bus driver must be largely designed to drive it.

In addition, the more blocks driving the same bus line, the larger the area occupied by the bus driver in the chip as a whole. Therefore, a problem arises in that the size of the chip is increased and the power consumption of the entire chip is also increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a bus drive circuit that reduces the number of bus drivers, reduces the area of the entire chip, and reduces power consumption.

In the bus driver circuit for reducing the area of the entire chip and the power consumption by reducing the number of bus drivers according to the present invention for achieving the above object,

A plurality of logic gate blocks for outputting in an exclusive logic using a corresponding internal data bus and one bit line of the data bus as input signals and a bus enable signal as an output control signal;

A latch unit for inputting and outputting the outputs of the plurality of logic gate blocks:

A latch unit for inverting the latched output value when the level of the signal output from the latch input unit changes; And

And an inverter driver for introducing and amplifying the output terminal signal of the latch unit.

First, the prior art will be described in order to help understanding of the present invention.

1 is a circuit diagram showing a conventional My Firm bus driver.

When the internal block data bus line LDB1 output from one of a plurality of blocks of the microcomputer is at a high level and the bus enable signal ENB1 is at a high level, the NAND gate 120 and the output are at a low level to drive transistors. Turn on (P1).

In addition, the high level of the bus enable signal ENB1 becomes a low level through the inverter 110 and is input to the noar gate 130 together with the high level signal of the LDB1 data. The output of the NOA gate 130 is at a low level and is applied to the gate of the transistor N2 to block the transistor N2.

Accordingly, the conducting transistor P1 drives the voltage level of the power supply Vcc by driving the high level 1 to the 1 bit line 140 of the external data bus.

On the other hand, when the internal block data bus line LDB1 is low level and the bus enable signal ENB1 is high level, the output of the NAND gate 120 becomes high level to block the drive transistor P1.

In addition, the high level of the bus enable signal ENB1 becomes low through the inverter 110 and is input to the noar gate 130 together with the low level signal of the LDB1 data. The output of the NOR gate 130 becomes high level and is applied to the gate of the transistor N2 to conduct the transistor N2.

Accordingly, the conducting transistor N2 drives the low level 0 by connecting the low voltage level of ground to the 1 bit line 140 of the external data bus.

Here, reference numeral 1 denotes one of the blocks for driving one bit line of a plurality of internal data buses, and reference numeral 2 denotes the other one of the blocks for driving one bit line of a plurality of internal data buses.

In addition, when the bus enable signal ENB1 is at a low level, the output of the NAND gate 120 is always at a high level and is applied to the gate of the transistor P1, thereby blocking the transistor P1. In addition, the NOR gate 130 and the output are always at a low level and are applied to the gate of the transistor P1 to thereby block the transistor N2.

Therefore, the one bit line 140 of the data bus connected to the transistor P1 and the transistor N2 is in a high impedance state.

Here, the data bus 150 including the one bit line 140 of the data bus is composed of a very large capacitance and a resistance component. In order to drive the data bus 150, the bus driver must design a large capacity transistor (P1, N2). Is large. In addition, the presence of multiple internal databus drivers that drive one external databus bitline consumes significant chip area and drive power consumption.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing a bus driver of the microcomputer according to the present invention.

The logic gate block 210 is composed of an exclusive ora gate and an end gate, respectively, and enables the corresponding internal data bus by using the output value of the internal data line and the output value of the external data line 300 as the exclusive oan logic (ENB3). And a logic gate block 230 is one of a plurality of logic gate blocks. Reference numeral 310 denotes a data bus composed of each data line.

The logic gate block 210 includes an exclusive oragate 240 and the exclusive ora to inject the data level of the 1-bit line 300 of the external data bus and the signal level of the internal block data bus line bit LDB3. And an AND gate 250 that receives an output signal of the gate 240 and a bus enable signal ENB3 and outputs the AND logic in an AND logic manner.

Also, reference numeral 230 is one of a plurality of logic gate blocks of the internal data bus 1 bit line, which is combined with the logic gate block 210 and is controlled by the bus enable signal ENB4 to control the corresponding internal data bus bit line LDB4. Outputs the data bits of. When the signal level of the external data bus 1 bit line 300 is 0 and the line bit (LDB3) signal level of the internal data bus block is 1, the output of the exclusive oragate 240 becomes 1 to the AND gate 250. Inflow. At this time, if the logic level of the bus enable signal ENB3 is 1, the output value of the AND gate 250 is 1, and the OR gate 250 is the signal level output from a plurality of logic gate blocks including the logic gate block 210. These signals are introduced into the oan logic and applied to the clock terminal CK which is a rising active of the T-flip flop 270.

The T-flip flop 270 enters the output signal of the oragate 260 that transitions from logic level 0 to 1 and toggles the zero value latched at the non-inverter output stage Q to 1. The latched value, toggled to logic 1, is a data logic level 1 with sufficient ampacity driven while passing through a medium first inverter driver 280 and a second large inverter drive 290 to actually drive the bus. Is applied to the external data bus line.

On the other hand, when the signal level of the external data bus bit line 300 is 1 and the line bit (LDB3) signal level of the internal data bus is 1 or both signals are 0, the output of the exclusive oragate 240 is 0. This flows into the end gate 260.

At this time, when the bus enable signal ENB3 becomes high, the output signal of the AND gate 250 becomes 0, and the OR gate 260 is a signal output from a plurality of logic gate blocks including the logic gate block 210. When the levels are introduced and output in a negative logic, the levels are applied to the clock terminal CK, which is the rising active of the T-flip flop 270.

At this time, since the output signal of the oragate 260 applied to the clock terminal of the T-flip flop 270 is not an active condition for transitioning from 0 to 1, the toggle latched to the output terminal of the T-flip flop 270 is It doesn't work.

Therefore, when the logic value of the line bit LDB3 of the internal data bus is the same as the logic value of the corresponding bit line of the external data bus, the data values are driven in the first and second inverter drivers 280 and 290 without being toggled. The data logic level is applied to one bit line 300 of the corresponding external data bus.

Therefore, the logic part of reference numeral 210,230 exists in each block and checks whether the value to be output to the data bus in that block is different from the line bit value of the current data bus to generate a signal, and the T-flip flop (after). 270) Only one external drive line exists in the external data bus bit line, and the data of one enabled block is applied among the signals output from the multiple blocks to set the data bit value of the corresponding line of the current data bus.

The bus driver use portion of each block is replaced with a logic circuit, and only one large driver 290 for driving the bus is finally used.

As described above, by reducing the number of large drivers, it is possible to reduce the area of the entire chip. Since there is only one driver per bit line of the data bus, it is possible to reduce the transition time of the bus line through accurate simulation. This can improve the access speed of the chip.

Claims (5)

In a bus driver circuit that reduces the area of the chip and reduces power consumption by reducing the number of bus drivers, a corresponding internal data bus and one bit line of the data bus are input signals, and the bus enable signal is an output control signal. A plurality of logic gate blocks output to exclusive logic; A latch input unit configured to input and output outputs of the plurality of logic gate blocks; A latch unit for inverting the latched output value when the level of the signal output from the latch input unit changes; And an inverter driver for inputting and amplifying the output terminal signal of the latching unit, thereby reducing the number of bus drivers. 2. The logic gate block of claim 1, wherein the logical gate block is configured to include an exclusive or gate which inputs a bit line of an internal data bus and a corresponding data bit line of an external data bus, an output of the exclusive or gate, and an in of the corresponding bus. Bus drive circuit which reduces the number of bus drivers, characterized in that it includes an AND gate for inputting a single signal and outputting it to AND logic. The bus drive circuit of claim 1, wherein the latch input unit is an ora gate which inputs outputs of the plurality of logic gate blocks and outputs them in ora logic. 2. The bus drive circuit according to claim 1, wherein the latch section is a T-flip flop output when the output of the latch input section rises to toggle the latched data. The bus driver circuit of claim 1, wherein the inverter driver connects a medium-sized inverter and a large-capacity inverter that actually drives the bus in series.