JPH09305534A - Data transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate waiting time for data transfer between CPU and input/ output(I/O) equipment, to improve data transmission efficiency, to accelerate speed and to save memory capacity. SOLUTION: I/O equipment 1 performs the I/O of data. A transfer end detection part 2 detects the transfer end of data. A data buffer 3 stores data from the I/O equipment 1. A RAM 4 stores data. Buffer gates 11 and 12 perform the data bus control of the data buffer 3. Buffer gates 13 and 14 perform the data bus control of the RAM 4. A CPU 5 performs the processing/control of data. A main storage part 6 stores data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer circuit, and more particularly to a data transfer circuit for speeding up data transfer between a central processing unit and an input / output unit by simultaneously performing memory access.

[0002]

2. Description of the Related Art In recent computer equipment, there is an increasing demand for faster data transfer between external input / output equipment (hereinafter referred to as I / O equipment) and central processing equipment (hereinafter referred to as CPU). Is coming.

FIG. 2 is a block diagram showing a conventional data transfer circuit.

The conventional data transfer circuit includes an I / O device 1 for inputting / outputting data, an input / output control unit 15 for controlling input / output of data, a data buffer 20 for temporarily storing data, and a data storage unit. Of random access memory (hereinafter referred to as RAM) 21, buffer gates 18 and 19 for switching data on / off, a CPU 5 for controlling data read / write, and a main memory 6 for storing data. ing.

Next, the operation of transferring data from the I / O device 1 to the main memory 6 will be described.

When data is transferred from the I / O device 1 to the input / output control unit 15, the input / output control unit 15 turns off the buffer gate 18 by the gate control signal 16 to turn off the CPU 5, the main storage unit 6 and the data buffer 20. Separate and. At the same time as this operation, data transfer is started between the input / output control unit 15 and the data buffer 20, and the data of the I / O device 1 is stored in the data buffer 20.

At the same time as the above operation, the input / output control unit 15 turns on the buffer gate 19 by the gate control signal 17 to connect the CPU 5 and the main storage unit 6 to the RAM 21.

Therefore, during this period, the CPU 5 is constantly in the RAM 21.
The data stored in is ready to be read and written.

Next, when the data transfer from the I / O device 1 is completed, the input / output control section 15 detects the end of the data transfer, and contrary to the above operation, this time, the gate control signal 16 causes the buffer gate to operate. 18 is turned on to connect the CPU 5 and the main storage unit 6 to the data buffer 20. That is,
Since the CPU 5 is ready to read and write data from the data buffer 20, the data stored in the data buffer 20 is transferred to the main storage unit 6 by the operation of the CPU 5.

At the same time as the above operation, the input / output control unit 15 turns off the buffer gate 19 by the gate control signal 17 to disconnect the CPU 5, the main storage unit 6 and the RAM 21.

During this time, the RAM 21 is separated not only from the CPU 5 and the main memory 6 but also from the input / output controller 15, so that the read / write operation to the RAM 21 is stopped.

Even if the input / output control unit 15 tries to start the next data transfer, the data buffer 20 cannot store data in the data buffer 20 because it is still accessed by the CPU 5. Further, since the RAM 21 cannot be accessed, the I / O controller 15 keeps the I / O during this period.
Since the data transfer from the O device 1 is temporarily waited, the data transfer efficiency is deteriorated.

It should be noted that I / O from the CPU 5 and the main storage unit 6
Since the data transfer to the O device 1 is the reverse of the above operation,
The description is omitted.

As another example of such a data transfer circuit, a "data transfer circuit" described in Japanese Patent Laid-Open No. 61-288253 is known.

In this publication, data transfer between an input / output device and a main memory is virtually provided with a data buffer and a random access memory as a shared memory area in a memory space of the main memory, and a shared memory is provided by a switching circuit. A technique for allocating an area to a data buffer or a random access memory and performing direct data transfer via this shared memory is described.

[0016]

The above-described conventional data transfer circuit has a C function even if the I / O device finishes transferring the data.
It has a drawback that the next data cannot be transferred until the PU finishes reading the data from the buffer memory.

Further, since the shared memory area is required inside the main memory device, the memory area of the main memory device is reduced.

An object of the present invention is to eliminate the waiting time for data transfer by simultaneously accessing the buffer memory by the CPU or I / O equipment, thereby improving the data transmission efficiency, speeding up and saving the memory area. To provide a data transfer circuit.

[0019]

According to the data transfer circuit of the present invention, data transfer means is provided between the input / output device for inputting / outputting data and the central processing unit and the main storage device. In the data transfer circuit, the data transfer means detects and transfers data from the input / output device, and a transfer detector; and a first storage unit and a second storage unit that store the data alternately. First and second connection switching units that are exclusively connected by control of the transfer detection unit so that the first storage unit can transfer data to either the input / output device or the central processing unit; Third and fourth connections that are exclusively connected under the control of the transfer detection unit so that the second storage unit can transfer data to either the central processing unit or the input / output unit. It is characterized by comprising; a switching unit.

In a data transfer circuit for performing data transfer between an input / output device for inputting / outputting data and a central processing unit and a main memory device by a data transfer means provided therebetween; When the data from the entry output device is input, the first control signal is turned on and the second control signal is turned off, and when the transfer of the data is completed, the first control signal is turned off and the second control signal is turned on. A first storage unit and a second storage unit that alternately store data from the input / output device or the central processing unit; and a first control signal is turned on or off. A first connection switching unit that connects or disconnects the input / output device and the first storage unit; the first storage unit and the central processing unit by an on / off operation of the second control signal; A second connection switching unit for connecting or disconnecting a device; a third connection switching unit for connecting or disconnecting the central processing unit and the second storage unit by turning on or off the first control signal And a fourth connection switching unit that connects or disconnects the second storage unit and the input / output device by turning on or off the second control signal.

Further, the first storage unit and the second storage unit are characterized by being constituted by a random access memory.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the data transfer circuit of the present invention.

In the present embodiment shown in FIG. 1, an I / O device 1 for inputting / outputting data, a transfer end detecting unit 2 for detecting the end of data transfer, and a data buffer 3 for temporarily storing data. A RAM 4 for storing data, and a buffer gate 11 for controlling the data bus of the data buffer 3.
And 12, the buffer gates 13 and 14 for controlling the data bus of the RAM 4, the CPU 5 for controlling the read / write of the data, and the main storage unit 6 for storing the data.

In FIG. 1, components corresponding to those shown in FIG. 2 are designated by the same reference numerals or symbols, and their description will be omitted.

Next, the operation of the present embodiment will be described in more detail with reference to FIG.

Here, the data buffer 3 is the I / O device 1
The case where the RAM 4 operates as a local memory of the CPU and the RAM 4 operates as a memory window on the CPU side will be described.

When data is input from the I / O device 1 to the transfer end detector 2, the transfer end detector 2 turns on the gate control signal 9 and turns off the gate control signal 10. The gate control signal 9 turns on the buffer gate 12 which connects the I / O device 1 and the data buffer 3, and the RAM 4 and the CPU.
The buffer gate 13 connecting with 5 is turned on. On the other hand, the gate control signal 10 turns off the buffer gate 14 connecting the I / O device 1 and the RAM 4, and turns off the buffer gate 11 connecting the data buffer 3 and the CPU 5.

In this state, the I / O device 1 can transfer data to the data buffer 3 via the I / O data bus 8, and the CPU 5 can access the RAM 4 via the CPU data bus 7.

Next, when the data transfer is completed, the transfer end detecting section 2 detects the end of the data transfer, and turns off the gate control signal 9 and turns on the gate control signal 10. The gate control signal 9 turns off the buffer gate 12 that connects the I / O device 1 and the data buffer 3, and turns off the buffer gate 13 that connects the RAM 4 and the CPU 5. On the other hand, the gate control signal 10 turns on the buffer gate 14 that connects the I / O device 1 and the RAM 4, and turns on the data buffer 3 and the CPU.
The buffer gate 11 connecting with 5 is turned on.

In this state, the CPU 5 can access the data buffer 3 storing the transfer data via the CPU data bus 7, and can receive the transfer data. At the same time, the RAM 4 is connected to the I / O device 1, so
The next data transfer becomes possible via the I / O data bus 8. Since the switching control of the data buffer 3 and the RAM 4 is simultaneously performed, the I / O device 1 should transfer the next data to the RAM 4 while the CPU 5 is reading the transfer data stored in the data buffer 3. You can

That is, when the data buffer 3 is accessible by the I / O device 1, the RAM 4 is accessible by the CPU 5, and when the data buffer 3 is accessible by the CPU 5, the RAM 4 is accessed by the I / O device 1. It is accessible, and the CPU 5 and the I / O device 1 can simultaneously access the data buffer 3 or the RAM 4. The data transfer from the CPU 5 to the I / O device 1 is the reverse of the above-mentioned operation, and the description thereof will be omitted.

As described above, since it is not necessary to secure the virtual storage area of the data buffer 3 or the RAM 4 in the main storage unit 6, data can be transferred independently of the main storage unit 6.

[0034]

As described above, the data transfer circuit of the present invention controls the data bus so that the CPU or I / O equipment can simultaneously access the memory.
Since the waiting time for data transfer is not required, it has an effect that the transmission efficiency can be improved and the speed can be increased.
Moreover, since it is not necessary to provide a virtual memory area in the main storage unit, there is an effect that the memory capacity can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer circuit of the present invention.

FIG. 2 is a block diagram showing a conventional data transfer circuit.

[Explanation of symbols]

 1 I / O device 2 Transfer end detection unit 3 Data buffer 4 RAM 5 CPU 6 Main storage unit 7 CPU data bus 8 I / O data bus 9, 10 Gate control signal 11, 12, 13, 14 Buffer gate 15 Input / output control Part 16, 17 Gate control signal 18, 19 Buffer gate 20 Data buffer 21 RAM

Claims (3)

[Claims] 1. A data transfer circuit for performing data transfer between an input / output device for inputting / outputting data and a central processing unit and a main memory device by a data transfer means provided therebetween; said data transfer means A transfer detection unit that detects and transfers data from the input / output device; a first storage unit and a second storage unit that alternately store the data; and the first storage unit is the input / output device or First and second connection switching units that are exclusively connected under the control of the transfer detection unit so that data can be transferred to one of the central processing units; and the second storage unit is the central processing unit or A third and a fourth connection switching unit that are exclusively connected by the control of the transfer detection unit so that data can be transferred to either one of the input / output devices. Transfer circuit. 2. A data transfer circuit for performing data transfer between an input / output device for inputting / outputting data and a central processing unit and a main memory device by a data transfer means provided therebetween; said data transfer means When the data from the input / output device is input, the first control signal is turned on and the second control signal is turned off, and when the data transfer is completed, the first control signal is turned off and the second control signal is turned on. A transfer detection unit for turning on the switch; a first storage unit and a second storage unit for alternately storing data from the input / output device or the central processing unit; turning on or off the first control signal A first connection switching unit that connects or disconnects the input / output device and the first storage unit by an operation; and the first storage unit and the central processing unit by an on / off operation of the second control signal. Second connection switching unit and for connecting or disconnecting the physical device; wherein the on or off operation of the first control signal the central processing device and the second
A third connection switching unit that connects or disconnects with the storage unit of;
And a fourth connection switching unit that connects or disconnects the second storage unit and the input / output device by turning on or off the second control signal. 3. The data transfer circuit according to claim 1, wherein the first storage section and the second storage section are formed of random access memories.