JPH09298247A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fine semiconductor device with unvaried threshold voltage due to existence/absence of stored electrons in a floating gate in an adjacent monolithic cell, and a manufacturing method of the semiconductor device. SOLUTION: A monolithic cell 23 has a floating gate 25 and a control gate 26. A first interlayer insulating film 30 covers a gate electrode 24 in the monolithic cell 23 and another gate electrode 24 in an adjacent monolithic cell 23, and a conductive layer 31 is formed on the first interlayer insulating film 30. Further, a second interlayer insulating film 32 is formed on the conductor layer 31 so as to isolate the monolithic cells 23. The conductive layer 31 blocks an electric force line by electrons stored in the floating gate 25, and reduces the influence of the adjacent monolithic cell 23 on the floating gate 25. This suppresses a change in a threshold voltage and realizes a fine semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a non-volatile memory or the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art As is well known, for example, in a nonvolatile memory of a semiconductor device, a threshold voltage is controlled by accumulating electrons in a floating gate to change the potential of the control gate. The conventional non-volatile memory is configured as shown in the sectional view of FIG. 18, and the semiconductor device 1 shown in FIG.
electrically Erasable Prog
It is a romable ROM).

A semiconductor device 1 is constructed by providing a plurality of single cells 3 on a semiconductor substrate 2, 4 is a gate electrode portion of the single cell 3, 5 is a floating gate, and 6 is a control gate. Is. Further, 7 is a tunnel gate insulating film, 8 is an inter-poly insulating film, 9 is a diffusion layer forming a source / drain formed on the semiconductor substrate 2, and 10 is a gate portion 4 of each single cell 3. Is an interlayer insulating film formed so as to be insulated and separated by providing a predetermined distance therebetween, and 11 is an interlayer insulating film 10.
It is a bit line formed above.

In the semiconductor device 1, first, the tunnel gate insulating film 7, the floating gate 5, the inter-poly insulating film 8 and the control gate 6 of each single cell 3 are sequentially laminated at a predetermined position on the semiconductor substrate 2 to form a gate portion. 4 are formed, and a diffusion layer 9 is formed between the gate electrode portions 4 of the single cells 3 on the semiconductor substrate 2. After that, an interlayer insulating film 10 is formed by a CVD method so as to cover the single cell 3, and a metal film is deposited on the interlayer insulating film 10 to form the bit line 1.
Form one.

In the semiconductor device 1 thus constructed,
The potential of the control gate 6 is changed depending on whether or not the floating gate 5 is made to store electrons.
This controls the threshold voltage. When the individual cells 3 are formed in a state where they are sufficiently separated from each other and the distance between the gate portions 4 of the single cells 3 is sufficiently large, they are accumulated in the floating gate 5 of the single cell 3. The influence of the electric field due to the electrons on the adjacent single cell 3 is small.

That is, normally, the floating gate 5
The electric field due to the electrons accumulated in is strong on the side of the tunnel gate insulating film 7 and the inter-poly insulating film 8, and the electric field leaking laterally from the side surface is weak. In such a state, the influence of the charges of the adjacent single cell 3 can be ignored. That is,
Capacitance C between the floating gate 5 and the semiconductor substrate 2
s, the electrostatic capacitance Cc between the floating gate 5 and the control gate 6, and the electrostatic capacitance Cn between the floating gates 5 of the adjacent unit cells 3, Cs ≧ Cc >>>>
As long as the relationship of Cn is established, the influence on the adjacent single cell 3 can be ignored.

However, as the semiconductor device 1 is required to be highly integrated and miniaturization progresses, it becomes impossible to form the individual cells 3 in a state where they are sufficiently separated from each other, whereby the distance between the individual cells 3 becomes small. It becomes smaller and the adjacent gate electrode portions 4 become closer to each other. Then, the distance between the adjacent gate electrode portions 4 decreases, and the distance between the adjacent single cell 3 is inversely proportional to the floating gate 5.
The capacitance Cn between the floating gates 5 that increases in proportion to the thickness of the abruptly increases. Such capacitance C
When the electric field formed by the electrons accumulated in the floating gate 5 cannot be ignored due to the increase of n, the threshold voltage depends on whether the electrons are injected into the floating gate 5 of the adjacent single cell 3. Will change.

That is, as shown in the schematic view of FIG. 19 in which electrons are accumulated in the floating gate 5, the lines of electric force F are formed so as to be concentrated around the floating gate 5 in which electrons are accumulated. . Among those formed in this way, the lines of electric force F formed on the side surface of the floating gate 5 reach the adjacent floating gate 5 when the distance is small.

The problem that the threshold voltage changes depending on whether or not electrons are stored in the floating gates 5 of the adjacent single cells 3 is common to all of the ones in which electrons (charges) are stored in the floating gate 5. In the semiconductor device 1 in which the single cells 3 having the floating gates 5 are provided adjacent to each other, this is a major obstacle to further miniaturization.

[0010]

In a semiconductor device having a plurality of unit cells each having a floating gate as described above, when the structure is miniaturized and the distance between adjacent unit cells is small, an electron is applied to the floating gate. The influence on the floating gates of the adjacent single cells due to the accumulation of electrons, and the threshold voltage changes depending on whether or not electrons are accumulated on the floating gates of the adjacent single cells. The present invention has been made in view of such circumstances, and an object of the present invention is to reduce the influence of floating gates in which electrons of adjacent single cells are accumulated and to suppress a change in threshold voltage. An object of the present invention is to provide a semiconductor device that can be miniaturized and a manufacturing method thereof.

[0011]

A semiconductor device and a method of manufacturing the same according to the present invention include a unit cell having a floating gate and a control gate, and an interlayer insulating film covering the unit cell so as to separate the unit cell from an adjacent unit cell. A semiconductor device provided with at least one conductor layer provided in an interlayer insulating film so as to cover a gate electrode portion of a single cell, and a single device having a floating gate and a control gate. Cells and
In a semiconductor device including an interlayer insulating film that covers this single cell so as to separate it from an adjacent single cell, at least 1 layer is formed in the interlayer insulating film so as to cover the gate electrode portion of the single cell.
A device characterized in that it is provided with two conductor layers and that the conductor layers have more free carriers than electrons stored in the floating gate. A device characterized by being electrically connected to a conductor portion or semiconductor portion having more free carriers than stored electrons, wherein the conductor layer is at least below the upper surface position of the floating gate. The device is characterized in that the conductor layer is formed in a position on the side,
A device characterized by being formed of silicon to which a dopant is added, and further characterized in that the dopant is any one of phosphorus, arsenic and boron. A conductor layer is formed of silicide, and the first and second floating gates are formed over the semiconductor substrate and then cover the control gate and the floating gate. A method comprising a step of forming an interlayer insulating film, a step of laminating a conductor layer on the surface of the first interlayer insulating film, and a step of laminating a second interlayer insulating film on the surface of the conductor layer, Furthermore, the first
The method is characterized in that the conductor layer laminated on the surface of the second interlayer insulating film is selectively removed before the second interlayer insulating film is laminated, and the conductor layer is floated above the semiconductor substrate. A step of forming a first interlayer insulating film so as to cover the control gate and the floating gate after forming the gate and the control gate, and a step of forming a dopant-free polycrystalline silicon or amorphous silicon on the surface of the first interlayer insulating film. A step of stacking the deposited film, a step of stacking a second interlayer insulating film containing a dopant on the surface of the deposited film, and a step of performing heat treatment to thermally diffuse the dopant of the second interlayer insulating film into the deposited film. It ’s a prepared method,
The method is characterized in that the second interlayer insulating film is formed of any one of PSG, BPSG, and AsSG.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. 1 is a sectional view, FIG. 2 is a sectional view of a first step, FIG. 3 is a sectional view of a second step,
4 is a sectional view of the third step, FIG. 5 is a sectional view of the fourth step, FIG. 6 is a sectional view of the fifth step, and FIG.
FIG. 8 is a schematic diagram showing a state where electrons are accumulated in the floating gate, and FIG. 8 is a characteristic diagram of threshold voltage with respect to a distance between unit cells.

In FIG. 1, reference numeral 21 is a NAND type EEPR.
An OM semiconductor device, which is configured such that a predetermined separation distance L is provided between adjacent ones of a plurality of single cells 23 on a P well 22 of an N-type semiconductor substrate,
Reference numeral 24 is a gate electrode portion in these unit cells 23. The gate electrode portion 24 has a floating gate 25 and a control gate 26 formed of polysilicon.
Is provided, and silicon oxide (SiO ₂ ) is provided between the upper surface of the P well 22 of the semiconductor substrate and the floating gate 25.
The tunnel gate insulating film 27 having a thickness of about 10 nm formed between the floating gate 25 and the control gate 26, and the inter-poly insulating film 28 having a thickness of about 20 nm formed of silicon oxide. It is provided. Further, an N-type diffusion layer 29 forming a source / drain is formed between the adjacent single cells 23 on the upper part of the semiconductor substrate 22.

Then, the upper surface and the side surfaces of the gate electrode portions 24 of the single cells 23 formed in plural on the P well 22 of the semiconductor substrate are covered with a film thickness of a predetermined thickness or more so as to follow the shape of the gate electrode portions 24. A first interlayer insulating film 30 made of silicon oxide is provided so as to insulate and separate each gate electrode portion 24. Further, on the first interlayer insulating film 30 thus formed, the conductor layer 31 made of silicon containing phosphorus is formed on the first interlayer insulating film 30 except the gate electrode lead-out portion (not shown). The floating gate 25 is formed so as to cover a position below the upper surface of the floating gate 25 with the insulating film 30 interposed therebetween.

In this way, the layer thickness of the conductor layer 31 covering the gate electrode portion 24 is several tens of nanometers when the distance L between the adjacent unit cells 23 is about 0.5 μm or less.
m. Further, the conductor layer 31 is formed to be large enough to have more free carriers than electrons stored in the floating gate 25.

A relatively thick second interlayer insulating film 32 made of silicon oxide is provided on the conductor layer 31 so as to fill up the irregularities around the gate electrode portion 24. Wirings such as bit lines 33 formed by depositing aluminum or the like and patterning are provided on the second interlayer insulating film 32. The conductor layer 31 is made of a material having conductivity such as silicon containing arsenic or boron as a dopant, silicide such as tungsten silicide or molybdenum silicide in addition to silicon containing phosphorus as a dopant. May be. Reference numeral 34 is a contact for the bit line 33.

Further, the semiconductor device 21 having the above structure is formed through the following manufacturing steps. That is, the first shown in FIG.
In the step of, the P formed on the N-type semiconductor substrate is formed.
A silicon oxide film forming a tunnel gate insulating film 27 having a thickness of about 10 nm is formed on the well 22 by thermal oxidation, and is formed on the silicon oxide film by the CVD method (Chemi).
A polysilicon layer forming the floating gate 25 is laminated by a cal vapor deposition method).

Subsequently, the upper portion of the polysilicon layer is thermally oxidized to form a silicon oxide film forming an inter-poly insulating film 28 having a thickness of about 20 nm on the upper portion of the layer, and the silicon oxide film is controlled by the CVD method on the silicon oxide film. A polysilicon layer forming the gate 26 is laminated. After that, a photoresist is applied on the upper surface of the uppermost polysilicon layer, and PEP is applied.
(Photo Engraving Process)
Then, the silicon oxide film and the polysilicon layer on the P well 22 of the semiconductor substrate are etched, and the photoresist is removed to provide the gate electrode portion 24 of the unit cell 23 at a predetermined position on the P well 22 of the semiconductor substrate.

Next, in the second step shown in FIG. 3, using the portion patterned so as to provide the gate electrode portion 24 in the previous step, impurities are ion-implanted on the exposed upper portion of the P well 22 of the semiconductor substrate. Implanting, thereby forming an N-type diffusion layer 29 on the P well 22 between the adjacent gate electrode portions 24 to form a unit cell 23. Subsequently, the upper surface of the diffusion layer 29 of the P well 22 of the semiconductor substrate and the upper surface and side surfaces of the gate electrode portion 24 are covered with a thickness equal to or more than a predetermined thickness so as to follow the shape of the gate electrode portion 24. The first interlayer insulating film 30 is formed by the CVD method.

Next, in the third step shown in FIG. 4, a step by a CVD method is formed on the first interlayer insulating film 30.
Conductor layer 31 is formed by depositing silicon to which phosphorus has been added so as to be deposited by cover coverage. The formed conductor layer 31 has a layer thickness
For example, the separation distance L between the adjacent single cells 23 is 0.5 μ.
If the thickness is about m or less, it is formed to about several tens of nm. The floating gate 2 of the gate electrode portion 24
5, the side surface portion below the upper surface thereof is also covered with the conductor layer 31 via the first interlayer insulating film 30.

Next, in a fourth step shown in FIG. 5, a photoresist is applied on the upper surface of the conductor layer 31, and a mask 34 having a predetermined pattern of the photoresist on the conductor layer 31 is formed by PEP. Then, using the mask 34, the portion of the gate electrode portion 24 of the conductor layer 31 that extends laterally along the surface of the P well 22 of the semiconductor substrate below the upper surface of the floating gate 25 is selectively etched. To remove. It should be noted that a predetermined portion of the conductor layer 31 is selectively etched and removed also in a gate electrode extraction portion and the like (not shown).

Next, in a fifth step shown in FIG. 6, after the photoresist mask 34 is removed, the first interlayer insulating film 30 on the conductor layer 31 and on the conductor layer 31 is selectively etched and removed. A second interlayer insulating film 32 made of a relatively thick silicon oxide having a thickness equal to or larger than a predetermined film thickness that is thicker than the first interlayer insulating film 30 is formed thereon by a CVD method.

After the second interlayer insulating film 32 is formed, a metal film such as aluminum is deposited on the second interlayer insulating film 32 by a vapor deposition method, and the deposited metal film is patterned to form a bit. Wiring such as the line 33 is provided.

The semiconductor device 2 configured as described above
In No. 1, when the electrons are injected into the floating gate 25 of one of the plurality of single cells 23 by operating this, as shown in the schematic diagram of the state in which the electrons are accumulated in FIG. F is formed so as to concentrate around the floating gate 25 in which electrons are accumulated. Regarding the electric field lines F formed on the side surface of the floating gate 25, electric charges are induced in the conductor layer 31 provided so as to cover the gate electrode portion 24, and the conductor layer 31 is formed. The leakage of the lines of electric force F to the outside is extremely reduced. Thus, the leakage of the lines of electric force F is reduced, so that the floating gates 25 of the adjacent gate electrode portions 24 are cut off from each other and have no influence.

As a result, as shown in the characteristic diagram of FIG. 8 in which the abscissa indicates the separation distance L between the unit cells 23 and the ordinate indicates the threshold voltage E, the conventional conductor layer is not provided. When the separation distance L becomes smaller, the threshold voltage E sharply decreases when the separation distance L becomes a certain value La or less as shown by the characteristic curve A shown by the solid line, whereas in the present embodiment in which the conductor layer 31 is provided. In the case where the distance L is small, the threshold voltage E hardly changes as shown by the characteristic curve B shown by the dotted line, and there is no critical distance L at which the threshold voltage E sharply decreases. That is, even if the distance L is reduced, the threshold voltage E of the adjacent single cell 23 is hardly affected. Therefore, the semiconductor device 21 can be made highly integrated by miniaturizing the single cells 23 and narrowing the separation distance L between the adjacent single cells 23.

In the above embodiment, when the conductor layer 31 made of silicon containing phosphorus was formed, the layer was formed by depositing silicon containing phosphorus as a dopant in advance. As a method of forming the above, first, silicon containing no dopant is first deposited on the first interlayer insulating film 30 so as to have a predetermined thickness, and after the deposition, phosphorus as a dopant is deposited on the silicon layered by ion implantation. The conductor layer 31 may be formed so as to be introduced.

Alternatively, silicon containing no dopant is first deposited on the first interlayer insulating film 30 to have a predetermined thickness, and the second interlayer insulating film 32 made of silicon oxide is formed on the deposited layer. Instead of PSG (Phosp
ho-Silicate Glass), BPSG (B
oron-doped Phospho-Silica
te Glass), AsSG (Arsenic-Si)
Ligate Glass) is deposited by low-temperature vapor deposition to a predetermined thickness, and in the heat treatment process of the manufacturing process that is performed later, the silicon containing no dopant is included in PSG, BPSG, AsSG, or the like. The conductor layer 31 may be formed by thermally diffusing the dopant.

Next, a second embodiment will be described with reference to FIGS. 9 to 17. FIG. 9 is a sectional view of the first step,
10 is a sectional view of the second step, FIG. 11 is a sectional view of the third step, FIG. 12 is a sectional view of the fourth step, and FIG. 13 is a sectional view of the fifth step. Yes, FIG. 14 is the sixth
15 is a sectional view of the seventh step, FIG. 16 is a sectional view of the eighth step, and FIG. 17 is a sectional view of the ninth step.

Then, the manufacturing process of the semiconductor device according to the second embodiment is as follows. Note that the first step shown in FIG. 9 to the third step shown in FIG. 11 are the same as the first step shown in FIG. 2 of the above first embodiment to the third step shown in FIG. To be done.

First, in the first step shown in FIG.
A silicon oxide film is formed on the P-well 22 of the semiconductor substrate by thermal oxidation to form a tunnel gate insulating film 27 having a thickness of about 10 nm, and a polysilicon film forming a floating gate 25 is formed on the silicon oxide film by a CVD method. Laminate a silicon layer. Then, 20 nm on the polysilicon layer
A silicon oxide film is formed by thermal oxidation to form an inter-poly insulating film 28 having a certain thickness, and a polysilicon layer forming the control gate 26 is laminated on this silicon oxide film by the CVD method. After that, a photoresist is applied to the upper surface of the uppermost polysilicon layer, the silicon oxide film and the polysilicon layer on the P well 22 of the semiconductor substrate are etched by PEP, and the photoresist is removed to remove the photoresist on the P well 22. The gate electrode portion 24 of the unit cell 23 is provided at a predetermined position.

Next, in the second step shown in FIG.
An impurity is implanted into the upper portion of the exposed P well 22 by an ion implantation method by using a portion patterned so as to provide the gate electrode portion 24 in the previous step, whereby the P well 22 of the semiconductor substrate between the adjacent gate electrode portions 24 is formed. The N-type diffusion layer 29 is formed on the upper portion to form the unit cell 23.
Subsequently, the upper surface of the diffusion layer 29 of the P well 22 of the semiconductor substrate and the upper surface and the side surface of the gate electrode portion 24 are covered with a film thickness of a predetermined thickness or more so as to follow the shape of the gate electrode portion 24. The first interlayer insulating film 30 is formed by the CVD method.

Next, in the third step shown in FIG.
By depositing by step coverage by the CVD method, phosphorus-doped silicon is layered on the first interlayer insulating film 30 to form a conductor layer 41. The formed conductor layer 41 has a layer thickness of, for example, about several tens nm when the separation distance L between the adjacent single cells 23 is about 0.5 μm or less. Further, the floating gate 25 of the gate electrode portion 24 is also covered with the conductor layer 41 via the first interlayer insulating film 30 also on the side surface portion below the upper surface thereof.

Next, in the fourth step shown in FIG.
A second interlayer insulating film 42 made of silicon oxide, which is thicker than the first interlayer insulating film 30 and is thicker than a predetermined thickness, is formed on the conductor layer 41 by a CVD method.

Next, in the fifth step shown in FIG.
The conductor layer 4 covering the control gate 26 of the gate electrode portion 24 by polishing or gas etching.
The second interlayer insulating film 42 is removed from above so that the upper surface of 1 is exposed.

Next, in the sixth step shown in FIG.
The conductor layer 41 is etched to remove the conductor layer 41 in the portion along the side surface of the gate electrode portion 24 from the exposed portion above the control gate 26 to the middle of the thickness of the inter-poly insulating film 28, thereby floating. Gate 2
The conductor layer 41 is left in a portion below the upper surface of the conductor 5.

The layer thickness of the conductor layer 41 left so as to surround the lower portion of the gate electrode portion 24 is, for example, when the separation distance L between the adjacent unit cells 23 is about 0.5 μm or less. It is formed with a thickness of several tens of nm. Further, the conductor layer 41 is formed to be large enough to have more free carriers than electrons stored in the floating gate 25.

Next, in the seventh step shown in FIG.
The photoresist is used to remove the conductor layer 41 from the upper surface of the first interlayer insulating film 30 above the control gate 26 and the second layer.
Is applied so as to fill the upper surface of the interlayer insulating film 42 and the groove-shaped portion between the two interlayer insulating films 30 and 42 from which the conductor layer 41 is removed, and a mask 43 having a predetermined pattern of photoresist is formed by PEP. . And the mask 43
Using, the portions of the second interlayer insulating film 42 and the conductor layer 41 that extend laterally along the surface of the P well 22 of the semiconductor substrate are selectively etched and removed. It should be noted that a gate electrode lead-out portion and the like (not shown) are also selectively etched and removed at predetermined portions of the conductor layer 41.

Next, in the eighth step shown in FIG.
After removing the photoresist mask 43, the exposed first interlayer insulating film 30 and the second interlayer insulating film 42 are covered, and the groove portion between the interlayer insulating films 30 and 42 in which the conductor layer 41 is removed A third interlayer insulating film 44 made of silicon oxide having a relatively thick predetermined film thickness or more is formed by a CVD method so as to completely fill the above.

Thereafter, a metal film of aluminum or the like is deposited on the third interlayer insulating film 44 by a vapor deposition method, and the deposited metal film is patterned to provide wirings such as the bit line 33 and the semiconductor device 45. To form.

The semiconductor device 4 configured as described above
In Example 5, since the side surface portion below the upper surface of the floating gate 25 is surrounded by the conductor layer 41, the same operation and effect as those of the first embodiment can be obtained, and the conductor layer covering the control gate 26 is obtained. Because there is no 41,
Even if a high voltage is applied to the control gate 26, a high electric field is generated between the control gate 26 and the conductor layer 41, a leak current flows, and the operation of the semiconductor device 45 is not impaired. Further, there is no possibility that the electrostatic capacitance between the control gate 26 and the conductor layer 41 covering the control gate 26 becomes large and the operating speed is deteriorated.

In each of the above embodiments, the conductor layer 3
1 and 41 are sized so as to have more free carriers than electrons stored in the floating gate 25, but conductor portions (not shown) further having more free carriers than electrons stored in the floating gate 25. Alternatively, it may be electrically connected to the semiconductor portion or the like.

[0043]

As is apparent from the above description, according to the present invention, a gate electrode portion of a single cell having a floating gate and a control gate and a gate electrode portion of an adjacent single cell are provided in a conductor layer in an interlayer insulating film. By providing the above structure and separating the structure, it is possible to reduce the influence of the floating gate in which the electrons of the adjacent single cells are accumulated, suppress the change in the threshold voltage, and enable the miniaturization of the device. Produce the effect of.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view of a first step according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a second step according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a third step according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a fourth step according to the first embodiment of the present invention.

FIG. 6 is a sectional view of a fifth step according to the first embodiment of the present invention.

FIG. 7 is a schematic diagram showing a state in which electrons are accumulated in a floating gate according to the first embodiment of the present invention.

FIG. 8 is a characteristic diagram of a threshold voltage with respect to a separation distance between single cells according to the first embodiment of the present invention.

FIG. 9 is a sectional view of a first step according to the second embodiment of the present invention.

FIG. 10 is a sectional view of a second step according to the second embodiment of the present invention.

FIG. 11 is a sectional view of a third step according to the second embodiment of the present invention.

FIG. 12 is a sectional view of a fourth step according to the second embodiment of the present invention.

FIG. 13 is a sectional view of a fifth step according to the second embodiment of the present invention.

FIG. 14 is a sectional view of a sixth step according to the second embodiment of the present invention.

FIG. 15 is a sectional view of a seventh step according to the second embodiment of the present invention.

FIG. 16 is a sectional view of an eighth step according to the second embodiment of the present invention.

FIG. 17 is a sectional view of a ninth step according to the second embodiment of the present invention.

FIG. 18 is a sectional view showing a conventional example.

FIG. 19 is a schematic diagram showing a state in which electrons are accumulated in a floating gate in a conventional example.

[Explanation of symbols]

 23 ... Single cell 24 ... Gate electrode part 25 ... Floating gate 26 ... Control gate 27 ... Tunnel gate insulating film 28 ... Inter Poly insulating film 30 ... First interlayer insulating film 31, 41 ... Conductor layer 32, 42 ... Second Interlayer insulating film 44 ... Third interlayer insulating film

Claims (11)

[Claims] 1. A semiconductor device comprising a unit cell having a floating gate and a control gate, and an interlayer insulating film covering the unit cell so as to separate the unit cell from an adjacent unit cell, wherein the unit cell is provided in the interlayer insulating film. At least one conductor layer is provided so as to cover the gate electrode part of the semiconductor device. 2. A semiconductor device comprising a single cell having a floating gate and a control gate, and an interlayer insulating film covering the single cell so as to separate the single cell from an adjacent single cell, wherein the single cell is provided in the interlayer insulating film. At least one conductor layer is provided so as to cover the gate electrode part of the semiconductor device, and the conductor layer has more free carriers than electrons accumulated in the floating gate. . 3. The semiconductor device according to claim 2, wherein the conductor layer is electrically connected to a conductor portion or a semiconductor portion having more free carriers than electrons accumulated in the floating gate. . 4. The semiconductor device according to claim 1, wherein the conductor layer is formed at a position at least below the upper surface of the floating gate. 5. The semiconductor device according to claim 1 or 2, wherein the conductor layer is formed of silicon to which a dopant is added. 6. The semiconductor device according to claim 5, wherein the dopant is one of phosphorus, arsenic and boron. 7. The semiconductor device according to claim 1, wherein the conductor layer is formed of silicide. 8. A step of forming a floating gate and a control gate above a semiconductor substrate and then forming a first interlayer insulating film so as to cover the control gate and the floating gate, and a step of forming the first interlayer insulating film. A method of manufacturing a semiconductor device, comprising: a step of laminating a conductor layer on the surface; and a step of laminating a second interlayer insulating film on the surface of the conductor layer. 9. The conductor layer laminated on the surface of the first interlayer insulating film is selectively removed before laminating the second interlayer insulating film. Manufacturing method of semiconductor device. 10. A step of forming a floating gate and a control gate above a semiconductor substrate and then forming a first interlayer insulating film so as to cover the control gate and the floating gate, and a step of forming the first interlayer insulating film. A step of laminating a deposited film of polycrystalline silicon or amorphous silicon with no dopant on the surface; a step of laminating a second interlayer insulating film containing a dopant on the surface of the deposited film; And a step of thermally diffusing the dopant of the interlayer insulating film into the deposited film. 11. The second interlayer insulating film is PSG or BPS.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is formed of any one of G and AsSG.