JPH1174388A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of the thickness of both end parts of the first and second conductor films of a semiconductor device, and a dielectric film in a capacity part held between them. SOLUTION: On a P type silicon substrate 1, a gate insulation film 10 composed of a silicon oxide film and a floating gate electrode 11 composed of a polysilicon film are successively formed. On the floating gate electrode 11, a capacity insulation film 12 composed of the silicon oxide film and a control gate electrode 13 composed of the polysilicon film are formed. Further, a first spacer film 14 composed of the silicon oxide film formed on the side face of respective members 11, 12 and 13, and a second spacer film 15 composed of a silicon nitride film formed on the first spacer film 14, are provided. Even when high temperature heat treatment is executed under an oxidation atmosphere, the supply of oxygen to both end parts of the capacity insulation film 12 and the control gate electrode 13 is obstructed, and the increase of the thickness of both end parts of the capacity insulation film 12 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a capacitance portion composed of two conductor layers and a capacitance insulating film sandwiched between the two conductor layers, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor device having a capacitance portion composed of two conductor layers in a semiconductor element and a capacitance insulating film sandwiched between the two conductor layers, a semiconductor device, a gate electrode, and a gate insulating film are used. Dynamic RAM (Random Access Memory) including a storage transistor including a MOS transistor including a storage capacitor, a storage node, a cell plate, and a capacitor insulating film.
ry), and a floating gate type EEPROM (Electrically) provided with a storage capacitance portion composed of a floating gate, a control gate, and a capacitance insulating film.
Erasable and Programmable
e Read Only Memory), a capacitor disposed in an analog circuit, and the like are well known.

FIG. 11 is a sectional view of a conventional floating gate type EEPROM. As shown in FIG. 1, a tunnel insulating film 110, a floating gate electrode 111, a capacitor insulating film 112, and a control gate electrode 113 are provided on a semiconductor substrate 101. Electrode 111
Source region 108 and drain region 10 that are self-aligned
9 are formed. Here, the floating gate electrode 111, the capacitance insulating film 112, and the control gate electrode 11
3 constitutes a capacitive coupling unit. By applying a control voltage to the control electrode 113, the capacitive coupling portion is connected to the capacitively coupled floating gate electrode 1.
It has a function of injecting and extracting electrons in the semiconductor device 11.

In a semiconductor device including a capacitor having such a capacitor insulating film, a single-layer silicon oxide film, a silicon nitride film having a large dielectric constant, or the like is usually used as the capacitor insulating film. The capacitor insulating film 112 illustrated in FIG. 11 includes a silicon nitride film-based insulating film, for example, a two-layer film (ON film) of a silicon nitride film-a silicon oxide film, a silicon oxide film-a silicon nitride film-a silicon oxide film. A three-layer film (ONO film) is often used. Furthermore, particularly in MOS transistors and the like, oxynitride films have been used.

In general, two polysilicon films having a high melting point are used as the two conductor layers. For example, the floating gate electrode and the control electrode 113 of the EEPROM shown in FIG. 11 are generally formed of a polysilicon film.

On the other hand, with the recent increase in the degree of integration of semiconductor integrated circuits, demands for miniaturization and lowering the voltage of semiconductor devices including the above-described capacitance section have been increasing.
There is an increasing demand for a semiconductor device having a capacitor having a typical size of 0.5 μm (half micron) or less. Therefore, each gate electrode 111, 1 shown in FIG.
Twelve gate lengths also tend to be miniaturized.

[0007]

However, in a semiconductor device having a capacitance portion having a size of half a micron or less, the lateral dimensions of the conductor layers above and below the capacitance portion and the floating gate of the floating gate type semiconductor memory device are not considered. If the lateral dimension of the electrode or control gate electrode is 0.5 μm or less, for example, a phenomenon in which the film thickness of the capacitor insulating film 112 shown in FIG. For this reason, the capacitance between the floating gate electrode 111 and the control gate electrode 113 is reduced, and it becomes difficult to secure a predetermined capacitance value required for exhibiting the original memory characteristics. Have been. It is considered that such non-uniformity of the film thickness is caused by the following causes.

That is, usually, after the floating gate electrode 111, the capacitor insulating film 112, and the control gate electrode 113 shown in FIG. 11 are formed by patterning, impurity ions are implanted into the semiconductor substrate 101 by using these as a mask to form a source. A region 108 and a drain region 109 are formed. At this time, heat treatment is performed in an oxidizing atmosphere at a high temperature of 800 to 1000 ° C. in order to activate the impurities and generate carriers, and the heat treatment increases the thickness of both ends of the capacitor insulating film 112. A phenomenon occurs. In other words, when the size of the floating gate electrode 1 is smaller than half microns,
Since the capacitor insulating film 112 sandwiched between the capacitor 11 and the control gate electrode 113 is rapidly oxidized from both sides, the thickness of the capacitor insulating film 112 is significantly different between the center and the periphery.

According to the study by the present inventors, each electrode 1
It has been found that when the electrodes 11 and 113 are made of a polysilicon film, the oxidation is rapidly accelerated when the dimensions of the electrodes become 0.4 μm or less. This is considered to be due to the accelerated oxidation of the polysilicon film sandwiching the capacitive insulating film.

As a result, in the conventional floating gate type semiconductor memory device, the control gate electrode 1
With the reduction of the voltage applied to the switch 13, the required capacity coupling ratio cannot be secured, and the characteristics such as writing and erasing speeds are degraded, and a sufficient read current cannot be secured. Also, in other types of semiconductor devices, there is a possibility that a problem in characteristics due to deterioration of the capacitance value of the capacitance portion or the like may occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object of the present invention is to suppress an increase in the thickness at both ends of a capacitive insulating film even when the lateral dimension is reduced to half a micron or less. It is an object of the present invention to provide a semiconductor device having a capacitance portion having a small variation in the thickness of a capacitance insulating film and a method of manufacturing the same by taking measures.

[0012]

In order to achieve the above object, the present invention provides means relating to a first semiconductor device, means relating to a second semiconductor device, and means relating to a method of manufacturing a semiconductor device. I have.

A first semiconductor device according to the present invention comprises a semiconductor substrate, a first conductive film provided on the semiconductor substrate, and a dielectric material provided on the first conductive film and containing an oxidizing material. A film, a second conductor film provided on the dielectric film,
A first spacer film made of an oxide film covering side surfaces of the first conductor film, the dielectric film, and the second conductor film; and a second spacer covering the first spacer film and having a function of preventing passage of oxygen. And a membrane.

Thus, even if the semiconductor device is subjected to a heat treatment in an oxygen atmosphere, both end portions of the dielectric film and the first and second portions adjacent thereto are formed by the second spacer film having an oxygen passage preventing function. Passage of oxygen to the conductor film is suppressed. Therefore, an increase in the thickness of both ends of the dielectric film is suppressed,
A decrease in capacitance between the first conductor film and the second conductor film is suppressed. Further, even when the insulating function of the second spacer film is low, since the first spacer film made of an oxide film having a high insulating function is provided, the first spacer film between the first conductive film and the second conductive film is provided. Generation of a leak current can be prevented.

[0015] In the first semiconductor device, the semiconductor device may include a gate insulating film provided on a semiconductor substrate;
A non-volatile semiconductor comprising: a floating gate electrode provided on the gate insulating film; a capacitive insulating film provided on the floating gate electrode; and a control gate electrode provided on the capacitive insulating film. In the storage device, the first conductive film may be the floating gate electrode, the dielectric film may be the capacitance insulating film, and the second conductive film may be the control gate electrode.

As a result, it is possible to obtain a semiconductor device which can operate at a high capacitance coupling ratio, that is, at a low voltage, and which functions as a floating gate type semiconductor memory device in which writing and erasing operations are performed at high speed.

In the first semiconductor device, the second semiconductor device
Further comprising a conductor portion protective film provided on the conductor film of
The first spacer film can be extended to the side surface of the conductor portion protective film.

In the first semiconductor device, when the conductor portion protective film is formed of an oxide film, the upper end of the first spacer film is positioned at a position higher than the height of the upper surface of the conductor portion protective film. Is also preferably reduced.

Thus, the contact area between the conductor protection film and the first spacer film, both of which are formed of oxide films, can be reduced as much as possible. -The amount of oxygen supplied to the dielectric film via the first spacer film can be suppressed, and an increase in the thickness of both ends of the dielectric film can be suppressed.

In the first semiconductor device, the conductor protection film may be a first conductor protection film made of an oxide film and an oxygen blocking function provided on the first conductor protection film. In the case where the first spacer film is constituted by the second conductor portion protective film, it is more preferable that the first spacer film extends to the side surfaces of the first conductor portion protective film and the second conductor portion protective film. .

As a result, the oxide film is not exposed on the surface even if the contact area between the first conductor portion protective film and the first spacer film, both of which are composed of oxide films, is large.
In the heat treatment step of the semiconductor device in an oxidizing atmosphere, the amount of oxygen supplied to the dielectric film via the conductor portion protective film and the first spacer film can be more reliably suppressed, and the thickness of both ends of the dielectric film increases. Can be suppressed.

In the first semiconductor device, the second semiconductor device
Can be made of a film containing silicon nitride.

In the first semiconductor device, the first and second spacer films are provided so as to cover the entire upper surface and both side surfaces of the first conductor film, the dielectric film, and the second conductor film. May be.

In the first semiconductor device, the second semiconductor device
May be a film containing oxynitride.

According to a second semiconductor device of the present invention, there is provided a semiconductor substrate, a gate insulating film provided on the semiconductor substrate,
A floating gate electrode provided on the gate insulating film, a capacitor insulating film made of a dielectric film provided on the floating gate electrode, and a control gate electrode formed on the capacitor insulating film; A tunnel insulating film formed on the side surface or a part of the side surface and the surface of the floating gate electrode; an erase gate electrode opposed to the floating gate electrode with the tunnel insulating film interposed therebetween; A spacer film provided on the side surface of the film and having a function of blocking oxygen passage.

Thus, in the heat treatment in an oxidizing atmosphere required for forming a tunnel insulating film composed of an oxide film interposed between the erase gate electrode and the floating gate electrode, both ends of the capacitive insulating film are separated by the spacer film. Since it is covered, it is possible to suppress an increase in the thickness at both ends of the capacitor insulating film. Therefore, a semiconductor device having a high capacitance coupling ratio, that is, a semiconductor device functioning as a floating gate type semiconductor memory device with an erase gate electrode having high write and erase operations at a low voltage can be obtained.

In the second semiconductor device, the spacer film may be a first spacer film provided on the control gate electrode and the dielectric film, and a first spacer film provided on the first spacer film. In the case of using two spacer films, at least one of the first spacer film and the second spacer film only needs to have an oxygen passage preventing function.

In the second semiconductor device, the first semiconductor device
When the spacer film is an oxide film, the second spacer film may be a film having an oxygen passage preventing function.

In the second semiconductor device, when the semiconductor device further includes a conductor protection film provided on the control gate electrode, the first spacer film extends to a side surface of the conductor protection film. Preferably it extends.

In the second semiconductor device, when the conductor portion protective film is formed of an oxide film, the upper end of the first spacer film is located at a position higher than the height of the upper surface of the conductor portion protective film. Is also preferably low.

In the second semiconductor device, the conductor portion protective film may be a first conductor portion protective film made of an oxide film, and may be provided on the first conductor portion protective film and have a function of preventing passage of oxygen. In the case where the first spacer film is constituted by the second conductor portion protective film, the first spacer film may extend to the side surfaces of the first conductor portion protective film and the second conductor portion protective film. preferable.

In the second semiconductor device, the second semiconductor device
May be a film containing oxynitride.

In the second semiconductor device, the spacer film may be provided so as to cover the upper surface and side surfaces of the entire control gate electrode and the capacitor insulating film.

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a first conductor film on a semiconductor substrate and a second step of forming a dielectric film on the first conductor film are provided. A third step of forming a second conductor film on the dielectric film, and a fourth step of forming a spacer film containing at least silicon nitride on at least side surfaces of the dielectric film and the second conductor film. And a process.

According to this method, in the fourth step, a spacer film containing silicon nitride having a high oxygen blocking function is formed, so that an increase in the thickness at both ends of the dielectric film can be suppressed.

In the method of manufacturing a semiconductor device, a step of forming a gate insulating film on a semiconductor substrate may be further provided before the first step, and in the first to third steps, a floating gate electrode conductor may be formed. After sequentially stacking a film, an insulating film for a capacitor insulating film, and a conductor film for a control gate electrode, the first film is patterned by patterning each of the films.
Forming a floating gate electrode as a conductive film, a capacitor insulating film as the dielectric film, and a control gate electrode as the second conductive film, wherein the fourth step is the same as the third step. Later, the spacer film may be formed on the side surfaces of the control gate electrode, the capacitor insulating film, and the floating gate electrode.

According to this method, a first semiconductor device is formed.

In the method of manufacturing a semiconductor device, a step of forming a gate insulating film on a semiconductor substrate may be further provided before the first step. In the first and second steps, a floating gate electrode may be formed. After sequentially laminating the conductive film for the capacitor, the insulating film for the capacitor insulating film, and the conductive film for the control gate electrode, the control gate electrode as the second conductive film is formed by patterning the conductive film for the control gate electrode and the capacitor insulating film. Forming an electrode and a capacitor insulating film as the dielectric film; forming the spacer film on the side surfaces of the control gate electrode and the capacitor insulating film in the fourth step; and forming the fourth film in the third step. Patterning the floating gate electrode conductor film using the control gate electrode and the capacitor insulating film as a mask after the step Accordingly, the first side surface is exposed
Forming a floating gate electrode as a conductor film of
Forming a tunnel insulating film made of an oxide film by thermally oxidizing the exposed side surface of the floating gate electrode after the third step; and opposing the floating gate electrode with the tunnel insulating film interposed therebetween. Forming an erase gate electrode.

According to this method, the second semiconductor device can be formed.

In the method of manufacturing a semiconductor device, in the fourth step, a spacer film made of a single-layer silicon nitride film can be formed.

In the method of manufacturing a semiconductor device, in the fourth step, a spacer film including at least a stacked film of a silicon nitride film and an oxide film can be formed.

In the method of manufacturing a semiconductor device, in the fourth step, a spacer film including an oxynitride film may be formed.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a floating gate type nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described.

As shown in FIG. 1, in the semiconductor memory device according to the present embodiment, a gate insulating film 10 made of a silicon oxide film having a thickness of about 30 nm and a And a floating gate electrode 11 made of a polysilicon film. However, the gate insulating film 10 may be formed of a silicon oxide film having a thickness of about 10 nm to have a function as a tunnel insulating film. On the floating gate electrode 11, a capacitance insulating film 12 made of a silicon oxide film having a thickness of about 25 nm and a control gate electrode 13 made of a polysilicon film having a thickness of about 400 nm are formed. In the silicon substrate 1, there are provided a source region 8 and a drain region 9 formed by introducing a high-concentration N-type impurity into the silicon substrate 1.

The feature of the semiconductor memory device according to the present embodiment is that the maximum thickness (lateral dimension at the lower end) formed over the side surfaces of the floating gate electrode 11, the capacitor insulating film 12, and the control gate electrode 13 is provided. Is a first spacer film 1 made of a silicon oxide film having a thickness of about 200 nm.
4 and a second spacer film 15 made of a silicon nitride film having a maximum thickness (lateral dimension at the lower end) of about 100 nm formed on the first spacer film 14. However, although not shown, an interlayer insulating film and a wiring layer thereover are provided on the substrate.

According to the semiconductor memory device of the present embodiment, on the side surface of the capacitive insulating film 12 including the silicon oxide film,
Since the second spacer film 15 made of oxidation-resistant silicon nitride film is provided via the first spacer film 14 made of silicon oxide film, activation of impurities implanted during the manufacturing process of the semiconductor memory device is activated. Even if a high-temperature heat treatment is performed in an oxidizing atmosphere, supply of oxygen to both ends of the capacitor insulating film 12 and the control gate electrode 13 is hindered. Therefore, the increase in the thickness of both ends of the capacitance insulating film 12 as in the above-described conventional semiconductor memory device is suppressed, and the capacitance of the capacitance insulating film 12 is maintained at an appropriate value. Therefore,
In the capacitance portion composed of the floating gate electrode 11, the capacitance insulating film 12, and the control gate electrode 13, the capacitance coupling ratio between the control gate electrode 13 and the floating gate electrode 11 is maintained in an appropriate range, and the voltage is reduced.
Even when the gate length is miniaturized, required characteristics such as high-speed writing and erasing and a large read current can be maintained satisfactorily.

FIG. 3 is a characteristic diagram comparing the gate length dependence of the rate of decrease of the capacitance coupling ratio of the floating gate type semiconductor memory device according to the present embodiment with the conventional semiconductor memory device. Here, the gate length on the horizontal axis indicates the horizontal dimension of the control gate electrode 13 in the cross section shown in FIG. 1, and the vertical axis indicates the capacitance coupling ratio between the floating gate electrode and the control gate electrode. As shown in the figure, the capacitance coupling ratio of the capacitance portion in the conventional semiconductor memory device rapidly decreases as the gate length becomes shorter when the electrode length becomes 0.5 μm or less. In the semiconductor memory device according to the embodiment, the capacitance coupling ratio of the capacitance portion hardly decreases even when the gate length becomes 0.4 μm or less. That is, according to the present invention, it is understood that the capacitance coupling ratio between the control gate electrode and the floating gate electrode can be kept within an appropriate range even when the gate length is shortened due to the miniaturization of the semiconductor memory device.

Next, a manufacturing process of the semiconductor memory device according to the present embodiment will be described with reference to FIGS. 2A to 2D.

First, in a step shown in FIG. 2A, a silicon oxide film 3 having a thickness of about 30 nm and a silicon nitride film 4 having a thickness of about 100 nm are sequentially formed on a silicon substrate 1 and these two films are patterned. Thus, an opening is formed in a region where element isolation is to be formed. Then, the silicon substrate 1 exposed in the opening is oxidized from the surface to form a field oxide film 2 having a thickness of about 700 nm.

Next, in the step shown in FIG. 2B, after removing the silicon nitride film 4 and the silicon oxide film 3, a silicon oxide film 10x having a thickness of about 30 nm is formed on the substrate by a thermal oxidation method. Then, on the silicon oxide film 10x, 2
About 10 × 10 ²⁰ cm ^-3 phosphorus-doped thickness of about 30
A 0 nm polysilicon film 11x is formed by a vapor phase growth method. After that, the polysilicon film 11x is thermally oxidized to form a silicon oxide film 12x serving as a capacitance insulating film. At this time, in this embodiment, the film is oxidized in an oxidizing atmosphere at 1000 ° C. to have a film thickness of about 25 nm. Further, on the silicon oxide film 12x, a polysilicon film 1 doped with about 2 × 10 ²⁰ cm ⁻³ of phosphorus and having a thickness of about 400 nm is formed.
3x is formed by a vapor deposition method.

Next, in the step shown in FIG. 2C, the polysilicon film 13x, the silicon oxide film 12x, and the polysilicon film 11 are formed.
x and the silicon oxide film 10x are patterned to form an electrode unit including the gate insulating film 10, the floating gate electrode 11, the capacitor insulating film 12, and the control gate electrode 13. Using the entire electrode unit and field oxide film 2 as a mask, arsenic ion implantation energy is 50 keV, and the dose is 4 × 10 ¹⁵ cm.
Injection is performed into the silicon substrate 1 under the condition of ^-3 to form a source region 8 and a drain region 9 which are self-aligned with the electrode unit.

Thereafter, a silicon oxide film having a thickness of about 250 nm is deposited on the substrate by vapor phase epitaxy, and then anisotropic dry etching is performed to form a gate insulating film 10, a floating gate electrode 11, a capacitive insulating film 12, A first spacer film made of a silicon oxide film is formed on both side surfaces of the electrode unit made of the control gate electrode. Further, a thickness of 150 n is formed on the substrate by a vapor growth method.
After depositing a silicon nitride film of about m, anisotropic dry etching is performed to form a second spacer film 15 for preventing oxidation on the first spacer film 14. The silicon nitride film is formed by, for example, dichlorosilane (SiH ₂ Cl).
₂ ) At a temperature of 750 ° C., ammonia (NH ₃ ) is obtained by a reduced pressure vapor phase growth method utilizing a chemical reaction between ammonia (NH ₃ ) and NH _3.
3 ) and the flow ratio of dichlorosilane (SiH ₂ Cl ₂ ) is set to 5.

Next, in a step shown in FIG. 2D, after an interlayer insulating film 17 made of a silicon oxide film having a thickness of about 1000 nm is formed on the entire surface of the substrate by a vapor phase growth method, the source region 8 and the drain region 9 are formed. In order to activate impurities in the semiconductor and to densify the silicon oxide film forming the interlayer insulating film 17,
Heat treatment is performed in an oxidizing atmosphere at 1000 ° C. for 20 minutes. At this time, the silicon nitride film is formed on both side surfaces of the electrode unit including the gate insulating film 10, the floating gate electrode 11, the capacitor insulating film 12, and the control gate electrode 13 via the first spacer film 14 made of the silicon oxide film. Since the second spacer film 15 is formed, supply of oxygen to the silicon oxide film forming the capacitive insulating film 12 and the polysilicon film forming each of the gate electrodes 11 and 13 is prevented. Therefore, the phenomenon that the thickness of both ends of the capacitance insulating film 12 is larger than that of the center portion does not occur.

Thereafter, a contact hole reaching the source region 8 and the drain region 9 and a contact hole (not shown) reaching the control gate electrode 13 are formed in the interlayer insulating film 17, and then the aluminum alloy film is formed on the substrate. Then, an aluminum electrode 18 is formed by patterning this.

Through the above manufacturing steps, the floating gate type semiconductor memory device shown in FIG. 1 is formed.

Next, in the floating gate type semiconductor memory device according to the first embodiment, the following modifications are possible.

FIG. 4 shows a semiconductor memory device according to the first embodiment in which the gate insulating film 10 is partially etched to form a tunnel insulating film 16 having a thickness of, for example, about 10 nm in the floating gate type semiconductor memory device according to the first embodiment. It is sectional drawing of an apparatus.

The floating gate type semiconductor memory device according to the first embodiment has a stacked gate structure in which a floating gate electrode is formed on the entire surface of a channel region sandwiched between a source region 8 and a drain region 9. However, it is also possible to apply the structure provided with the spacer film of the present invention to a split gate structure in which a floating gate electrode is formed only on a part of the channel region sandwiched between the source region 8 and the drain region 9. It is.

(Second Embodiment) Next, a floating gate type semiconductor memory device with an erase gate according to a second embodiment will be described.

FIG. 5 is a sectional view of a semiconductor memory device according to the second embodiment. However, FIG. 5 shows a structure in a cross section orthogonal to the gate length direction. In FIG.
Although a pair of cells and an erase gate electrode 26 commonly used for each cell are shown, the structure of one of the pair of cells will be described first.

As shown in FIG. 5, on the P-type silicon substrate 1, active regions separated by element isolation insulating films composed of silicon oxide films 30 and 31 are provided. A gate insulating film 20 made of a silicon oxide film having a thickness of about 30 nm and a floating gate electrode 21 made of a polysilicon film having a thickness of about 400 nm are sequentially formed. Further, on the floating gate electrode 21, a capacitance insulating film 22 made of a silicon oxide film having a thickness of about 25 nm, a control gate electrode 23 made of a polysilicon film having a thickness of about 400 nm, and a silicon oxide film having a thickness of about 300 nm are formed. An on-gate insulating film 24 made of a film is formed. On the side surface of the floating gate electrode 21, a tunnel insulating film 25 made of a silicon oxide film having a thickness of about 35 nm formed by oxidizing a region near the side surface of the polysilicon film is provided. The maximum thickness (lateral dimension at the lower end) formed over the side surfaces of the floating gate electrode 21, the capacitor insulating film 22, and the control gate electrode 23 is about 200.
a first spacer film 27 made of a silicon oxide film having a thickness of
A second spacer film 28 made of a silicon nitride film having a maximum thickness (lateral dimension at the lower end) of about 100 nm formed on the first spacer film 27 is provided.

Further, an erase gate electrode 26 shared by the pair of cells is provided on the silicon oxide film 30 serving as a region between the pair of cells. The erase gate electrode 26 is formed of a polysilicon film having a thickness of about 400 nm, and includes the capacitance insulating film 22 and the control gate electrode 2.
1 and the second spacer film 2
7 and 28, and the floating gate electrode 2
1 is opposed to the tunnel insulating film 25.

Although not shown in the cross section shown in FIG. 5, a source region and a drain region formed by introducing a high-concentration N-type impurity into silicon substrate 1 are formed in silicon substrate 1. Is provided.

According to the semiconductor memory device of the present embodiment, on the side surface of the capacitance insulating film 22 including the silicon oxide film,
Since the second spacer film 28 made of the oxidation-resistant silicon nitride film is provided via the first spacer film 27 made of the silicon oxide film, the polysilicon film forming the floating gate electrode 21 is oxidized to perform tunnel insulation. Membrane 25
In a high-temperature oxidation step (usually performed at 900 to 1000 ° C.) for forming
Can be prevented from being oxidized at both ends of the polysilicon film, and an increase in the film thickness at both ends of the capacitor insulating film 22 can be suppressed.

Therefore, the thickness of both ends of the capacitance insulating film 22 does not greatly increase unlike the conventional semiconductor memory device, and the capacitance of the capacitance insulating film 22 is maintained at an appropriate value. Therefore, in the capacitance portion composed of the floating gate electrode 21, the capacitance insulating film 22, and the control gate electrode 23, the capacitance coupling ratio between the control gate electrode 23 and the floating gate electrode 21 is maintained in an appropriate range, and the voltage is reduced and the gate length is reduced. Even when miniaturization progresses,
Necessary characteristics such as high-speed writing and erasing and a large read current can be maintained favorably.

Next, the manufacturing process of the semiconductor memory device according to the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

First, in the step shown in FIG. 6A, a silicon oxide film 30 having a thickness of about 30 nm for separating the active region and a silicon oxide film 31 on the side surface thereof are formed on the silicon substrate 1 and then the active region is formed. Next, a gate insulating film 20 made of a silicon oxide film having a thickness of about 30 nm is formed by a thermal oxidation method. Thereafter, a polysilicon film 2 doped with about 2 × 10 ²⁰ cm ^-3 of phosphorus and having a thickness of about 300 nm is formed on the substrate.
1x is formed by a vapor deposition method. Thereafter, the polysilicon film 21x is thermally oxidized to form a silicon oxide film 22x serving as a capacitance insulating film. At this time, in the present embodiment, 1
Oxidized in an oxidizing atmosphere at 000 ° C. to a thickness of about 25 nm
And Further, a thickness of about 4 × 10 ²⁰ cm ⁻³ doped with phosphorus on the silicon oxide film 22x is about 4 × 10 ²⁰ cm ^−3.
A polysilicon film 23x of 00 nm and a thickness of about 300 n
m silicon oxide films 24x are sequentially formed by a vapor growth method.

Next, in the step shown in FIG. 6B, the silicon oxide film 24x, the polysilicon film 23x and the silicon oxide film 2x are formed.
2x is patterned to form a capacitance insulating film 22, a control gate electrode 23, and an on-gate insulating film 24.
After that, a silicon oxide film having a thickness of about 250 nm is deposited on the substrate by a vapor phase growth method, and then anisotropic dry etching is performed, so that both sides of the capacitance insulating film 22, the control gate electrode 23 and the on-gate insulating film 24 are formed. A first spacer film 27 made of a silicon oxide film is formed thereon. Further, after a silicon nitride film having a thickness of about 150 nm is deposited on the substrate by a vapor growth method, anisotropic dry etching is performed to form a second spacer film 28 for preventing oxidation on the first spacer film 27. Form.

Next, in the step shown in FIG.
Etching is performed using the electrode unit including the mask 8 as a mask, and the polysilicon film 21x is patterned to form the floating gate electrode 21. At this point, the side surface of the floating gate electrode 21 is
Is self-aligned and exposed.

Next, in the step shown in FIG. 7A, the exposed side surface of the floating gate electrode 21 is thermally oxidized in a steam atmosphere at 900 ° C. to form a tunneling insulating film 25 made of a silicon oxide film having a thickness of about 30 nm. To form At this time, since the second spacer film 28 made of the silicon nitride film is formed, an increase in the film thickness at both ends of the capacitor insulating film 22 is suppressed by the same operation as in the first embodiment.

Next, in a step shown in FIG. 7B, a polysilicon film having a thickness of about 400 nm is formed on the entire surface of the substrate by a vapor phase growth method, and thereafter, by using a photo-etching technique.
By patterning the polysilicon film, an erase gate electrode 26 covering the tunneling insulating film 25 is formed.

After that, the silicon substrate 1 in the active region is
Impurity ions are implanted therein to form a source region and a drain region. However, since the source region and the drain region do not appear in the cross sections shown in FIGS. 7A and 7B, description thereof will be omitted.

A process for forming an interlayer insulating film, a metal wiring, a protective film, and a bonding pad is performed.
Since these can be implemented by a well-known technique and are not related to the present invention, the description is omitted.

(Other Embodiments) Next, the first embodiment of the present invention will be described.
The first and second conductor parts are related to the structure of a capacitance part composed of a second conductor part and an insulating film sandwiched between the conductor parts.
Another embodiment different from the second embodiment will be described.

FIG. 8 shows a capacitor insulating film 52 made of a silicon oxide film or the like and a second conductor made of a polysilicon film or the like on a first conductor portion 51 made of a polysilicon film or the like.
And an on-gate insulating film 54 composed of a silicon oxide film or the like. Then, the capacitance insulating film 5
2. A first spacer film 55 and a second spacer film 56 are formed on side surfaces of the second conductor film 53 and the on-gate insulating film 54. The structure of the electrode unit is the same as that of the second embodiment.
However, as in the first embodiment, the first conductor film 51 is patterned so as to have the same planar shape as the capacitance insulating film 52, the second conductor film 53, and the like. The first and second spacer films 55 and 56 are
May extend on the side surface of the conductive film 51.

Here, different from the structure of the second embodiment, the upper end of the first spacer film 55 shown in FIG. 8 is located lower than the upper surface of the on-gate insulating film 54. Such a structure can be easily realized by over-etching when depositing a silicon oxide film or the like for forming the first spacer film 55 and performing anisotropic etching. By thus lowering the upper end of the first spacer film 55, the contact area between the first spacer film 55 and the insulating film 54 above the gate is reduced. Therefore, even when the on-gate insulating film 54 and the first spacer film 55 are both formed of a silicon oxide film, oxygen passes through the silicon oxide film to form the capacitor insulating film 52 in the heat treatment process in an oxidizing atmosphere. There is an advantage that it can be more reliably prevented from reaching the vicinity of both ends. However, also in the second embodiment, the insulating film 5 on the gate
In order to reach both ends of the capacitor insulating film 52 through the contact portion between the capacitor insulating film 4 and the first spacer film 55, it is necessary to pass through a long and narrow path, so that much oxygen is supplied to the capacitor insulating film 52.
(And the portions of the first conductor film 51 and the second conductor film 53 in contact with both ends). Therefore, even with the configuration of the electrode unit as in the second embodiment, there is an effect of suppressing an increase in the thickness of both ends of the capacitance insulating film 52.

As shown by the dotted line in FIG. 8, the supply of oxygen is ensured by over-etching the silicon oxide film until the upper end of the first spacer film 55 is at the same position as the upper surface of the second conductor film 53. Can be blocked. Therefore, it is possible to more reliably prevent the thickness of both ends of the capacitive insulating film 52 from increasing, and the effect is particularly large when the gate length is further reduced.

FIG. 9 is a cross-sectional view showing the structure of a capacitor in which an oxidation preventing film 57 made of an insulating film having a high oxygen blocking function such as a silicon nitride film is further formed on the insulating film 54 above the gate. In this case, when performing anisotropic etching of a silicon oxide film or the like for forming the first spacer film 55, the capacitor insulating film 5 can be formed without over-etching.
It is possible to more reliably prevent the passage of oxygen to the vicinity of both ends of the second member. Therefore, there is an advantage that damage to the underlayer due to over-etching can be more reliably prevented.

FIG. 10 shows the structure of a capacitor portion provided with an oxidation prevention film 58 such as a silicon nitride film covering the side surfaces of the on-gate insulating film 54, the second conductor film 53 and the capacitive insulating film 52. FIG. Also in this case, with a simple configuration, the passage of oxygen to the vicinity of both ends of the capacitor insulating film 52 can be reliably prevented, and the thickness of both ends of the capacitor insulating film 52 can be prevented from increasing.

In each of the above embodiments, the silicon oxide film is used as the capacitor insulating film. However, the insulating film of the capacitor in the present invention is not limited to this. For example, a silicon nitride film-based insulating film, for example, a silicon nitride film-silicon oxide film two-layer film (ON film), a silicon oxide film-silicon nitride film-silicon oxide film three-layer film (ONO)
Film) may be used. Further, an oxynitride film may be used.

The spacer film of the present invention may be basically any film as long as it has a function of blocking the passage of oxygen. However, in order to avoid electrical connection between the conductor films or between the conductor film and the substrate, the film is preferably made of an insulating material. Therefore, as the spacer film, in addition to the laminated film of the silicon oxide film (first spacer film) and the silicon nitride film (second spacer film) in each of the above embodiments, a single-layer film of the silicon nitride film shown in FIG. And an insulating film containing silicon nitride such as a silicon oxide film-silicon nitride film-silicon oxide film three-layer film and an oxynitride film. Further, in each of the above embodiments, the first spacer film may be formed of a silicon nitride film, and the second spacer film may be formed of a silicon oxide film.

However, since the silicon nitride film tends to have a larger leak current than the silicon oxide film, it is preferable to use the silicon oxide film for the member directly in contact with the electrode.

[0083]

According to the first semiconductor device of the present invention, a first conductor film, a dielectric film containing an oxidizing material, and a second conductor film are laminated on a semiconductor substrate. Conductive film,
Since the first spacer film made of an oxide film covering the side surfaces of the dielectric film and the second conductor film and the second spacer film covering the oxide film and having a function of preventing passage of oxygen are provided, Even if it receives heat treatment, it has the second function of blocking oxygen passage.
The spacer film suppresses the passage of oxygen to both ends of the dielectric film and the first and second conductor films adjacent thereto, thereby increasing the capacitance due to the increase in the thickness of both ends of the dielectric film. Can be suppressed.

According to the second semiconductor device of the present invention, a gate insulating film, a floating gate electrode, a capacitive insulating film composed of a dielectric film, and a control gate electrode are laminated on a semiconductor substrate, and the floating gate electrode is formed. A tunnel insulating film on the side surface, an erase gate electrode facing the floating gate electrode with the tunnel insulating film interposed therebetween,
Since a spacer film provided on the side surface of the control gate electrode and the capacitor insulating film and having a function of blocking oxygen passage is provided, a tunnel insulating film made of an oxide film interposed between the erase gate electrode and the floating gate electrode is formed. In the heat treatment in an oxidizing atmosphere necessary for the above, since both ends of the capacitor insulating film are covered with the spacer film, an increase in thickness at both ends of the capacitor insulating film can be suppressed, and the control gate electrode It is possible to provide a floating gate type semiconductor memory device having a high capacitance coupling ratio between floating gate electrodes and a high operation speed such as writing / erasing.

According to the method of manufacturing a semiconductor device of the present invention,
Forming a first conductive film on a semiconductor substrate, forming a dielectric film on the first conductive film, forming a second conductive film on the dielectric film, And a step of forming a spacer film containing at least silicon nitride on the side surface of the second conductor film. According to this method, in the fourth step, the spacer containing silicon nitride having a high oxygen blocking function is provided. Since the film is formed, it is possible to suppress an increase in thickness at both ends of the dielectric film.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device functioning as a floating gate type semiconductor memory device according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor memory device according to the first embodiment;

FIG. 3 is a characteristic diagram showing gate length dependence of a capacitance coupling ratio between the storage semiconductor device according to the first embodiment and a conventional semiconductor storage device.

FIG. 4 is a cross-sectional view of a semiconductor memory device according to a first modification that functions as a floating gate semiconductor memory device with a tunnel insulating film.

FIG. 5 is a sectional view of a floating gate type semiconductor memory device with an erase gate electrode according to a second embodiment.

FIG. 6 is a cross-sectional view illustrating a process up to a floating gate electrode forming process in the manufacturing process of the semiconductor memory device according to the second embodiment;

FIG. 7 is a cross-sectional view showing a step after a thermal oxidation step of a side surface of a floating gate electrode in a manufacturing step of the semiconductor memory device according to the second embodiment.

FIG. 8 is a cross-sectional view of a semiconductor memory device according to another embodiment having an on-gate insulating film made of a silicon oxide film and a first spacer film formed by over-etching.

FIG. 9 is a cross-sectional view of a semiconductor memory device according to another embodiment having an on-gate insulating film composed of a silicon oxide film and a silicon nitride film thereon, and a first spacer film that is not over-etched.

FIG. 10 shows an insulating film on a gate made of a silicon oxide film;
FIG. 21 is a cross-sectional view of a semiconductor memory device according to another embodiment having a silicon nitride film covering the entire electrode unit.

FIG. 11 is a sectional view of a conventional floating gate type semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 7 silicon substrate 8 source region 9 drain region 10 gate insulating film 11 floating gate electrode 12 capacitance insulating film 13 control gate electrode 14 first spacer film 15 second spacer film 16 tunnel insulating film 17 interlayer insulating film 18 aluminum electrode 20 gate insulating film Reference Signs List 21 floating gate electrode 22 capacitance insulating film 23 control gate electrode 24 insulating film on gate 25 tunnel insulating film 26 erase gate electrode 27 first spacer film 28 second spacer film

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115 29/78

Claims (22)

[Claims] A semiconductor substrate; a first conductive film provided on the semiconductor substrate; a dielectric film provided on the first conductive film and containing an oxidizing material; A second conductive film provided on the first conductive film, a first spacer film made of an oxide film covering side surfaces of the first conductive film, the dielectric film, and the second conductive film; A second spacer film having a covering function of preventing passage of oxygen. 2. The semiconductor device according to claim 1, wherein said semiconductor device includes a gate insulating film provided on a semiconductor substrate, a floating gate electrode provided on said gate insulating film, and said floating gate electrode. A non-volatile semiconductor storage device comprising: a capacitor insulating film provided on the substrate; and a control gate electrode provided on the capacitor insulating film, wherein the first conductive film is the floating gate electrode, The semiconductor device, wherein the dielectric film is the capacitance insulating film, and the second conductor film is the control gate electrode. 3. The semiconductor device according to claim 1, further comprising: a conductor protection film provided on the second conductor film, wherein the first spacer film is formed of the conductor protection film. A semiconductor device extending to a side surface. 4. The semiconductor device according to claim 3, wherein the conductor portion protective film is formed of an oxide film, and an upper end of the first spacer film is located at a height of an upper surface of the conductor portion protective film. Semiconductor device characterized by being lower than the above. 5. The semiconductor device according to claim 3, wherein the conductor portion protection film is a first conductor portion protection film made of an oxide film, and oxygen is provided on the first conductor portion protection film. A second conductor portion protective film having a blocking function, wherein the first spacer film extends over the side surfaces of the first conductor portion protective film and the second conductor portion protective film. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 1, wherein said second spacer film is a film containing silicon nitride. 7. The semiconductor device according to claim 1, wherein the first and second spacer films are the first conductor film, the dielectric film, and the second conductor film. A semiconductor device provided so as to cover the entire top surface and both side surfaces. 8. The semiconductor device according to claim 1, wherein said second spacer film is a film containing oxynitride. 9. A semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a floating gate electrode provided on the gate insulating film, and a dielectric provided on the floating gate electrode A capacitor insulating film made of a film; a control gate electrode formed on the capacitor insulating film; a tunnel insulating film formed on a side surface or a part of the side surface and the surface of the floating gate electrode; A semiconductor comprising: an erase gate electrode opposed to the floating gate electrode with a film interposed therebetween; and a spacer film provided on a side surface of the control gate electrode and the capacitor insulating film and having an oxygen passage blocking function. apparatus. 10. The semiconductor device according to claim 9, wherein said spacer film comprises: a first spacer film provided on said control gate electrode and said capacitor insulating film;
A second spacer film provided on the first spacer film, wherein at least one of the first spacer film and the second spacer film has an oxygen passage preventing function. . 11. The semiconductor device according to claim 10, wherein said first spacer film is an oxide film, and said second spacer film is a film having an oxygen passage preventing function. 12. The semiconductor device according to claim 11, further comprising a conductor protection film provided on the control gate electrode, wherein the first spacer film extends to a side surface of the conductor protection film. A semiconductor device characterized in that: 13. The semiconductor device according to claim 11, wherein the conductor portion protective film is formed of an oxide film, and an upper end of the first spacer film is located at a height of an upper surface of the conductor portion protective film. Semiconductor device characterized by being lower than the above. 14. The semiconductor device according to claim 11, wherein said conductor portion protection film is a first conductor portion protection film made of an oxide film, and oxygen is provided on said first conductor portion protection film. A second conductor portion protective film having a blocking function, wherein the first spacer film extends over the side surfaces of the first conductor portion protective film and the second conductor portion protective film. A semiconductor device characterized by the above-mentioned. 15. The semiconductor device according to claim 10, wherein the second spacer film is a film containing oxynitride. 16. The semiconductor device according to claim 9, wherein the spacer film is provided so as to cover an upper surface and side surfaces of the entire control gate electrode and the capacitor insulating film. 17. A first step of forming a first conductive film on a semiconductor substrate, a second step of forming a dielectric film on the first conductive film, and a second step of forming a dielectric film on the dielectric film. A third step of forming a second conductive film, and a fourth step of forming at least a spacer film containing silicon nitride on at least side surfaces of the dielectric film and the second conductive film. A method for manufacturing a semiconductor device. 18. The method for manufacturing a semiconductor device according to claim 17, further comprising, before the first step, a step of forming a gate insulating film on a semiconductor substrate. After sequentially stacking a floating gate electrode conductive film, a capacitor insulating film insulating film, and a control gate electrode conductive film, the respective films are patterned to form a floating gate electrode as the first conductive film, Forming a capacitor insulating film as a dielectric film and a control gate electrode as the second conductor film; and in the fourth step, after the third step, the control gate electrode and the capacitor insulating film. And forming the spacer film on the side surface of the floating gate electrode. 19. The method for manufacturing a semiconductor device according to claim 17, further comprising, before the first step, a step of forming a gate insulating film on a semiconductor substrate, wherein the first and second steps include: After sequentially stacking the conductive film for the floating gate electrode, the insulating film for the capacitor insulating film and the conductive film for the control gate electrode, the second conductive film is patterned by patterning the control gate electrode conductive film and the capacitor insulating film. Forming a control gate electrode and a capacitor insulating film as the dielectric film, and forming the spacer film on side surfaces of the control gate electrode and the capacitor insulating film in the fourth step; In the step, after the fourth step, the floating gate electrode conductor is formed using the control gate electrode and the capacitor insulating film as a mask. To form a floating gate electrode as the first conductor film having exposed side surfaces, and after the third step, thermally oxidize the exposed side surfaces of the floating gate electrode to form an oxide film. A method of manufacturing a semiconductor device, further comprising: a step of forming a tunnel insulating film comprising: and a step of forming an erase gate electrode facing the floating gate electrode with the tunnel insulating film interposed therebetween. 20. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, a spacer film made of a single-layer silicon nitride film is formed. Manufacturing method of a semiconductor device. 21. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, a spacer film including a stacked film of a silicon nitride film and an oxide film is formed. A method for manufacturing a semiconductor device, comprising: 22. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, a spacer film including an oxynitride film is formed. Device manufacturing method.