JPH09289457A - Digital information reproducing device, maximum likelihood decoding device and phase comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the transfer rate of the digital information reproducing device by providing an SMU which stores likelihood state transition to specific length, excluding the state transition array of a rules by partial response equalization, and outputs a survival path and performing synchronous operation at a frequency which is 1/n as high as a channel clock. SOLUTION: This device is equipped with a frequency divider 4 which divides the frequency of a timing signal by n, a parallel data converter 5 which outputs quantized data outputted from an A/D converting means in parallel according to the clock generated by dividing the frequency of n pieces of quantized data, a BMU (branch metric unit) which finds the distance between the n pieces of quantize data inputted from the converter 5 and a partial response equalization expected value, an ACS(addition/comparison selection unit) which performs adding operation between the branch metric inputted from the BMU and metric values showing the likelihood in respective states n time before, selects a likelihood state transition out of possible state transitions in every hours, and outputs the result to the SMU (survival memory unit) 3, and the SMU 3 which excludes a state transition array that can not be carried on along the time base according to the rule determined by the partial response equalization and outputs survival paths.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information reproducing apparatus for reproducing original digital information from an analog signal reproduced from a recording medium.

[0002]

2. Description of the Related Art As a method for demodulating digital information recorded at high density on a medium, PRML signal processing combining partial response equalization and Viterbi decoding is used. When high density recording is performed on the medium, interference between codes occurs due to the frequency characteristics of the recording / reproducing system. The partial response equalization can improve the S / N ratio as compared with the conventional Nyquist equalization by giving a known intersymbol interference. on the other hand,
Viterbi decoding is effective when there is a correlation before and after the code.
The partial response equalization is effective in combination with Viterbi decoding because it gives a known intersymbol interference by providing correlation between the codes. A digital information reproducing apparatus using such a PRML signal processing system outputs from a A / D converting means for quantizing a predetermined partial response equalized reproduced signal for each timing signal and an A / D converting means. A maximum likelihood decoding means for decoding the original digital information with the quantized data as an input and a timing signal extracting means for generating a timing signal used in the A / D conversion means are provided. It is known that the error rate can be significantly improved as compared with the binary detection method using the slice level up to now.

[0003]

FIG. 1 shows an example of the maximum likelihood decoding means of the PRML signal processing system. In the maximum likelihood decoding means, first, a branch metric unit (hereinafter B
MU), a distance between the quantized data input from the A / D conversion means and the expected partial response equalization value, that is, a so-called branch metric is obtained.

Next, an addition comparison selection unit (hereinafter referred to as ACS
In the above), the branch metric input from the BMU and the metric value indicating the certainty of each state one hour before are added, the results are compared, and the state transitions that are likely to occur at each time Is selected and the selected result is output to the survival memory unit (hereinafter referred to as SMU). The SMU stores a certain length of certain state transitions, eliminates the state transition sequence in which transitions cannot continue in the time axis direction according to the rules established by partial response equalization, and the most probable state remaining as a result. Output the transition sequence, the so-called survivor path.

The original digital information can be decoded from this survivor path. In such maximum likelihood decoding means,
All the calculations are performed in synchronization with the timing signal, and the calculations must be completed at the timing signal intervals. Parallel processing may be considered to increase the processing speed of the maximum likelihood decoding means, but since ACS uses the metric value one hour before, there is a problem that speedup cannot be realized by simple parallel processing. It was

FIG. 2 shows an example of the path feedback type maximum likelihood decoding means. BMU, ACS, and SMU operate in the same manner as the maximum likelihood decoding means in FIG. The survivor path information output from the SMU is the low-pass filter (hereinafter L
PF). Shift register (hereinafter RE
G) represents the quantized data as BMU, ACS and SMU.
It is delayed by the same time as the processing time of and output to the LPF. L
The PF stores the quantized data in different memories according to the survivor path information, and obtains the average value of the quantized data.
The calculated average value includes the ideal expected partial response equalization value and the level fluctuation component included in the reproduced signal, the average value is fed back to the BMU, and the phase error amount of the timing signal is calculated from the calculated average value. Is calculated and output to the digital loop filter (DLF). The DLF obtains the integrated value of the phase error amount and outputs the sum of the instantaneous value of the phase error amount and the integrated value to the timing signal extraction means.

In such a path feedback type maximum likelihood decoding means,
Before obtaining the partial response equalization expected value including the level fluctuation component in the LPF, BMU, ACS and S
There is a problem that the processing time in the MU and LPF is required, and the frequency band of the level fluctuation component that can be feedback-controlled is limited. In addition, before the control signal of the VCO in the timing signal extraction means is obtained in the DLF, BMU, ACS, SMU, LPF, DLF
However, there is a problem that the capture range of the phase-locked loop becomes small because it requires only the processing time at.

[0008]

A maximum likelihood decoding apparatus according to the present invention comprises a frequency divider (n is an integer greater than 1) that divides the timing signal output from the timing signal extraction means by 1 / n. A parallel data converter that outputs the quantized data output from the A / D conversion means in parallel in synchronization with the quantized data of the n quantized data, and n quantized data input from the parallel data conversion means. BMU for obtaining the distance between the normalized data and the expected value of partial response equalization
And a branch metric input from the BMU and a metric value indicating the certainty of each state n time ago are added, the results are compared, and a probable state transition is selected from the possible state transitions at each time. And the selected result is S
The ACS output to the MU and certain state transitions are stored for a predetermined length, and a sequence of transitions in which transition cannot continue in the time axis direction is eliminated according to a rule determined by partial response equalization, and a surviving path is output. It is configured to include an SMU.

The digital information reproducing apparatus of the present invention comprises A / D conversion means for converting a reproduced signal into quantized data, and A / D conversion means.
A maximum likelihood decoding means for decoding the original digital information with the quantized data output from the D conversion means as an input, and a timing signal used in the A / D conversion means based on the phase error information output from the maximum likelihood decoding means. In a digital information reproducing apparatus having a timing signal extracting means for generating
When the gate signal indicating the start timing of the signal processing by the timing signal extraction means becomes valid, the timing signal is generated at the preset center frequency at the moment when the reproduction signal reaches the preset threshold value, and The frequency of the timing signal is changed based on the phase error amount output from the likelihood decoding means, the preset amplification factor control signal, and the center frequency control signal.

The digital information reproducing apparatus of the present invention is
A / D conversion means for converting the reproduced signal into quantized data,
The maximum likelihood decoding means for decoding the original digital information with the quantized data output from the A / D conversion means as input, and the timing signal extraction means are preset when the gate signal indicating the start timing of signal processing becomes valid. A timing signal is generated at a preset center frequency at the moment when the reproduction signal reaches the threshold value, and a phase error amount output from the maximum likelihood decoding means, a preset amplification factor control signal, and a center frequency control signal are also generated. In the digital information reproducing apparatus provided with the timing signal extracting means for generating the timing signal with the oscillation frequency changed, the gate signal becomes effective, and the first quantized data from the A / D converting means becomes the maximum likelihood decoding means. A metric value indicating the certainty of each state one time before the input and the start of calculation in the ACS in the maximum likelihood decoding means. And configured to be initialized to a predetermined value.

The digital information reproducing apparatus of the present invention is
A / D conversion means for converting the reproduced signal into quantized data,
The phase comparison means for obtaining the phase error information from the quantized data using the quantized data output from the A / D conversion means as input, and the timing signal extraction means are preset when the gate signal indicating the start timing of signal processing becomes effective. A timing signal is generated at a preset center frequency at the instant when the reproduction signal reaches the threshold value, and the phase error amount output from the phase comparison means and the preset amplification factor control signal and center frequency control signal are generated. Based on the above, a configuration is provided in which the timing signal extracting means for generating the timing signal with the oscillation frequency changed is provided.

Further, the digital information reproducing apparatus of the present invention is
A / D conversion means for converting the reproduced signal into quantized data,
The maximum likelihood decoding means for decoding the original digital information with the quantized data output from the A / D conversion means as input, and the timing signal extraction means are preset when the gate signal indicating the start timing of signal processing becomes valid. A timing signal is generated at a preset center frequency at the moment when the reproduction signal reaches the threshold value, and a phase error amount output from the maximum likelihood decoding means, a preset amplification factor control signal, and a center frequency control signal are also generated. In the digital information reproducing device having the timing signal extracting means for changing the frequency of the timing signal, the maximum likelihood decoding means has path memories of different lengths, and from different surviving path information, different phase error information is obtained, A from the time when the gate signal indicating the signal processing start timing of the timing signal extraction means becomes valid
The / D conversion means selects the phase error information according to the output value of the counter circuit which counts the number of times the reproduced signal is quantized, obtains the phase error amount, and outputs it to the timing signal extraction means.

The digital information reproducing apparatus of the present invention is
A / D conversion means for converting the reproduced signal into quantized data,
A maximum likelihood decoding means for decoding the original digital information with the quantized data output from the A / D conversion means as an input;
The phase comparison means for obtaining the phase error information from the quantized data using the quantized data output from the converting means and the preset threshold when the gate signal indicating the start timing of the signal processing by the timing signal extracting means becomes effective. The timing signal frequency is generated based on the detected phase error amount, the preset amplification factor control signal and the center frequency control signal by generating the timing signal at the preset center frequency at the moment when the reproduction signal reaches the value. In the digital information reproducing apparatus having the timing signal extracting means for changing the signal, the maximum likelihood decoding means causes the A / D converting means to reproduce the reproduced signal from the time when the gate signal indicating the signal processing start timing of the timing signal extracting means becomes effective. The phase error information and the position of the maximum likelihood decoding means are determined by the output value of the counter circuit that counts the number of times Select the phase error information comparison means obtains a phase error amount, configured to output to the timing signal extractor.

The digital information reproducing apparatus of the present invention is
A / D conversion means for converting the reproduced signal into quantized data,
The maximum likelihood decoding means for decoding the original digital information with the quantized data output from the A / D conversion means as input, and the timing signal extraction means are preset when the gate signal indicating the start timing of signal processing becomes valid. The timing signal is generated based on the detected phase error amount, the preset amplification factor control signal and the center frequency control signal by generating the timing signal at the preset center frequency at the moment when the reproduction signal reaches the threshold value. In a digital information reproducing apparatus provided with a timing signal extracting means for changing the frequency,
The timing signal extraction means counts the number of times the A / D conversion means quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the timing signal extraction means becomes effective, and the digital loop is performed by the output value of the counter circuit. The configuration is such that the filter coefficient is changed.

The digital information reproducing apparatus of the present invention is
A / D conversion means for converting the reproduced signal into quantized data,
The maximum likelihood decoding means for decoding the original digital information with the quantized data output from the A / D conversion means as input, and the timing signal extraction means are preset when the gate signal indicating the start timing of signal processing becomes valid. The timing signal is generated based on the detected phase error amount, the preset amplification factor control signal and the center frequency control signal by generating the timing signal at the preset center frequency at the moment when the reproduction signal reaches the threshold value. In a digital information reproducing apparatus provided with a timing signal extracting means for changing the frequency,
The timing signal extraction means counts the number of times the A / D conversion means quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the timing signal extraction means becomes valid, and reaches the maximum value when it reaches a predetermined value. The partial response equalization expected value used for the branch metric calculation of the likelihood decoding means is switched from the fixed partial response equalization initial expected value to the partial response equalization expected value detected by the maximum likelihood decoding means.

The phase comparison method of the present invention quantizes a reproduced signal in an area in which a specific original digital information pattern is recorded, subtracts a quantized data and a predetermined value, and outputs the subtracter output. A shift register for storing, a multiplier for multiplying an output value of the shift register by an output value of the subtractor, and a register for storing an output of the multiplier,
A counter circuit that counts the number of input quantized data and a selector circuit that selects the output of the multiplier and the output of the register according to the output value of the counter circuit are provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the maximum likelihood decoding system of the present invention will be described. As a modulation code, the so-called (d, k)
A run-length limited code (hereinafter referred to as an RLL code) satisfying the limitation (d and k are integers satisfying d, k ≧ 0), and particularly a code satisfying the minimum run-length condition (d = 2) is used. . The recording code is NRZI (Non Ret
urn to Zero Inverted) Modulate. Further, as the partial response equalization, an equalization method in which the impulse response h (t) satisfies (Equation 1) is used.

[0018]

[Equation 1]

In the following description of the present embodiment, for simplicity,
The so-called PR (1, 3, 3, 1) equalization is taken up, and the constants in the impulse response are a = d = 1 and b = c, respectively.
= 3. When the recording code having the minimum polarity reversal distance of 3 and the PR (1,3,3,1) equalization method are combined as in the present embodiment, the original digital information b _t (t represents time and is equal to or greater than 0) The integer value) and the amplitude value x _t of the partial response equalized output follow the state transition diagram of FIG.

In FIG. 3, the symbol S (l, m, n) is assigned to each state.
There are added, S (l, m, n ) is 1-bit previous recording code c _t-1 is l, record code c _t-2 of 2 bits before the m
Indicates that the recording code _ct-3 3 bits before is n. Further, the symbols of the recording code c _t is 0 or 1. V / u added to each state transition in FIG. 3, v is the value of the original digital information b _t input at the current time, u
Indicates the expected amplitude value x _t of the partial response equalized output. A trellis diagram as shown in FIG. 4 is obtained by expanding the state transition diagram of FIG. 3 in the time axis direction. When the value obtained as a result of sampling the reproduction signal with the timing signal extracted from the reproduction signal is quantized data y _t as an index indicating the likelihood of each state in performing maximum likelihood decoding, the quantized data y _t and the partial The distance of the response equalization expected value x _t is obtained, cumulative addition is performed, and the state transition is selected so as to always take the minimum value. The cumulative addition value at each time is called a metric value. This metric value is added to each state of the ^{L (l, m, n)} each time in the trellis diagram as _t t. Time t
In each of the states, the maximum likelihood state transition is selected from the possible state transitions from time t-1. Similarly, time t-1
Assuming that the value obtained as a result of sampling the reproduction signal with the timing signal extracted from the reproduction signal is quantized data y _t-1 , the state transition from time t-2 that can be taken in each state at time t-1 Of these, the most likely state transition is selected.

Therefore, in each state at time t, it is possible to select the most likely state transition among the possible state transitions from time t-2. Generally, in each state at time t, it is possible to select the maximum likelihood state transition among possible state transitions from time t-n (n is an integer of 1 or more).

An embodiment in which n = 2 will be described for simplification. As shown in FIG. 3, there were eight possible state transitions from time t-1 to time t.
Considering this for the state transition from the time t-2 to the time t, there are 12 state transitions as shown in FIG. Here, the state transition is defined as pathi (i is an integer from 0 to 11), and each state transition is defined as follows.

Metric value L of each state at time t-2
_{^{(1,1,1) t-2, L}} (1,1,0) t-2, L (1,0,0) t -2, L (0,1,1)
_t-2 , L ^(0,0,1) _t-2 , L ^(0,0,0) _t-2 , and the quantized data y _t at time t and the quantized data y _{t-1 at time t-1.} Is given, 6 of the 12 possible state transitions are selected.

Here, the state transition from the state L ^(1,1,1) _t-2 to L ^(1,1,1) _t is path 11, and the state L ⁽ 1,1,0 ⁾ _t-2 to L.
State transition to ^(1,1,1) _t is path 10, state transition from state L ⁽ 1,0,0 ⁾ _t-2 to L ^{(1,1,1 )} _t is path 9, state L ^{(0,0) , 0)} _t-2
State transition from path to L ^(1,1,0) _t is path 8, state L ^(0,0,1)
State transition from _t-2 to L ⁽ 1,0,0 ⁾ _t is path 7, state L
State transition from ^(0,0,0) _t-2 to L ⁽ 1,0,0 ⁾ _t is path 6, state L ^(1,1,1) _t-2 to L ^(0,0,1) _t State transition of path 5 and state transition of state L ^(1,1,0) _t-2 to L ^(0,1,1) _t of path 4,
^Path state transition from state L ^(1,1,1) _t-2 to L ^(0,0,1) _t
3, the state L ^(0,1,1) _t-2 from L ^{(0, 0,0)} to state transition to _t pa
th2, state transition from state L ^(0,0,1) _t-2 to L ^(0,0,0) _t
The state transition from path 1, state L ^(0,0,0) _t-2 to L ^(0,0,0) _t will be called path ⁰ .

In this way, the metric value is obtained every other time, and the maximum likelihood state transition is selected. The selection result is stored in a register having a predetermined length, and only one state transition sequence according to the trellis diagram in the time axis direction is obtained from the state transition sequences. This is the most likely state transition sequence, the so-called survivor path p _t . Original digital information b _t and b _t-1 from the surviving path p _t
Is uniquely obtained, and maximum likelihood decoding can be realized by an operation every other time.

FIG. 6 is a block diagram of the maximum likelihood decoding system of the present invention. The maximum likelihood decoding method of this embodiment is BMU1 and AC.
The quantized data input from the frequency divider 4 that divides the timing signal output from the S2 and SMU3 and the timing extraction unit by n and the quantized data input from the A / D conversion unit are output in accordance with the n-divided timing signal. It is composed of a parallel data converter 5.

The operation of the maximum likelihood decoding system of the present invention will be described in detail. Quantized data y _t , y _t-1 and eight partial response equalization expected values are input to the BMU. BM
The amplitude expected values of the eight partial response equalized outputs input to U are x _{i, t} (i is an integer from 0 to 7,
Further, t indicates time. ). In the present embodiment, the absolute value of the difference between the quantized data y _t , y _t-1 and the partial response equalization expected value x _{i, t} is branched as in (Equation 2) instead of the normally used two-sum. Calculate as a metric.

[0028]

[Equation 2]

The expected partial response equalization value x _{i, t} represents the amplitude value after partial response equalization when each state transition occurs in the response characteristic of the recording / reproducing system.
For example, in the case of ideal PR (1, 3, 3, 1) equalization,
x _{7, t} = 8, x _{3, t} = x _{6, t} = 7, x _{2, t} = x _{5, t} = 4, x
_{1, t} = x _{4, t} = 1, x _{0, t} = 0.

In each state at time t, a method for selecting the most likely state transition among the possible state transitions from time t-2 will be described. By using (Equation 2), (Equation 3) is obtained.

[0031]

(Equation 3)

[Mathematical formula-see original document] Here, if [Equation 2] is used in the same manner as the operator for selecting the one having the largest value of [alpha] and [beta], then [Equation 4] is obtained.

[0033]

(Equation 4)

Further, the difference M _{j, t} (j is an integer from 1 to 6) between the metric values in each state is defined as in (Equation 5).

[0035]

(Equation 5)

By substituting (Equation 3) and (Equation 4) into (Equation 5), (Equation 6) is obtained.

[0037]

(Equation 6)

FIG. 7 shows an embodiment of the maximum likelihood decoding system of the present invention.
2 is a block diagram of BMU1 in FIG. BMU1 is absolutely
It consists of a logarithmic value calculator and a subtractor (sub),
Data y_t, Y_t-1And partial response equalization output
Expected amplitude x_{i, t}Calculate the absolute value of the difference of
7) is calculated and the calculation result E01a,_t, E04a,_t, E14a,
_t, E20a,_t, E21a,_t, E32a,_t, E45a,_t, E56a,_t, E
57a,_t, E63a,_t, E73a, _t, E76a,_t, E01b,_t, E02
b,_t, E04b,_t, E12b,_t, E14b,_t, E20b,_t, E21b, _t,
E30b,_t, E31b,_t, E32b,_t, E45b,_t, E46b,_t, E47
b,_t, E56b,_t, E57b, _t, E63b,_t, E65b,_t, E73b,_t,
E75b,_t, E76b,_tTo ACS2.

[0039]

(Equation 7)

FIG. 8 is a block diagram of ACS2 in the embodiment of the maximum likelihood decoding system of the present invention. ACS2 includes an adder (add), a comparator (comp), and a selector (se).
l) and a register (reg).
Always stores the difference M _{j, t-2} (j is an integer from 1 to 6) in the metric value at time t-2 in the register, and is represented by (Equation 6) at time t. Input signal E01a,
_t , E04a, _t , E14a, _t , E20a, _t , E21a, _t , E32a, _t , E
45a, _t , E56a, _t , E57a, _t , E63a, _t , E73a, _t , E76
a, _t , E01b, _t , E02b, _t , E04b, _t , E12b, _t , E14b, _t ,
E20b, _t , E21b, _t , E30b, _t , E31b, _t , E32b, _t , E45
b, _t , E46b, _t , E47b, _t , E56b, _t , E57b, _t , E63b, _t ,
E65b, _t , E73b, _t , E75b, _t , E76b, _t and the difference in metric value between time t-2, M _{1, t-2} , M _{2, t-2} , M _{3, t-2} ,
From M _{4, t-2} , M _{5, t-2} , M _{6, t-2} , the difference of the metric values at time t by the calculation of (Equation 8) M _{1, t} , M _{2, t} , M _{3, t} ，
Find M _{4, t} , M _{5, t} , M _{6, t} .

At the same time as obtaining the difference between the metric values, the ACS 2 outputs to the SMU 3 as 12-bit information which 6 state transitions out of 12 state transitions have been selected. The 12-bit output signal is called the selection signal, and SELi
(I is an integer from 0 to 11). The ACS2 outputs the selection signal SELi to the SMU3 according to (Equation 8). However, HIGH in (Equation 8) indicates that the selection signal is at a high level, and LOW indicates that the selection signal is at a low level.

[0042]

(Equation 8)

FIG. 9 is a block diagram of the SMU 3 in the embodiment of the maximum likelihood decoding system of the present invention. The operation of the SMU 3 will be described in detail. The SMU 3 has a register of 12 × predetermined length (hereinafter referred to as path memory length m) (hereinafter referred to as path memory), and stores the state transition selection result in the path memory based on the selection signal input from the ACS 2. To do. Since twelve state transitions can occur, a register having a path memory length of m is prepared for each state transition. MEM _{i, j} (i is state transition path _i (i is 0
(Integer from 1 to 11), and for simplicity, only the integer i is added to the subscript.

Further, j indicates the address of the path memory, and 1
To the value of the path memory length m. ). SMU3
Is a logic circuit A (LogicA) and a logic circuit B (Log
icB), a logic circuit C (LogicC), and a register. Configuration diagrams of the logic circuits A, B, and C are shown in FIGS. 10A, 10B, and 10C, respectively. Logic circuit A is 4
A signal Y satisfying Y = A × (B + C + D) is output from the two inputs A, B, C and D. The symbol x represents a logical product, and the symbol + represents a logical sum. Further, the logic circuit B outputs a signal Y satisfying Y = A × (B + C) from the three inputs A, B and C.

The logic circuit C has two inputs A, B to Y.
The signal Y that satisfies = A × B is output. The logic circuit A, the logic circuit B, and the logic circuit C can remove from the path memory the state transition selection result at the time t and the time t + 2 that does not survive at the time t + 2 among the state transition selection results at the time t.

For example, assume that the selection signal is output as shown in Table 1 at time t, time t + 2, and time t + 4 in ACS2. Table 1 shows the input signal of the SMU 3 from time t to time t + 4.

[0047]

[Table 1]

However, "H" indicates that the signal is at high level, and "L" indicates that it is at low level.

[0049] SMU3 is a selection signal at time t is input, the path memory MEM _9,1 and MEM _{8, 1} and MEM _6,1 and MEM _5,1
"1" is stored in and MEM _3,1 and MEM _0,1 , and MEM _11,1 and MEM _10,1
"0" is stored in and MEM _7,1 and MEM _4,1 and MEM _2,1 and MEM _1,1 . Here, "1" indicates that the data stored in the register is at the high level, and "0" indicates that the data stored in the register is at the low level.

[0050] When the selection signal at time t + 2 is input, the path memory _{MEM 11,1, MEM 10,1, MEM 9,1} , MEM 8,1, ME
M _7,1 , MEM _6,1 , MEM _5,1 , MEM _4,1 , MEM _3,1 , MEM _2,1 , MEM
_The data stored in _1,1 , MEM _0,1 is stored in the path memory MEM
_11,2 , MEM _10,2 , MEM _9,2 , MEM _8,2 , MEM _7,2 , MEM _6,2 , MEM
_5,2 , MEM _4,2 , MEM _3,2 , MEM _2,2 , MEM _1,2 , MEM _0,2 stored in path memory MEM _11,1 and MEM _8,1 and MEM _6,1 and MEM _5,1 and MEM
'1' for _3,1 and MEM _0,1 , MEM _10,1 and MEM _9,1 and MEM _7,1 and ME
'0' is stored in M _4,1 and MEM _2,1 and MEM _1,1 .

When the selection signal is further input at time t + 4, the input A of the logic circuit A is the _data'of MEM _11,2 '.
It becomes 0 ', and the input B of the logic circuit A is the data of MEM _3,1 '.
1 ', and the input C of the logic circuit A is the data of MEM _5,1 '
1 ', the input D of the logic circuit A becomes the data' 1 'of MEM _11,1 and the output of the logic circuit A becomes Y =' 0 ', which is stored in MEM _11,3 .

Further, the input A of the logic circuit A becomes the data “0” of the MEM _10,2 , the input B of the logic circuit A becomes the data “1” of the MEM _3,1 and the input C of the logic circuit A becomes. , MEM _5,1 data becomes “1”, and the input D of the logic circuit A is MEM _11,1
Data becomes "1", and the output of the logic circuit A is Y = '
It becomes _0'and stored in MEM _10,3 . Further, the input A of the logic circuit A becomes the data “1” of MEM _9,2 , the input B of the logic circuit A becomes the data “1” of MEM _3,1 , and the input C of the logic circuit A becomes MEM _{5 , 1} data becomes “1”, the input D of the logic circuit A becomes MEM _11,1 data “1”, and the output of the logic circuit A becomes Y = “1”, which is stored in MEM _9,3 . To do.

Further, the input A of the logic circuit B becomes the data "1" of MEM _8,2 , the input B of the logic circuit B becomes the data "0" of MEM _4,1 , and the input C of the logic circuit B becomes. , MEM _10,1 data becomes "0", and the output of the logic circuit B is Y = "0".
_And stored in MEM _8,3 .

[0054] Also, the input A of the logic circuit C, data '0' next to MEM _{7, 2,} the input B of the logic circuit C, data '0' next to the MEM _9,1, the output of the logic circuit C, Y = '0', which is stored in MEM _7,3 .

Further, the input A of the logic circuit C becomes the data “1” of the MEM _6,2 , the input B of the logic circuit C becomes the data “0” of the MEM _9,1 and the output of the logic circuit C becomes Y = '0', which is stored in MEM _6,3 .

Further, the input A of the logic circuit C becomes the data “1” of MEM _5,2 , the input B of the logic circuit C becomes the data “0” of MEM _2,1 and the output of the logic circuit C becomes Y = '0', which is stored in MEM _5,3 .

Further, the input A of the logic circuit C becomes the data “0” of MEM _4,2 , the input B of the logic circuit C becomes the data “0” of MEM _2,1 , and the output of the logic circuit C becomes Y = '0', which is stored in MEM _4,3 .

Further, the input A of the logic circuit B becomes the data “1” of MEM _3,2 , the input B of the logic circuit B becomes the data “0” of MEM _1,1 and the input C of the logic circuit B becomes. , MEM _7,1 data becomes “0”, the output of the logic circuit B becomes Y = “0”, and this is stored in MEM _3,3 . Further, the input A of the logic circuit A becomes the data “0” of MEM _2,2 , the input B of the logic circuit A becomes the data “1” of MEM _0,1 , and the input C of the logic circuit A becomes MEM _{6. , 1} data “1”, the input D of the logic circuit A becomes MEM _8,1 data “1”, and the output of the logic circuit A becomes Y = “0”, which is stored in MEM _2,3 . To do.

Further, the input A of the logic circuit A becomes the data “0” of MEM _1,2 , the input B of the logic circuit A becomes the data “1” of MEM _0,1 and the input C of the logic circuit A becomes. , the data '1' next to the MEM _6,1, input D of the logic circuit a, the data '1' next to the MEM _{8, 1,} the output of the logic circuit a, Y = '0', and the which MEM _1, Store in ₃ .

Further, the input A of the logic circuit A becomes the data “1” of MEM _0,2 , the input B of the logic circuit A becomes the data “1” of MEM _0,1 , and the input C of the logic circuit A becomes , the data '1' next to the MEM _6,1, input D of the logic circuit a, the data '1' next to the MEM _{8, 1,} the output of the logic circuit a, Y = '0', and the this MEM _0, Store in ₃ .

By the above calculation, from time t to time t + 2
Path3, path5, path6, and pa among the state transitions
th8 was removed.

Further, the path memory MEM_11,1, MEM_10,1, MEM
_9,1, MEM_8,1, MEM_7,1, MEM_6,1, MEM_{Five , 1}, MEM_4,1, MEM
_3,1, MEM_2,1, MEM_1,1, MEM_0,1Data stored in
Pass memory MEM_11,2, MEM_10,2, MEM_9,2, MEM_8,2, MEM
_7,2, MEM_6,2, MEM_5,2, MEM_4,2, MEM_3,2, MEM_2,2, MEM
_1,2, MEM_0,2Stored in the path memory MEM_11,1And MEM_8,1And ME
M_7,1And MEM_5,1And MEM_3,1And MEM_1,1'1' to MEM_10,1And M
EM_9,1And MEM_6,1And MEM_4,1And MEM _2,1And MEM_0,1To '0'
To pay. Path memory MEM_{i, 3}(I is an integer from 0 to 12
MEM the operation in_{i, n}(N is 4 or more and path memory length or less
Also, if you do the
If yes, 12 path memories MEM_{i, m}(M is the path memory
'1' is stored in only one path memory
Will be.

This is the survival path. As described in the trellis diagram of FIG. 5, if “1” is stored in the path memory MEM _{3, m} or the path memory MEM _{8, m} , the SMU 3 outputs “10” as the decoding result and the path memory MEM. _{4, m} , path memory MEM _{5, m} , path memory MEM _{6, m} or path memory ME
If "1" is stored in M7 _{, m} , SMU3 outputs "01" as the decoding result, and if not, otherwise SMU3
Outputs "00" as the decoding result. As a result, the original digital information b _t-1 b _t is reproduced.

The SMU 3 has 12-bit information p _{i, t} (i is an integer from 0 to 11 and t is an integer indicating time) indicating a surviving path as p _{i, t} = MEM _{i, m} (m is a path memory length) )
Output to satisfy. BMU1, ACS2 and SMU
All three are half the frequency of the channel clock,
Since the configuration is such that they operate synchronously, the transfer rate of the digital information reproducing apparatus can be increased. In the SMU 3 according to the first embodiment of the present invention, the logic circuit A, the logic circuit B, and the logic circuit C survive the state transition selection result at the time t and the time t + 2 at the time t + 2 among the state transition selection results at the time t. Although the state transition that is not present is removed from the path memory, the state transition selection result from the time t to the time t + 2r (r is an integer of 1 or more) indicates that the state transition selection result at the time t survives from the time t + 2 to the time t + 2r. The same effect can be obtained by removing the state transition that is not present from the path memory.

In the first embodiment of the present invention, (Equation 2)
As described above, the absolute value of the difference between the quantized data y _t , y _t-1 and the partial response equalization expected value x _{i, t} was used as the branch metric, but the quantized data y _t , y _t-1 and the partial response etc. The same effect can be obtained even with the method in which the square of the difference between the coded expected values x _{i, t} is used as the branch metric. Further, in the first embodiment of the present invention, the time t is set in each state at the time t.
Although the method of selecting the maximum likelihood state transition from the possible state transitions from -2 is shown, generally, in each state at time t, the number of possible state transitions from time t-n (n is an integer of 1 or more) The same effect can be obtained even with the method of selecting the most likely state transition.

Next, an embodiment of the phase comparison circuit of the present invention will be described. FIG. 24 is a block diagram of the phase comparator of the present invention. The phase comparator is composed of a subtractor, a multiplier, a selector, a counter and a register. The quantized data y _t input from the A / D conversion means is input to the subtractor 100. The subtractor 100 obtains the difference between the input quantized data y _t and the slice level signal level set so that the DC component of the quantized data becomes zero. The calculation result of the subtractor 100 is stored in the register. Multiplier 10
1 performs multiplication represented by the calculation result y _t -level and register output value y _t-2 -level of the subtractor 100 (9), and outputs the multiplication result and its complement.

[0067]

[Equation 9]

The counter 102 resets the counter from the zero phase start signal input from the timing signal extraction means and counts the number of quantization times of the A / D conversion means. The count result count _t is output to the selector 103.
The selector 103 outputs the output signal of the multiplier 101 of (Equation 9), the selector output phase_error _{t-1 one} hour before, and the counter 1.
The counter value count _{t of} 02 is input, and the operation shown in (Equation 10) is performed. The calculation result is the phase error information phase_error _t
Is stored in the register.

[0069]

(Equation 10)

Next, the operation of the phase comparator will be described in detail. FIG. 25 is a timing chart of the phase comparator of the present invention. In the timing signal extraction means, FIG.
25 (c), a VCO output as shown in FIG. 25 (b) is obtained according to the timing of the zero phase start signal of FIG. 25 (c) and the zero phase slice level. It is assumed that the conversion unit quantizes the reproduction signal and obtains quantized data.

FIG. 25D shows the output signal of the subtractor 100,
FIG. 25 (e) shows the output signal of the register. Fig. 25 from the rising edge of the zero phase start signal
The counter reset signal of (f) is generated to synchronously reset the counter. The output count _{t of the} counter 102 is as shown in FIG. The selector 103 selects three signals based on the counter output value count _t and outputs them to the register. The output result is shown in FIG. FIG.
Quantized data y _t is shown in (a). If there is no shift of the phase of the timing signal, when the output S _t of the subtractor 100 is t = 4j + 3 (j is an integer of 0 or more), since zero, phase error information of the phase comparator output phase_erro
r _t always has a value of zero.

Consider the case where the phase of the VCO output signal of the timing extraction means is delayed as shown in FIG. The output S _t of the subtractor 100 does not become zero when t = 4j + 3 (j is an integer of 0 or more), and the phase error information phase_error _t of the phase comparator output always takes a negative value. Similarly, FIG.
Consider the case where the phase of the VCO output signal of the timing extraction means is advanced as in (l). Output S of subtractor 100
_{When t} = 4j + 3 (j is an integer of 0 or more), _t does not become zero, and the phase error information phase_error _t of the phase comparator output always takes a positive value.

Therefore, when a specific recording pattern is reproduced, the phase error information can be extracted from the quantized data obtained by quantizing the reproduced signal. This phase error information phase_
The sign of error _t indicates the lead or lag of the phase of the timing signal, and the absolute value of the phase error information phase_error _t indicates the absolute value of the phase shift of the timing signal.

In the present embodiment, the case where the recording pattern is a single signal having a frequency of ⅛ of the channel clock as the fundamental wave is shown. However, by changing the configuration of the phase comparator according to the recording pattern. The phase error information can be detected from the quantized data regardless of the recording pattern.

Next, a first embodiment of the digital information reproducing apparatus of the present invention will be described. FIG. 11 is a block diagram of a digital information reproducing apparatus of the present invention. The reproduction signal reproduced from the recording medium is sampled at the timing signal input by the A / D conversion means 6 and quantized data is output. The maximum likelihood decoding means 7 estimates the maximum likelihood state transition from the input quantized data, reproduces the original digital information, and outputs it. Further, the maximum likelihood decoding means 7 outputs the amount of phase error from the decoding result to the timing signal extraction means 8. The timing signal extraction means 8 calculates the oscillation frequency from the phase error amount and outputs the timing signal to the A / D conversion means 6.
The operation of the timing extracting means 8 of the digital information reproducing apparatus will be described in detail.

FIG. 12 is a block diagram of the timing signal extracting means 8 of the first embodiment of the digital information reproducing apparatus of the present invention. The center frequency control signal sets the center frequency of the VCO 9, and the amplification factor control signal sets the gain of the VCO 9. The comparator 10 converts the input reproduction signal into a binary value at the comparator slice level,
Output to the O control circuit 11. The VCO control circuit 11 outputs a zero phase start signal for oscillating the VCO to the VCO 9 in accordance with the phase detected by the comparator 10 from the read gate and the binary conversion result. D / A converter 12
Converts the input phase error amount into an analog signal.
The VCO 9 changes the oscillation frequency based on the output signal of the D / A converter 12 and outputs the timing signal to the A / D conversion means 6 and the maximum likelihood decoding means 7. Next, the timing extraction means 8
The operation in the time direction will be described.

When reproducing original digital information from a normal recording medium, for example, the rotational speed of a disk or the relative speed of a tape and a head of a tape varies. A continuous repetitive pattern is recorded on the recording medium so that the original digital information can be surely reproduced even if there is such a variation. An area in which such a repeating pattern is recorded is called a VFO area. The operation will be described for the case where a single signal having a frequency of 1/8 of the channel clock is recorded in the VFO area.

FIG. 13 shows a timing chart of the timing signal extracting means 8 of the digital information reproducing apparatus of the present invention. FIG. 13A shows a reproduced signal in the VFO area. When the read gate (Fig. 13 (c)) is not valid,
The VCO output (FIG. 13B) is locked to the recording clock. Further, the VCO control circuit 11 invalidates the zero phase start signal (FIG. 13 (e)). When the read gate becomes valid, the VCO control circuit 11 stops the VCO oscillation and outputs a zero phase start signal so that the VCO 9 oscillates in accordance with the phase detected by the comparator 10. The VCO 9 starts oscillation at the rising edge of the zero phase start signal.

The timing extraction means 8 is the A / D conversion means 7.
To the A / D conversion means (see FIG. 1).
3 (f)) is obtained. Timing extraction means 8 is VFO
Since the VCO 9 is oscillated in accordance with the phase information detected from the reproduction signal in the area, the oscillation output of the VCO does not include a phase error at the start of oscillation, and a reliable synchronous operation can be obtained. The operation of the maximum likelihood decoding means 7 in the first embodiment of the digital information reproducing apparatus will be described in detail. For simplicity, in each state at time t, a method of selecting the most likely state transition among possible state transitions from time t-1 will be described.

FIG. 14 is a block diagram of the maximum likelihood decoding means 7 of the first embodiment of the digital information reproducing apparatus of the present invention. The quantized data input from the A / D conversion means 6 is B
It is input to the MU 13 and the REG 14. The BMU 13 calculates the branch metric and outputs it to the ACS 16. ACS
16 selects six probable state transitions from the branch metric and the metric value one hour before, and outputs them to the SMU 17. The SMU 17 stores the state transition selection result for a predetermined length and removes the selection result that does not follow the state transition rule. As a result, a surviving path is obtained and output to the LPF 1 ”5.
The REG 14 outputs the quantized data y _t delayed by the shift register by the processing time of the BMU 13, ACS 16 and SMU 17, to the LPF 15. The LPF 15 averages the quantized data according to the surviving path,
The obtained average value is output to the BMU 13 as an expected partial response equalization value.

Further, the LPF 15 obtains the phase error information from the average value and uses this for the digital loop filter (hereinafter D
Output to 18). The DLF 18 obtains a phase error amount that determines the oscillation frequency of the timing extraction means 8.
The operation of each block will be described. FIG. 15 shows the BMU 13 of the maximum likelihood decoding means 7 of the digital information reproducing apparatus of the present invention.
FIG. Quantized data y is stored in the BMU 13.
_{The t} and eight expected partial response equalization values from the LPF 15 are input. The amplitude expected values of the eight partial response equalized outputs input to the BMU 13 are set to x _{i, t} (i
Represents an integer from 0 to 7, and t represents time. ). As in (Equation 2), the absolute value of the difference between the quantized data y _t and the partial response equalization expected value x _{i, t} is calculated as a branch metric. From (Equation 2), (Equation 3), (Equation 4), (Equation 11) is obtained.

[0082]

[Equation 11]

Further, substituting (Equation 7) into (Equation 12)
Is obtained.

[0084]

(Equation 12)

FIG. 16 shows a block diagram of the ACS 16 of the maximum likelihood decoding means 7 of the digital information reproducing apparatus of the present invention. A
In CS16, the metric value M _{i, t-1} (i is an integer from 1 to 6) one hour before and the output signal E01a, _t , E0 of the BMU.
4a, _t , E14a, _t , E20a, _t , E21a, _t , E32a, _t , E45
From a, _t , E56a, _t , E57a, _t , E63a, _t , E73a, _t , E76a, _t (Equation 12) Therefore, the metric value at the time t is obtained, and six possible state transitions among eight state transitions are obtained. Is selected and the selection result is output to the SMU 17.

The ACS 16 selects 6 probable state transitions out of the 8 possible state transitions each time from the certainty of each state one hour before. When the read gate becomes valid in the VFO area, the timing signal extracting means 8 oscillates the VCO in accordance with the detected phase, so that the first quantized data y ₀ at which the read gate becomes valid is sent to the maximum likelihood decoding means 7. When input, the metric value M _{i, -1} (i is an integer from 1 to 6) must be set. Since a fixed pattern is recorded in the VFO area, the quantized data y _i (i is an integer of -1 or less) can be estimated.

Therefore, by setting the metric value at the time t = −1 based on the estimated quantized data y _i , a reliable maximum likelihood decoding result can be obtained with an SMU having a small memory length. Next, a method of setting the metric value at time t = −1 will be described. In the VFO area, a single signal of 1/8 of the channel clock is recorded, and before the time t = 0, ideal PR (1,
3, 3, 1) Assume that equalized quantized data has been input. FIG. 17 shows an operation schematic diagram of the maximum likelihood decoding means of the first embodiment of the digital information reproducing apparatus of the present invention.

FIG. 17A shows a partial response equalized reproduction signal in the VFO area. When this reproduced signal is quantized by the A / D conversion means 6, FIG.
The quantized data of (c) is obtained. When this is input to the maximum likelihood decoding means 7, a trellis diagram as shown in FIG. 17 (d) is obtained. The solid line indicates the state transition selected by the ACS 16. The broken line shows the state transition that the ACS 16 has not selected. The thick solid line indicates the survival path estimated by SMU17. Assuming that the reproduced signal before time t = −1 is also quantized by the A / D conversion means 7 and the quantized data is obtained by the A / D conversion means 7 as shown in FIG. The maximum likelihood decoding result as shown in (f) is obtained. The quantized data S _t takes the value of (Equation 13).

[0089]

(Equation 13)

Next, in FIG. 17 (f), time t =-
1 in each state S (1,1,1), S (1,1,0), S (1,0,0),
The metric value of S (0,1,1), S (0,0,1), S (0,0,0) is estimated, and the initial value is set in the register. Attention is paid to the area surrounded by the broken line in FIG. FIG. 18 is an enlarged view of FIG. State S (1,1, at time t = -1
Considering 0), it is on the state transition sequence estimated by the maximum likelihood decoding means 7. Further, since ideal partial response equalization is performed before time t = −1, each state on the surviving path is always the most probable, and in the embodiment, the metric value is always 0.

Next, at the time t = -1, the state S (1,1,
Considering 1), the maximum-likelihood decoding means 7 is shown in FIG.
The state S at time t = −1 is obtained by cumulatively adding the branch metric values indicated by the thick broken line as in (b).
It becomes the metric value of (1,1,1). Similarly, considering the state S (1,0,0) at time t = −1, the maximum likelihood decoding means 7 cumulatively adds each branch metric value indicated by a thick broken line as shown in FIG. Is the metric value of state S (1,0,0) at time t = -1. Similarly, considering the state S (0,1,1) at time t = -1,
In the maximum likelihood decoding means 7, as shown in FIG. 18 (d), the cumulative addition of each branch metric value indicated by the thick broken line becomes the metric value of the state S (0,1,1) at time t = -1. . Similarly, considering the state S (0,0,1) at the time t = −1, the maximum likelihood decoding means 7 cumulatively adds the branch metric values indicated by the thick broken line as shown in FIG. Is the metric value of state S (0,0,1) at time t = -1. Similarly, state S at time t = -1
Considering (0,0,0), the maximum likelihood decoding means 7 uses
8 (f) is a state S at time t = −1 obtained by cumulatively adding the branch metric values indicated by the thick broken line.
The metric value is (0,0,0). The branch metric and the addition result at each time are shown in (Table 2).

[0092]

[Table 2]

Therefore, the difference in the metric of each state at time t = −1 is obtained from (Equation 2), and time t = −
By setting the value of (Equation 14) in 1 in the register, the SMU 17 can quickly estimate the surviving path and shorten the memory length. Further, in the first embodiment of the digital information reproducing apparatus, the quantized data y _t , y _t−1 and the partial response equalization expected value x are expressed as in (Equation 2).
_Although the absolute value of the difference between _{i and t} is used as the branch metric, it is a method in which the square of the difference between the quantized data y _t and y _t-1 and the partial response equalization expected value x _{i, t} is used as the branch metric. Also has the same effect.

The same effect can be obtained by obtaining the metric difference in each state at time t = -1 in the same procedure according to the recording pattern of the VFO area and the partial response equalization method and setting it as the initial value. .

[0095]

[Equation 14]

FIG. 19 shows a block diagram of the SMU 17 of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention. SM
In U17, the logic circuit A and the logic circuit B allow the ACS1
From the state transition selection results at time t and time t + 1 obtained in step 6, the state transitions that do not survive at time t + 1 among the state transition selection results at time t are removed from the path memory according to the state transition rule of FIG. As a result, a survivor path is obtained, and the survivor path is output to the LPF 15.

FIG. 20 shows a block diagram of the LPF 15 of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention. LP
F15 performs an operation satisfying (Equation 15) according to the survival path Pi, t (i is an integer from 0 to 7) of the SMU 17, and stores the operation result in each register. The calculation result is B
It is output to the MU 13 as a partial response equalization expected value.

If the survivor path Pi, t is HIGH,

[0099]

(Equation 15)

If the surviving path Pi, t is LOW, Xi,
t-1 = Xi, t (i is an integer from 0 to 7) Further, the LPF 15 performs an operation for satisfying (Equation 16) as the phase error information phase_error _t , and outputs it to the DLF 18.

[0101]

(Equation 16)

FIG. 21 shows a block diagram of the DLF 18 of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention. DL
F18 is composed of two multipliers, two adders and a register. Phase error information ph input from the LPF 15
Based on the (number 17) from ase_error _t phase error amount VCOCTL _t
Ask for. This is output to the timing extraction means 8.

[0103]

[Equation 17]

Next, a second embodiment of the digital information reproducing apparatus will be described. The second embodiment is shown in FIG.
The configuration is the same as that of the first embodiment. Since the A / D conversion means and the timing signal extraction means operate in the same manner, the maximum likelihood decoding means of the second embodiment will be described here. 22 is a block diagram of the maximum likelihood decoding means of the second embodiment of the digital information reproducing apparatus of the present invention. The quantized data input from the A / D conversion means 6 is input to the BMU 19, the REG 20, and the phase comparator 21. The BMU 19 calculates the distance between the partial response equalization expected value and the quantized data, and outputs the distance to the ACS 22. AC
In S22, a probable state transition is selected from the state transitions that can be taken from the metric value one hour before and the branch metric, and the metric value of each state is obtained and stored in the register. The ACS 22 also outputs the state transition selection result to the SMU 23.

According to the state transition rule, the SMU 23 removes a state transition sequence that is no longer consistent and estimates a surviving path. Decode the original digital information from the surviving path. The SMU 23 outputs the surviving path to the LPF 24. The REG 20 inputs the quantized data into the BMU.
The data is stored in the register only for the processing time required by 19, the ACS 22, and the SMU 23, and the quantized data is output to the LPF 24. The LPF 24 smoothes the quantized data according to the survivor path, and outputs the partial response equalization expected value to the selector 25 and the phase error information to the selector 26.

The phase comparator 21 obtains phase error information from the quantized data and outputs it to the selector 26. Counter 2
When the zero phase start signal is input from the timing signal extraction means 7, the counter 7 resets the counter value and counts the number of quantized data. When it is time to complete the pull-in operation of the phase-locked loop, a selection signal is output to the selector 25, the selector 26, and the DLF 28. Selector 2
Reference numeral 5 selects a partial response equalization initial expected value as a partial response equalization expected value during the PLL pull-in operation, outputs it to the BMU 19, and selects the partial response equalization expected value output from the LPF 24 when the PLL pull-in is completed. Feedback to BMU19.

The selector 26 receives the phase error information output from the phase comparator 21 as DL during the pull-in operation of the PLL.
Output to F28, and when the pulling of PLL is completed, LPF
The phase error information output from 24 is output to the DLF 28. The DLF 28 sets the values of the coefficients α and β of (Equation 17) so that the loop gain becomes high during the PLL pull-in operation, and sets the values of α and β so that the loop gain becomes low when the PLL pull-in operation is completed. PL in VFO area
Phase comparator 21 which takes a short processing time in the L pull-in operation
By using the phase error information of 1 and further increasing the loop gain, it is possible to shorten the PLL pull-in operation time and widen the capture range.

When reproducing valid data, the LP
By using the phase error information using the maximum likelihood decoding result output from F24 and further lowering the loop gain, the possibility of loss of lock can be suppressed even if the quality of the reproduced signal deteriorates.

Next, a third embodiment of the digital information reproducing apparatus will be described. The third embodiment is shown in FIG.
The configuration is the same as that of the first embodiment. Since the A / D conversion means and the timing signal extraction means operate in the same manner, the maximum likelihood decoding means of the third embodiment will be described here. FIG. 23 is a block diagram of the maximum likelihood decoding means of the third embodiment of the digital information reproducing apparatus of the present invention. The quantized data input from the A / D conversion means 6 is input to the BMU 29, REG 30, and REG 31. B
The MU 29 obtains the distance between the partial response equalization expected value and the quantized data, and outputs it to the ACS 32.

In the ACS 32, a probable state transition is selected from the state transitions that can be taken from the metric value one hour before and the branch metric, and the metric value of each state is obtained and stored in the register. Further, the ACS 32 outputs the state transition selection result to the SMU 33 and SMU 34. The SMU 33 and the SMU 34 remove the inconsistent state transition series according to the state transition rule to estimate the surviving path. However, SMU33 has a short path memory length, and SMU3
4 has a long path memory length. SMU33
And SMU 34 decodes the original digital information from the surviving path.

The SMU 33 and SMU 34 output the survivor paths to the LPF 35 and LPF 36, respectively. REG3
0 is the input quantized data BMU29 and ACS32
Then, the processing time required by the SMU 33 is stored in the register and the quantized data is output to the LPF 35. Similarly, RE
G31 inputs the quantized data to BMU29 and ACS
The data is stored in the register only for the processing time required by 32 and SMU 34, and the quantized data is output to LPF 36. LPF
Reference numeral 35 smoothes the quantized data according to the surviving path, and outputs phase error information to the selector 38. LP
F36 smoothes the quantized data according to the survivor path, and outputs the partial response equalization expected value to the selector 37 and the phase error information to the selector 38. The counter 39 resets the counter value when the zero phase start signal is input from the timing signal extraction means,
Count the number of quantized data. When it is time to complete the pull-in operation of the phase-locked loop, a selection signal is output to the selector 37, the selector 38, and the DLF 40.

During the PLL pull-in operation, the selector 37 selects the partial response equalization initial expected value as the partial response equalization expected value and outputs it to the BMU 29. When the PLL pull-in is completed, the partial response equalization output from the LPF 36 is completed. Select expected value and select BMU2
Give feedback to 9. The selector 38 outputs the phase error information output from the LPF 35 to the DLF 40 during the PLL pull-in operation, and outputs the phase error information output from the LPF 36 to the DLF 40 when the pull-in of the PLL is completed.
Output to The DLF 40 sets the values of the coefficients α and β of (Equation 17) so that the loop gain becomes high during the PLL pull-in operation, and sets the values of α and β so that the loop gain becomes low when the PLL pull-in operation is completed. By using the phase error information of the loop having a short processing time in the PLL pull-in operation in the VFO area and further increasing the loop gain, the PLL pull-in operation time can be shortened and the capture range can be widened. Further, when reproducing valid data, the phase error information output from the LPF 36 is used, and the loop gain is further lowered, so that the possibility of lock release is suppressed even if the quality of the reproduced signal is deteriorated.

[0113]

According to the present invention, the maximum likelihood decoding system is a BMU for obtaining a distance between n quantized data and a partial response equalization expectation value, a branch metric input from the BMU, and each n time before. Performs an addition operation with a metric value indicating the certainty of the state, compares the results, and selects a probable state transition from possible state transitions at each time,
An ACS that outputs the selected result to the SMU and a certain length of certain state transitions are stored, and the state transition sequence in which the transition cannot continue in the time axis direction is eliminated in accordance with the rule determined by partial response equalization and survives. The SMU for outputting a path is provided, and the synchronous operation is performed at a frequency of 1 / n of the channel clock, so that the transfer rate of the digital information reproducing apparatus can be increased.

Further, in the digital information reproducing apparatus, when the gate signal indicating the start timing of the signal processing by the timing signal extracting means becomes effective, the timing is set in advance at the moment when the reproducing signal reaches the preset threshold value. Generate a timing signal at the center frequency, and from the maximum likelihood decoding means,
Alternatively, the frequency of the timing signal is changed based on the amount of phase error output from the phase comparison means, the preset amplification factor control signal, and the center frequency control signal.

Further, the maximum likelihood decoding means has path memories of different lengths, different phase error information is obtained from different surviving path information, and the gate signal indicating the signal processing start timing of the timing signal extracting means becomes effective. The phase error information is selected from the output value of the counter circuit that counts the number of times the A / D conversion unit quantizes the reproduction signal from the time point, the phase error amount is obtained, and the phase error amount is output to the timing signal extraction unit. Further, the maximum likelihood decoding means determines the maximum value according to the output value of the counter circuit that counts the number of times the A / D converting means quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the timing signal extracting means becomes valid. The phase error information of the likelihood decoding means and the phase error information of the phase comparison means are selected to obtain the phase error amount, and the phase error amount is output to the timing signal extraction means. Further, the timing signal extraction means digitally outputs the output value of the counter circuit which counts the number of times the A / D conversion means quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the timing signal extraction means becomes valid. The loop filter coefficient is changed.

The timing signal extracting means counts the number of times the A / D converting means quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the timing signal extracting means becomes valid, and the timing signal extracting means counts a predetermined value. And the partial response equalization expected value used in the branch metric calculation of the maximum likelihood decoding means is switched from the fixed partial response equalization initial expected value to the partial response equalization expected value detected by the maximum likelihood decoding means. did.

Also, one time before the gate signal becomes valid, the first quantized data is input from the A / D conversion means to the maximum likelihood decoding means, and the calculation is started in the ACS in the maximum likelihood decoding means, The metric value indicating the certainty of each state is initially set to a predetermined value. With such a configuration, by using the phase error information having a short processing time in the PLL pull-in operation in the VFO area and further increasing the loop gain, the PLL pull-in operation time can be shortened and the capture range can be widened. Also, when reproducing valid data, phase error information using the maximum likelihood decoding result is used, and the loop gain is further lowered, so that even if the quality of the reproduced signal deteriorates, the possibility of lock loss is kept low. To be

In the phase comparison method, the reproduction signal in the area in which a specific original digital information pattern is recorded is quantized, and a subtracter for subtracting the quantized data and a predetermined value, and a shift for storing the subtracter output. A register, a multiplier that multiplies the output value of the shift register by the output value of the subtractor, a register that stores the output of the multiplier, a counter circuit that counts the number of input quantized data, and the multiplication It is equipped with a selector circuit for selecting the output of the counter and the output of the register according to the output value of the counter circuit, and phase error information can be extracted from the quantized data, and a digital phase-locked loop with a wide capture range can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a conventional maximum likelihood decoding system.

FIG. 2 is a diagram showing a configuration example of a conventional path feedback maximum likelihood decoding system.

FIG. 3 shows a recording code having a minimum polarity reversal distance of 3 and PR (1,
3, 3, 1) State transition diagram when equalization methods are combined

FIG. 4 shows a recording code having a minimum polarity reversal distance of 3 and PR (1,
3, 3, 1) Trellis diagram when equalization methods are combined

FIG. 5 is a trellis diagram of the maximum likelihood decoding system of the present invention.

FIG. 6 is a block diagram of an embodiment of a maximum likelihood decoding system of the present invention.

FIG. 7B in the embodiment of the maximum likelihood decoding system of the present invention
Block diagram of MU

FIG. 8 A in the embodiment of the maximum likelihood decoding system of the present invention
Block diagram of CS

FIG. 9 shows S in the embodiment of the maximum likelihood decoding system of the present invention.
Block diagram of MU

FIG. 10 is a configuration diagram of logic circuits A, B, and C.

FIG. 11 is a block diagram of a digital information reproducing apparatus of the present invention.

FIG. 12 is a block diagram of a timing signal extracting means of the digital information reproducing apparatus of the present invention.

FIG. 13 is a timing chart of the timing signal extracting means of the digital information reproducing apparatus of the present invention.

FIG. 14 is a block diagram of maximum likelihood decoding means of the first embodiment of the digital information reproducing apparatus of the present invention.

FIG. 15 is a block diagram of the BMU of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention.

FIG. 16 is a block diagram of ACS of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention.

FIG. 17 is an operation schematic diagram of the maximum likelihood decoding means of the first embodiment of the digital information reproducing apparatus of the present invention.

FIG. 18 is an enlarged view of the operation schematic diagram of the maximum likelihood decoding means of the first embodiment of the digital information reproducing apparatus of the present invention.

FIG. 19 is a block diagram of the SMU of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention.

FIG. 20 is a block diagram of the LPF of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention.

FIG. 21 is a block diagram of the DLF of the maximum likelihood decoding means of the digital information reproducing apparatus of the present invention.

FIG. 22 is a block diagram of maximum likelihood decoding means of the second embodiment of the digital information reproducing apparatus of the present invention.

FIG. 23 is a block diagram of maximum likelihood decoding means of the third embodiment of the digital information reproducing apparatus of the present invention.

FIG. 24 is a block diagram of a phase comparator of the present invention.

FIG. 25 is a timing chart of the phase comparator of the present invention.

[Explanation of symbols]

 1 Branch metric unit 2 Addition / comparison / selection unit 3 Survival memory unit 4 Minute period 5 Parallel data converter 6 A / D conversion means 7 Maximum likelihood decoding means 8 Timing signal extraction means 9 VCO 10 Comparator 11 VCO control circuit 12 D / A conversion Device 13 Branch metric unit 14 Shift register 15 Low-pass filter 16 Addition comparison selection unit 17 Survival memory unit 18 Digital loop filter 19 Branch metric unit 20 Shift register 21 Phase comparator 22 Addition comparison selection unit 23 Survival memory unit 24 Low pass filter 25 Selector 26 Selector 27 Counter 28 Digital loop filter 29 Branch metric unit 30 Shift register 31 Shift register Star 32 Addition / comparison / selection unit 33 Survival memory unit 34 Survival memory unit 35 Low-pass filter 36 Low-pass filter 37 Selector 38 Selector 39 Counter 40 Digital loop filter 100 Subtractor 101 Multiplier 102 Counter 103 Selector

Claims (8)

[Claims] 1. A maximum likelihood decoding apparatus for reproducing original digital information recorded on a recording medium by using a partial response equalization system, wherein a reproduced signal reproduced from the recording medium is a timing signal from a timing signal extracting means. A / D conversion means for converting into quantized data sampled in
Parallel data conversion means for outputting n quantized data output from the A / D conversion means, maximum likelihood decoding means for decoding original digital information based on the quantized data, and timing signal extraction means. Maximum-likelihood decoding apparatus, comprising: a frequency dividing unit that divides the timing signal output from the unit into 1 / n, and the timing signal extracting unit that extracts and outputs the timing signal included in the reproduction signal. . 2. An A / D conversion means for converting a reproduction signal from a recording medium into quantized data, and a maximum likelihood decoding for decoding the original digital information with the quantized data output from the A / D conversion means as an input. Means and a timing signal extraction means for generating a timing signal used in the A / D conversion means based on the phase error amount output from the maximum likelihood decoding means When the gate signal indicating the start timing of the signal processing by the means becomes valid, at the moment when the reproduction signal reaches the preset threshold value, based on the preset amplification factor control signal and center frequency control signal, A timing signal is generated, and the frequency of the timing signal is determined based on the phase error amount output from the maximum likelihood decoding means and a preset timing signal control signal. A digital information reproducing apparatus characterized by changing the wave number. 3. A / D conversion means for converting a reproduced signal from a recording medium into quantized data, and maximum likelihood decoding for decoding the original digital information with the quantized data output from the A / D conversion means as an input. Means and the timing signal extracting means generate a timing signal at a preset center frequency at the moment when the reproduction signal amplitude reaches a preset threshold when the gate signal indicating the signal processing start timing becomes valid. A digital signal having timing signal extraction means for generating a timing signal with an oscillation frequency changed based on the phase error amount output from the maximum likelihood decoding means, a preset amplification factor control signal and a center frequency control signal. In the information reproducing apparatus, the gate signal becomes valid, the first quantized data is input from the A / D conversion means to the maximum likelihood decoding means, and A digital information reproducing apparatus characterized in that a metric value indicating the certainty of each state one time before is initialized to a predetermined value by the time the calculation is started in the addition comparison selector in the maximum likelihood decoding means. . 4. An A / D conversion means for converting a reproduction signal from a recording medium into quantized data, and a maximum likelihood decoding for decoding the original digital information with the quantized data output from the A / D conversion means as an input. Means and the timing signal extracting means generates a timing signal at a preset center frequency at the moment when the reproduction signal reaches a preset threshold when the gate signal indicating the start timing of signal processing becomes valid, In a digital information reproducing apparatus including the timing signal extracting means for changing the frequency of the timing signal based on the phase error amount output from the maximum likelihood decoding means, the preset amplification factor control signal and the center frequency control signal. , The maximum-likelihood decoding means have path memories of different lengths, and obtain different phase error information from different surviving path information. The phase error information is selected by the output value of the counter circuit that counts the number of times the A / D conversion means quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the ming signal extraction means becomes valid. A digital information reproducing apparatus characterized in that an error amount is obtained and outputted to the timing signal extracting means. 5. A / D conversion means for converting a reproduced signal from a recording medium into quantized data, and maximum likelihood decoding for decoding the original digital information with the quantized data output from the A / D conversion means as an input. Means, phase comparing means for obtaining phase error information using the quantized data output from the A / D converting means as input, and timing signal extracting means that is preset when the gate signal indicating the start timing of signal processing becomes valid. The timing signal is generated at the preset center frequency at the moment when the reproduction signal reaches the threshold value, and based on the detected phase error amount, preset amplification factor control signal and center frequency control signal. In the digital information reproducing apparatus provided with the timing signal extracting means for changing the frequency of the timing signal, the maximum likelihood decoding means includes the timing signal From the time when the gate signal indicating the signal processing start timing of the extraction means becomes valid, the A /
The phase error amount is determined by selecting the phase error information of the maximum likelihood decoding means and the phase error information of the phase comparison means according to the output value of the counter circuit that counts the number of times the D conversion means quantizes the reproduced signal, and the timing signal is obtained. A digital information reproducing device characterized by outputting to an extracting means. 6. A / D conversion means for converting a reproduction signal from a recording medium into quantized data, and maximum likelihood decoding for decoding the original digital information with the quantized data output from the A / D conversion means as an input. And a timing signal extracting means for generating a timing signal at a preset center frequency at the moment when the reproduction signal reaches a preset threshold when the gate signal indicating the start timing of signal processing becomes valid. In a digital information reproducing apparatus having the timing signal extracting means for changing the frequency of the timing signal based on the detected output phase error amount, preset amplification factor control signal and center frequency control signal,
The output value of the counter circuit that counts the number of times the A / D conversion unit quantizes the reproduction signal from the time when the gate signal indicating the signal processing start timing of the timing signal extraction unit becomes valid in the maximum likelihood decoding unit. A digital information reproducing apparatus characterized in that the coefficient of a digital loop filter is changed by. 7. A / D conversion means for converting a reproduction signal from a recording medium into quantized data, and maximum likelihood decoding for decoding the original digital information with the quantized data output from the A / D conversion means as an input. Means and the timing signal extraction means generate and detect a timing signal at a preset center frequency at the moment when the reproduction signal reaches a preset threshold when the gate signal indicating the signal processing start timing becomes valid. In the digital information reproducing apparatus provided with the timing signal extracting means for changing the frequency of the timing signal based on the phase error amount and the preset amplification factor control signal and the center frequency control signal, the timing signal extracting means comprises: The A / D conversion is started from the time when the gate signal indicating the signal processing start timing of the timing signal extraction means becomes valid. The means counts the number of times the reproduced signal is quantized, and when a predetermined value is reached, the partial response equalization expected value used in the branch metric calculation of the maximum likelihood decoding means, from the fixed partial response equalization initial expected value, A digital information reproducing apparatus characterized by switching to a partial response equalization expected value detected by the maximum likelihood decoding means. 8. A subtracter for quantizing a reproduction signal of an area in which a specific original digital information pattern is recorded, and subtracting the quantized data and a predetermined value, a shift register for storing an output of the subtractor, and A multiplier that multiplies the output value of the shift register and the output value of the subtractor, a register that stores the output of the multiplier, a counter circuit that counts the number of input quantized data, and an output of the multiplier. A phase comparator comprising a selector circuit for selecting an output of the register according to an output value of a counter circuit.