JPH09288870A - Data decoding device and method and data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a memory capacity for decoding and also to rapidly access an objective data to be read out. SOLUTION: In the device 50 and its method for decoding a coded data S2 recorded on a recording medium, the coded data S2 read out of the recording medium is stored in a memory 51 for decoding. At this time, data information about a data to be a read-out object is detected from a decoded data generated in the midst of decoding the coded data S2, this data information is stored in a data information storage means, and also an output of the decoded data S10 is controlled based on the data information. Thus, independently of decoding of the coded data S2, the output of the decoded data S10 is controlled based on the data information.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIGS. 53 to 57) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 52) (1) First Example (FIGS. 1 to 20) (1-1) Overall configuration of data reproducing apparatus (FIG. 1) (1-2) ECC circuit and ECC decoding (FIGS. 2 to 9) (1-3) Sector detection (FIGS. 10 to 20) (2) Second embodiment (2-1) Recorded data format (FIGS. 21 to 24) (2-2) Data reproducing device and ECC decoding (FIGS. 1 and 2)
5 to 52) (2-3) Operations and effects of the second embodiment (FIGS. 43 to 4)
5) (3) Other Examples Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding apparatus, a method therefor, and a data reproducing apparatus, and is suitable for use in, for example, reproducing a moving image that has been digitalized and recorded on a disk.

[0003]

2. Description of the Related Art Conventionally, for example, MPEG (Moving Pictures Ex
pert Group) There is a disk in which moving images according to the standard are digitalized and recorded at a variable rate. The MPEG used here is an I-picture (Intra-Picture) that is an intra-frame coded image for image data, and a P-picture (Predictive-Pictur) that is an inter-frame forward prediction coded image.
e), B picture (Bidirect)
Ionally predictive-Picture) is defined as three types, and the screen group structure GOP (Group Of
Pictures)). Similarly, the MPEG standard is applied to audio data, but for audio data other than MPEG, for example, ATRAC (Aditive TRansfor
m Acoustic Coding) for digitalization and compression coding. ATRAC is a trademark.

FIG. 53 shows a data decoding device 1 for reproducing data recorded on a disk at a variable rate. The data decoding device 1 irradiates the data recorded on the optical disk 2 with a laser beam by means of a pickup 3, and reproduces it from the reflected light. Playback signal S1 output by the pickup 3
Is input to the demodulation circuit 6 of the decoding circuit system 5 controlled by the system controller 4 and demodulated. The data demodulated by the demodulation circuit 6 is input to an ECC (Error Correction Code) circuit 8 via a sector detection circuit 7,
Error detection and error correction are performed.

If the sector number which is the address assigned to the sector of the optical disk 2 is not normally detected in the sector detection circuit 7, a sector number abnormality signal is output to the track jump determination circuit 9. ECC
The circuit 8 outputs an error occurrence signal to the track jump determination circuit 9 when uncorrectable data is generated. The error-corrected data is sent from the ECC circuit 8 to the ring buffer memory 10 and recorded.

At this time, the ring buffer control circuit 11
The address of each sector is read from the output of the sector detection circuit 7, and the write address on the ring buffer memory 10 corresponding to the address (hereinafter, write pointer WP
Is specified). In addition, the ring buffer control circuit 11 controlled by the system controller 4 reads out the address of the data written in the ring buffer memory 10 (hereinafter, referred to as "the read buffer address") based on the code request signal R10 from the multiplexed data separation circuit 13 in the subsequent stage. A read pointer RP) is designated, data is read from the read pointer RP and supplied to the multiplexed data separation circuit 13.

The header separation circuit 14 of the multiplexed data separation circuit 13 separates the pack header and the packet header from the data supplied from the ring buffer memory 10 and supplies the separated data to the separation circuit control circuit 15. The separation circuit control circuit 15 sequentially switches and connects the input terminal G and the output terminals (switched terminals) H1 and H2 of the switching circuit 16 in accordance with the stream ID (Stream IDentifier) information of the packet header supplied from the header separation circuit 11. By doing so, the time-division multiplexed data is correctly separated and supplied to the corresponding code buffer.

Here, the video code buffer 17 is a multiplexed data demultiplexing circuit 1 depending on the remaining amount of the code buffer inside.
A code request R1 is generated for 3. Then, the received data is stored. Also, the video decoder 18
It receives the code request R1 from and outputs the internal data. The video decoder 18 reproduces a video signal from the supplied data and outputs it from the output terminal OUT1.

The audio code buffer 19 depends on the remaining amount of the code buffer inside the multiplexed data separation circuit 13.
A code request R2 is generated. Then, the received data is stored. Also, the audio decoder 2
The code request R2 from 0 is accepted, and the internal data is output. The audio decoder 20 reproduces an audio signal from the supplied data and outputs it from the output terminal OUT2.

As described above, the video decoder 18 requests data from the video code buffer 17, and the video code buffer 17 sends a request to the multiplexed data separation circuit 13,
The multiplexed data separation circuit 13 is a ring buffer control circuit 1.
Make a request to 1. At this time, data flows from the ring buffer memory 10 this time in the opposite direction to the request.

Data decoding in the demodulation circuit system 5 will now be described. First, the reproduction signal S1 read from the disk 2 is converted into a binary signal by RF processing in the demodulation circuit 6, and rough servo is applied based on the measurement result of the mark length of the signal S1. Here, when the sector detection circuit 7 detects a sync header with EFM + as an interface of the system controller 4, it detects a PLL (Phase Lock).
ed Loop) Servo is applied. After that, when the sync header is detected several times in succession, the EFM + demodulated data S2 is deinterleaved (hereinafter referred to as deinterleave).

As shown in FIG. 54, the EFM + demodulated data S2 sent to the ECC circuit 8 is first temporarily stored in the RAM 24 and then, in the ECC decoders 25, 27 and 29, the C1 / C2 convolution / Reed-Solomon code ( CIRC Pl
us) to decode ECC of 3 sequences C11 (first C1 sequence), C2 and C12 (second C1 sequence).

For ECC decoding in the ECC circuit 8, for example, as shown in FIG. 55, the data S2 after EFM + demodulation is written in the RAM 24 in the order of 00, 01, ..., A8, A9, and (EFM Write)
, When two frames of data after EFM + demodulation are stored in the RAM 24, 00 ', 02', ~ A8 'of frame 1
ECC of deinterleaved C1 sequence data by transferring data to the ECC decoder 25 in the order 01, 03, ... A9
Perform decryption. Here, in the error correction, the error position and the correction pattern are read from the ECC decoder 25, and the erroneous data is read from the RAM 24 (C
1 read), exclusive OR with the correction pattern,
As shown in FIG. 56, it is executed by writing back to the RAM 26 again (C1 Write). Here, the ECC decoder 25 executes the ECC decoding of the C1 sequence for the C2 code sequence length.

When the C1 sequence ECC decoding is executed for the C2 code sequence length, the C2 sequence ECC decoding can be executed. Next, the data on the RAM 26 is 00 ', 01', 02 ', 0
3 ', ~ A9' are read in this order (C2 read), ECC
The decoder 27 executes C2 sequence ECC decoding. Here, the erasure correction can be performed by transferring the uncorrectable flag for each frame to the ECC decoder in the subsequent stage in synchronization with the data. For erasure correction of the C2 series, the uncorrectable flag of C1 is used. The error correction operation is similar to that of C1. As shown in FIG. 57, when the C2 sequence ECC decoding result is written to the RAM 28 (C2 Write) and the C2 sequence ECC decoding is executed for the C1 code sequence length, the C12 sequence ECC decoding becomes feasible and the ECC decoder According to 29, 00 ', 01, 02, 03,
~ A9 read in order (C12 read) of C12 series
ECC decoding is performed.

Here, for erasure correction of the C12 series, the uncorrectable flag of C2 is used. And C1
When the error correction of No. 2 is completed, as shown in FIG.
ECC of C12 series in the order of 00, 01, 02, 03, to A9 in M30
The decryption result is written. In this way, the RAM 30 has EC
The decoded data of each sequence C11, C2, and C12 of C is stored and read out in the order of 00, 01, 02, 03, to A9 (O
UT read), descramble processing is performed, and the data is sent to the ring buffer memory 10, whereby necessary sector data is written.

The target sector to which the output data to be read belongs is detected by extracting the sector address from the reproduction data stored in a memory different from the memory used for ECC decoding. That is, a memory (RAM 24) for solving interleaving in the previous stage to detect a sector address, and a memory (RAM 26, for ECC decoding).
28 and 30) are assigned in sector address units so that the sector address comes first. In this way, the sector address is detected from the reproduction data read on the memory, and the optical disk 2 by the system controller 4 is detected.
It is used as location information when accessing.

In practice, the ECC decoded data S10 which has been ECC-decoded in the ECC circuit 8 compares the detected sector address with the target sector address set by the system controller 4 by the ring buffer control circuit 11 to determine the address. If they match, the ECC decoded data is written in the ring buffer memory 10.

In this ECC decoding method, the sector interleaved with respect to the target sector is detected by disk access, a sector several sectors before is detected, and then the EFM + demodulated reproduced data is placed at the beginning of the sector for ECC decoding memory. The corresponding start frame is written, ECC decoding is executed, and the decoded data is written in the ring buffer memory 10.

[0019]

When decoding the interleaved coded data, the sector address for the disk access by the system controller 4 is recognized, and the data of the sector is output after the ECC decoding. There is a gap between the and the time required for ECC decoding. Due to this shift, when the sector address is recognized during disk access, the ECC of the sector
Since the decoding has not been executed yet, the ECC decoded data S1
There is a problem that it is not possible to determine whether 0 is always written in the ring buffer memory 10.

When decoding coded data with interleaving, a memory for detecting a target sector and a storage medium such as a memory necessary for ECC decoding are separately required. There was a problem of getting bigger. In order to recognize the sector, the deinterleaved data is first written into the RAM 24 of the decoding memory in arbitrary sector units. At this time, the reproduction data read from the optical disk 2 is read from the beginning of the memory to the beginning of the sector. In order to store the data correspondingly, it is necessary to prepare the memory capacity for N times the sector.

Further, at the stage of writing to the ring buffer memory 10, since the head of the decoded data is not always the head of the sector, the ECC decoded data S10 stored in the memory for ECC decoding (RAM30) is read again from the target sector. Need to detect. Therefore, in addition to the circuit for recognizing the sector address at the time of disk access, another circuit for recognizing whether the data has the target sector address has to be provided, which causes a problem that the circuit configuration becomes complicated. It was The present invention has been made in view of the above points, and proposes a data decoding apparatus and method and a data reproducing apparatus that can quickly access a target sector while reducing the memory capacity for ECC decoding. To do.

[0022]

In order to solve such a problem, according to the present invention, in a data decoding device for decoding coded data recorded on a recording medium, the coded data and the decoding decoded from the coded data are performed. A decoding memory for storing data, a data information detection circuit for detecting data information of data to be read from decoded data generated during decoding of encoded data, and a data information storage means for storing the data information. And a data output control circuit that controls the output of the decoded data based on the data information.

Further, in the present invention, in the data decoding method for decoding the coded data recorded on the recording medium, the coded data read from the recording medium is stored in a decoding memory, and the coded data is stored. The data information of the data to be read is detected from the decoded data generated during the decoding of the data, the data information is stored, and the output of the decoded data is controlled based on the data information.

As a result, during the decoding of the encoded data recorded on the recording medium, the data information of the data to be read is detected and stored in the data information storage means, thereby decoding the encoded data. The output of the decoded data can be controlled independently of the above based on the data information.

Further, in the present invention, in a data reproducing apparatus for reading and reproducing an image signal and / or an audio signal composed of encoded data recorded on a recording medium, the encoded data and the decoded data decoded from the encoded data are used. And a data information detection circuit for detecting data information of the data to be read from the decoded data generated during the decoding of the encoded data,
A data decoding device having a data information storage means for storing data information and a data output control circuit for controlling the output of decoded data based on the data information is provided.

Thus, in the course of decoding the encoded data recorded on the recording medium, the data information of the data to be read is detected and stored in the data information storage means, thereby decoding the encoded data. Independently of this, the output of the decoded data can be controlled based on the data information, and the decoded data can be reproduced quickly.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment (1-1) Overall Structure of Data Reproducing Device 4 in FIG. 1 in which parts corresponding to those in FIG.
Reference numeral 0 indicates the overall structure of a data reproducing device using the data decoding device according to the present invention. The data reproducing device 40 irradiates the optical disk 2 with laser light of image data and audio data recorded at a variable rate on the optical disk 2, and reads the recorded data from the reflected light to reproduce the data. The reproduction signal S1 reproduced by the pickup 3 is sent to the demodulation circuit 6 of the demodulation / decoding circuit system 35 controlled by the system controller 4. The demodulation circuit 6 demodulates the reproduction signal S1 and outputs it to the sector detection circuit 7.

The sector detection circuit 7 detects the address recorded in each sector from the supplied data and outputs it to the ring buffer control circuit 11, and at the same time, the EC in the subsequent stage.
The data is output to the C circuit 50 in a state in which the sector is synchronized. The ring buffer control circuit 11 controlled by the system controller 4 controls writing and reading with respect to the ring buffer memory 10 and monitors a code request signal R10 requesting data output from the multiplexed data separation circuit 13. . Here, the sector detection circuit 7 cannot detect an address,
When the detected addresses are not continuous, the sector buffer abnormality signal is output to the track jump determination circuit 9 via the ring buffer control circuit 11.

The ECC circuit 50 detects an error in the data supplied from the sector detection circuit 7, executes error correction using the redundant bit added to the data, and outputs the FIFO (Fir
It is output to the ring buffer memory 10 for the track jump having the st in first out) function. The data in the ring buffer memory 10 is supplied to the multiplexed data separation circuit 13. At this time, the ECC circuit 50 detects the sector header data and sends it to the system controller 4 through the sector detection circuit 7. Here, if the ECC circuit 50 cannot correct the data error, it outputs an error occurrence signal to the system controller 4.

The track jump judgment circuit 9 monitors the output of the ring buffer control circuit 11, outputs a track jump signal JP1 to the tracking servo circuit 22 when a track jump is necessary, and determines the reproduction position of the pick up 3 with respect to the optical disk 2. It's designed to trigger truck jumps. Here, the system controller 4 sends the sector number abnormality signal from the sector detection circuit 7 or the ECC.
When the error occurrence signal from the circuit 50 is detected, the track jump determination circuit 9 outputs a track jump signal to the tracking servo circuit 22 to track the reproduction position of the pick-up 3.

The header separation circuit 14 to the multiplexed data separation circuit 13 separates the packet header and the packet header from the data supplied from the ring buffer memory 10 and supplies them to the separation circuit control circuit 15 and time-division multiplexed. Data is supplied to the input terminal G of the switching circuit 16. The output terminals (switched terminals) H1 and H2 of the switching circuit 16 are the video code buffer 17, respectively.
It is connected to the input terminal of the audio code buffer 19. Here, when the output terminal is switched to H1 by the switching circuit 16, the video code output is sent to the video decoder 18 through the video code buffer 17 and output from the output terminal OUT1. When the output terminal is switched to H2 by the switching circuit 16, the audio code output is sent to the audio decoder 20 through the audio code buffer 19 and output from the output terminal OUT2.

The code request signal R1 generated by the video decoder 18 is input to the video code buffer 17 and then to the multiplexed data separation circuit 13. Similarly, the code request signal R2 generated by the audio decoder 20 is input to the audio code buffer 19 and then to the multiplexed data separation circuit 13.

By the way, for example, when the data processing relating to a simple screen continues and the data consumption amount of the video decoder 18 per unit time decreases, the ring buffer memory 1
Reads from 0 are also reduced. In this case, the amount of data stored in the ring buffer memory 10 increases and there is a risk of overflow. Therefore, the track jump determination circuit 9 calculates the amount of data currently stored in the ring buffer memory 10 by the write pointer WP and the read pointer RP, and when the data exceeds a predetermined reference value set in advance. , Ring buffer memory 1
It judges that 0 may overflow, and outputs a track jump command to the tracking servo circuit 22.

Further, the track jump determination circuit 9 uses the sector number abnormal signal or ECC from the sector detection circuit 7.
When the error occurrence signal from the circuit 50 is detected, the amount of data remaining in the ring buffer memory 10 is obtained from the write pointer WP and the read pointer RP, and
Data required to guarantee the reading of the multiplexed data separation circuit 13 from the ring buffer memory 10 while the optical disk 2 makes one rotation (while waiting for one rotation of the optical disk 2) from the current track position. Find the amount. Here, when the amount of remaining data in the ring buffer memory 10 is large, underflow does not occur in the ring buffer memory 10 even if data is read from the ring buffer memory 10 at the highest transfer rate. Therefore, the track jump judgment circuit 9 judges that the error recovery is possible by reproducing the error occurrence position again by the pick-up 3, and outputs the track jump command to the tracking servo circuit 22.

(1-2) ECC Circuit and ECC Decoding The ECC circuit 50 shown in FIG. 2 decodes ECC by C1 / C2 convolutional / Reed Solomon code (CIRC Plus).
The ECC circuit 50 is a RAM composed of a ring buffer memory.
A (Random access Memory) 51, an ECC decoder 52 that performs error correction on the EFM + demodulated data and performs ECC decoding, and an error register 53 for storing an error correction impossible flag, an error correction pattern, and an error position. Is formed by.

ECC decoding, as shown in FIGS. 2 and 3,
The reproduction signal S1 read from the disk 2 is subjected to RF processing and binarization processing in the RF processing circuit 42, and then the demodulation circuit 4
4 detects the EFM + sync pattern. When the EFM + synchronization pattern is detected, the CLV control circuit 46 first applies rough servo. Then, the demodulation circuit 44 EF
When the M + sync pattern is detected, the PLL (Phase Locked
Loop) Servo is applied. After that, when the sync pattern is detected several times in succession, the data S2 after EFM + demodulation is written in the RAM 51 of the ECC circuit 50 in a frame unit through the RMIF (Random Access Memory InterFace) 48. Then, it is output to the ring buffer memory 10 through the OCTL (output control circuit) 56.

The ECC circuit 50 generates a write address to the RAM 51 through the RMIF 48. Here, the data read from the RAM 51 is transferred to the ECC controller 54 and the ECC decoder 55 through the RMIF 48. If an error is detected here and the error can be corrected, the error position and the error correction pattern are EC.
It is output from the C decoding unit 55 to the ECC control unit 54. In this case, the error position and the error correction pattern are stored in the RAM 5
1 is output for each frame and stored in the error register 53 (FIG. 2). For error correction, the error register 53
The error position and the correction pattern are read from the RAM 5
This is executed by reading the error data corresponding to the error position from 1 and taking the exclusive OR with the correction pattern and writing back to the RAM 51 again. When an uncorrectable error is detected, the uncorrectable flag of the frame is stored in the error register 53 for use in the ECC erasure correction in the subsequent stage.

As a result, the error register 53 stores the ECC for each ECC series C11, C2, and C12.
The error position and the correction pattern are accumulated as data necessary for solving If the error positions and correction patterns necessary and necessary to solve the ECC are aligned, E
The CC control unit 54 performs error correction with the data stored in the RAM 51.

Here, the data storage address RA is calculated from the data written in the RAM 51 as shown in FIG. 4 by using the data order Dn of the C1 series and the frame count Fn of the C1 code unit as follows.

[Equation 1]

[Equation 2]

(Equation 3)

(Equation 4) Required by.

Here, the RMIF 48 stores the results of the three ECC decoding sequences C11, C2 and C12 on the RAM 51 in the A of the frame including the head data of the sequence.
Write to any of A, AB, AC, AD, AE, and AFth addresses. Here, for example, the ECC result is AA, A
If writing to B and AC, three sequences C1 of ECC decoding are performed by frame count Fn and data order AA, AB, and AC.
The memory address of the RAM 51 for the results of 1, C2 and C12 can be easily generated.

In the disk reproducing apparatus 40, since it is necessary to secure a sufficient amount of data from the ring buffer memory 10 to guarantee the reading to the multiplexed data separation circuit 13, the RFCK records the disk (cutting). Set the channel bit rate during playback to a larger value than the reference channel bit rate at 26.6 (Mbit / s).

As shown in FIG. 5, for example, when EFM + writing (EFM + Wrire) is executed for the frame 182 of the RAM 51, at the same time, the C11 series data is transferred to the ECC decoder 52 in the order of 00, 02 to A9. (C11 read) Subsequently, the C2 series data is transferred (C2 read) to the ECC decoder 52, and then the C12 series data transfer (C12 read) is executed. And each series C
Frame 0 in which ECC of 11, C2, and C12 is executed is O
Data is transferred (OUT) to the CTL 56. Here, ECC data transfer of each series C11, C2, and C12 is executed at fixed intervals without interruption. So 1168 cycles of RF
ECC with a code length of 170 [byte] during one CK cycle
If C data is transferred, ECC must be performed 3 times within the cycle of RFCK.
Data is set to be transferred.

The EC stored in the RAM 51 in this way
Each data S2 of the three series C11, C2 and C12 of C is
Data is transferred to the ECC decoder 52 within one cycle of RFCK. At this time, the ECC data in the RAM 51 is left as it is. Here, when the ECC decoder 52 detects an ECC error and the ECC error can be corrected, the error position and the error correction pattern are sent to the error register 53 as the error result ER. The ECC circuit 50 takes the exclusive OR (EXOR) of the correction pattern read from the error register 53 and the erroneous data read from the RAM 51 based on the error position, and writes it back to the RAM 51 to correct the error. To execute. From the ECC circuit 50, the decoded data S1
0 and the sector header data SH are separated and sent to the ring buffer memory 10 and the sector detection circuit 7, respectively.

FIG. 6 shows the execution control timing of the actual data transfer, error result output and error correction of each series C11, C2 and C12 of the ECC data on the RAM 51. E
The CC control unit 54 first sends the ECC C1 to the ECC decoding unit 55.
C1 at the timing when the two-series data transfer is completed
Execute a series of error corrections (C11W). Next RA
At the timing after the C11 series data of the next frame is transferred from the M51 to the ECC decoder 52, the C of the current frame is transferred.
Two series of error correction (C2W) is executed. Further, the C12 series error correction (C12W) of the current frame is executed at the timing after the data transfer of the C2 series of the next frame.

In this way, the data of each of the three ECC series is RA
Continuous transfer from M51 to ECC decoder 55 (C11
R, C2R, and C12R), and then ECC error correction (C11W, C2W, and C12) of each 3-series data.
By executing W), the ECC data can be read and the error can be corrected within one cycle of RFCK. As a result, for each ECC series C11, C2, and C12,
RAM at fixed intervals with respect to RFCK and without interruption
Data can be output from 51.

When the ECC transfer code length NCYC is 170 cycles and the parity transfer code length PCYC is max 14 cycles, the timing at which the error result is output to the ECC register is

(Equation 5) This sets the timing of ECC operation clock (ECCK) 395 cycles. Here, the RMIF4 of the ECC circuit 50
From 8 on, ECCKs of the number of symbols for C1 and C2 sequences are counted, and C11R, C2R, and C within one RFCK cycle.
It is designed to always output three times in synchronization with the 12R data transfer. Therefore, the result of C11 is always output during the data transfer of C12. Also, the results of the C2 and C12 series can be output without fail during the data transfer of C11 and C2.

FIG. 7 shows the error output timing of the ECC circuit 50. Here, it is obtained by the equation (5).
(ECCK) When the OSTT signal, which is the output timing of the ECC result, is output after 395 cycles, OCORRECT = 1 after 3 clocks from the OSTT signal and the error pattern EDX appears in ODATA [7: 0] and OORIG [7: 0] , Error position EAX is output. In this example, the case where three errors ED0 to ED2 are output will be described. By the way, the ECC start pulse signal ESTT is
The ECC decoding unit 55 recognizes the beginning of the data of C1 and C2, the OCORRECT signal is the ECC result ODATA [7: 0],
This is a strobe signal for taking in OORIG [7: 0]. The error pattern EDX and the error position EAX are temporarily held in the error register 53, and the error correction is executed when the data transfer to the ECC decoder 52 at that time is completed.

Here, each EFM +, C11, C2, C1 is shown in FIG.
2, 1 frame (RFCK) cycle of OUT, that is, ECC operation clock required to access RAM51 during 1168 cycles
Indicates the number of clocks (ECCK). EFM + is 170 ± α for 1 cycle of writing sector sync pattern and EFM + demodulation output
It takes a cycle. The ECC C11 series requires 170 cycles for reading C11, 8 + 8 cycles for error correction for C11, and 1 cycle for writing C11, and 1 cycle for reading sector sync pattern, 20 cycles for reading header data and writing sector information in SUB. Requires 1+ (14) cycles.

Further, the ECC C2 series requires 170 cycles for reading C2, 14 + 14 cycles for correcting C2 errors, and one cycle for writing C2. Also ECC C
For 12 series, 170 cycles for reading C12, C12
It takes 8 + 8 cycles for error correction and 1 cycle for writing C12. OUT that indicates the end of ECC decoding
It takes 1 cycle to read the sector information, 1 cycle to read the correction result of C11, 1 cycle to read the error correction result of C2, 1 cycle to read the correction result of C12, and 170 cycles to OUT. This gives C1
Accessing RAM 51 of 1, C2, C12, and OUT is 948 cycles in total.

SUB for executing reading of header data
Is the sync code (4 bytes) to the sector detection circuit 7 +
The sector detection circuit 7 for detecting a sector by transferring the header data (16 bytes) extracts the sector address from the header data, and after CRC check, applies a flywheel (FW) and transfers to the system controller.
The sector header data SH is extracted from the ECC-decoded data of only the C11 series at the timing (SUB) after C11W shown in FIG.
The system controller 4 extracts the sector address through the disk position information of the C2 and C12 series.
It takes out as early as the time required for ECC decoding. The flywheel is a protection and interpolation operation that keeps the lock state even if the sink is not detected several times. The system controller 4 compares and determines whether or not it is the target sector. The flywheel detects the sync pattern of the binarized signal extracted from the RF signal several times in succession, and if it detects the main sync pattern and the sub sync pattern several times in succession, it locks the FW.

In addition, a frame unit operation (JOB
) Execution condition

(Equation 6)

(Equation 7)

(Equation 8)

[Equation 9] Set as follows. When the frame count for JOBXXX is Fn (XXX), the count is incremented by +1 when all JOBs for XXX in frame units are completed. SUB is included in C11.

In EFM +, when a sync is detected several times in succession, a sync pattern FW lock is obtained. At this time, the memory write enable signal MWENS becomes MWENS = 1 and EF
Writing of M + demodulation data starts. When the sync cannot be detected several times in succession, the sync pattern FW is unlocked and the memory write enable signal is MWENS = 0.
Therefore, writing of EFM + is prohibited and each frame counter is reset to 0. Here, MWENS is a signal that becomes 1 when the sync pattern FW is locked, and MWENS =
When it is 1, it is a memory write enable signal for writing to the memory.

Here, in FIG. 9, for example, output of decoded data
OUT issues a request OUTREQ once every four cycles of C11M, and OUTREQ,
The access acquisition timing for the RAM 51 when the access acquisition is prioritized is shown in the order of EFMREQ and ECCREQ.
Here, a predetermined job is executed with XXX ACK (ACKnowledge) = 1. ECC data output is started at the rising edge of RFCK and is executed based on the JOB execution conditions. Each ECC sequence C11, C2 and C12 includes C11R-C including SUB.
2W-C2R-C12W-C12R-C11W-SUB are executed in this order.

Therefore, each ECC sequence C11, C2 and C
For 12 and OUT, the sync FW once locks and MWENS =
If the condition of 1 continues and the execution condition of each JOB continues to be satisfied, Fn
The difference value between the count values of (C11) to Fn (OUT) is a fixed value in the RFCK cycle. By the way, in the data decoding device 40 to which the present invention is applied, from the ring buffer memory 10,
It is necessary to secure a data amount enough to guarantee the reading to the multiplexed data separation circuit 13. Therefore, RFCK is set so that the channel bit rate during playback is larger than the reference channel bit rate of 26.6 (Mbit / s) during disk recording (cutting).

(1-3) Sector Detection Detection of the target sector of the optical disk 2 and generation of sector information will be described with reference to FIGS. First, FIG.
(A) and (B) show the frame structure of the reproduction data read from the optical disk 2 and the specific contents of the sync word. As shown in FIG. 10B, the sync word is
Additional Sync (Additional Sync) S1, C1 Sync (C1 Sync) S2, and Sector Sync (Sector Sync) S
It starts from 3. FIG. 11 shows the sector format after deinterleaving. When the sync pattern (S1 to S3) is detected by the sector detection circuit 7, the sync pattern FW is locked, then the sector FW is performed in the sector header SH (HEADER), and then the sector address SA
(ADRESS) is detected and the sector address FW is locked.

Next, each bit B of the sector information shown in FIG.
IT data will be described. First, bit 7 shows the detection result of the presence or absence of the sector sync pattern S3, and 1 is set in the frame in which the sector sync pattern S3 is detected. Bit 6 indicates the result of detection of the presence or absence of the sync code, and the sector detection circuit 7 sets "1" in the frame in which the specific code "HDCD" was detected at the sync code position at the head of the sector. Bit 5 indicates the recognition of the sector sync, and by using the information of the sector sync pattern S3 and the sector sync code SC, the frame finally regarded as the sector sync by the sector detection circuit 7 is set to 1 and is interpolated. Will be the sector sync.

Next, bit 4 shows the result of CRC check. If no error is detected as a result of executing the CRC calculation for each sector, "0" is written. Bit 3 is C1
Indicates the ECC decoding result of the sequence, and is set to "0" if no error is detected. This is a C from RMIF48
As a result of the ECC decoding of the 11 series, a flag indicating whether or not the data cannot be corrected is fetched by the sector detection circuit 7 and written in this bit.

Bit 2 indicates the continuity of the sector address SA, and the sector address (R
aw Sector Adrress, RSA) is equal to the sector address (Current Sector Adrress, CSA) stored in the sector detection circuit 7 (actually RSA and CSA of the previous sector).
Comparing with +1. ), It is determined that the sectors have continuity, and BIT2 = 1. Bit 1 shows the detection result of the starting sector address BSA, and is set to "1" when the address BSA is detected. Bit 0 indicates the detection result of the end sector address ESA, which is set to "1" when the address ESA is detected.

As shown in FIG. 13A, the actual sector detection is performed by the system controller 4 to the register (not shown) in the sector detection circuit 7 in the BSA setting mode SACT =
1 (shown in FIG. 19 which will be described later) is set, a target sector start address BSA and a sector end address ESA are set, and reproduction is performed in a register (not shown) in the sector detection circuit 7. Extracted from the data,
The sector address FW is compared with the locked sector address. When it is confirmed from the comparison result that the detected sector address belongs to the target sector, this comparison result is stored in the RAM 51 as sector information (bits 0, 1).
Is written back to

Here, when SACT = 1, output is possible from frame M (FIG. 18). However, when the descramble is initialized by the sector address, the condition is that the sector address of the output for the descramble can be extracted before that. The output sector address is
The output sector address protected by the address continuity of the sector information is used.

Further, this sector information is stored in the ECC circuit 50.
It is sent to the OCTL 56 together with the ECC decoded data S10 for which the ECC decoding by is completed and is used for controlling the data output OUT of the ECC decoded data. At this time, the system controller 4 anticipates ECC interleaving, and causes the disk access position to track jump to a position in front of the intended sector on the optical disk 2. Further, at this time, if the target sector is not specified by the system controller 4, by setting SACT = 0 in advance,
Data can be output from the time when ECC decoded data can be read.

The detection result of the presence or absence of the sector sync pattern S3 of the bit 7 of the sector information is written in the RAM 51 for each frame together with the EFM + demodulated data detected from the reproduced data at the time of EFM + demodulation in the EFM + demodulation circuit 44, and the header data SH. At the same time, it is transferred to the sector detection circuit 7. The sector detection circuit 7 detects the presence / absence of the sector sync pattern S3 in each frame based on the detection result.
Recognize more sectors. When the sector of the optical disc 2 is recognized by the sector detection circuit 7, the sector address SA is extracted from the header data SH of the sector.

In the sector detection circuit 7, the header data SH
The flywheel FW is applied to the sector address SA by adaptively using the result of the CRC check, the continuity of the address, the ECC decoding result of the C1 sequence of the sector frame, and the like. In the system controller 4, the flywheel F
The sector address SA in which the sector address FW is protected by W is taken out and used as the position information ADD of the optical disk 2.

Of the sector information, bits 0 and 1 are OCT
When the bit 1 of the sector information is "1" and the bit 0 of the sector information is "0", which is referred to by L56, that is, when the sector from the sector address BSA to the ESA is detected, the data of the target sector of the system controller 4 is detected. Is set to output. Here, when the sector address ESA is not designated, the bit 0 holds "0". During this period, the ECC decoded data will continue to be output to the ring buffer memory 10. Here, for example, the data output control register (not shown) provided in the OCTL 56 may be used to control the data output regardless of the states of the bits 0 and 1.

Here, as shown in FIG. 13B, the starting sector address BSA and the ending sector address ES
The setting of A can be performed by the system controller 4 after the track jump, other than when the track jump is performed. For example, when the access positions on the disk are close to each other, such as when skipping unnecessary data during the fast-forward operation, the current sector address SA is recognized and then the sector addresses BSA and / or ESA are reset. As a result, data can be output from the sector address BSA without performing a track jump.

FIG. 14 shows sync patterns (S1 to S
3) shows the time relationship from when the sector address SA becomes readable to when data is output after the block 3). When the sync pattern (S1 to S3) is locked after the EFM + demodulation is started after the disk access position is track-jumped by the system controller 4, the sync pattern lock SYLK becomes SYLK = 1. Then, the sector address SA of the target sector is locked by the flywheel FW (at SALK = 1). Then, when the C11 execution frame of ECC decoding becomes 170 or more, STOK = 1, and the data after that becomes output OUT of data after ECC decoding. Actually, after executing about 173 frames of C2 sequence ECC decoding including jitter for STOK = 1 timing, the effective data of the ECC decoded data at the next stage is detected at the timing when the start sector address BSA is detected. The data strobe signal DSTB output to the ring buffer memory 10 is
DSTB = 1 and output of valid data of the ECC decoded data S10 is started.

In the above configuration, the actual sector detection and data output are the timings after the execution of C11 shown by the arrow in FIG. 15 with the enable signal + LATCHED MWEN for enabling the writing of EFM + decoded data being "1". Then, the presence or absence of the sector sync pattern of bit 7 of the sector information of the frame, the data of the sync code SC and the header data SH are analyzed by the sector detection circuit 7, and the reading operation of the sector address SA is started. Leadframe Clock RF here
The CK cycle is

(Equation 10) Required by

Then, as shown in FIG. 16, when the frame at the head of the sector is detected (3 frames) and the sector confirmation condition that bits 6 and 7 of the sector information are "1" is satisfied, the sector FW is determined. Lock. Further, when it is determined that the continuity of the sector addresses is correct, the sector address SA confirmation condition is satisfied and the sector address FW is locked (3 frames). As a result, SALK = 1 at the timing shown by the arrow in the figure (considering a margin of one frame such as jitter). System controller 4
Then, if SALK = 1, the sector address SA locked by the FW can be read. Frame count Fn (C11) of C11 sequence of ECC decoding at this time, N is the following equation,

[Equation 11] Is represented by

Then, as shown in FIG. 17, the C11 series
After 170 frames of ECC decoding, each C11 of ECC decoding,
If the RMIF 48 determines that the C2 and C12 sequences are all executed and output frames, STOK = 1
Then, the sector detection circuit 7 is notified at the timing of SUB that output is possible.

Subsequently, as shown in FIG. 18, when STOK = 1 when the start sector address BSA is detected in the frame M at the head of the sector, the frame M is subjected to ECC decoding in the future and can be output. The information bit 1 is "1", that is, the sector address BS which is the start address of the sector.
When A is detected, the signal ISTT which becomes "1" is set to ITT = 1, and the bit 7 to 0 of the sector information is written back to the RAM 51 from the RMIF 48 at the timing of the end of SUB. At this time, if STOK = 0 when the start sector address BSA is detected, it is judged as an error that the system controller 4 re-accesses the optical disk 2 from a position ahead of the previous time, for example.

Here, as shown in FIG. 19, when the sector address BSA is set and SACT = 1, the data strobe signal DSTB = 1 and the ECC is sequentially started from the frame M.
The decoded data Fn (OUT) can be output (indicated by an arrow in the figure). However, when the descrambling initialization is executed by the sector address SA, it is a condition that the output sector address SA for descrambling can be extracted before that. As the output sector address SA, the output sector address SA protected by the address continuity of the sector information is used.

As shown in FIG. 20, when SACT = 0 in which the sector addresses BSA and ESA are not set, output is possible from the head of the sector after the 170th frame (indicated by an arrow in the figure). However, the output from the 170th frame is impossible here because the output sector address SA for descrambling is required. Therefore, a maximum of one sector is waited for the output sector address SA to be read. When the descrambling is initialized by the output sector address SA, DSTB = 1 and output to the ring buffer memory 10 is started. In this way, it is possible to detect the sector based on the sector information and control the output of the data of the target sector. Thus RAM5
By setting a small memory area for sector information in 1 without increasing the memory required for ECC decoding, the sector information can be used to reliably access the target sector data and control the data output. it can.

According to the above configuration, a small area for storing sector information used for sector detection is provided in the decoding RAM 51 in the ECC circuit 50, so that the encoded data decoded in the ECC circuit 50 can be interleaved. Even if there is a problem, without providing a separate memory for sector detection, EC with almost the memory capacity used for ECC decoding
C decryption can be performed.

Further, according to the above-described embodiment, the sector buffer generated by the sector detection circuit 7 and the STOK signal generated by the RMIF 48 cause the ring buffer memory 10 of the next stage at the timing when the C11 sequence of ECC decoding is completed.
It is possible to determine whether or not to output to. As a result, it is possible to immediately judge whether or not the sector data can be written to the ring buffer memory 10 in the next stage at the timing of recognizing the sector address SA for the disk access by the system controller 4, and the access to the sector data can be performed. Can be done fast and reliably.

Further, according to the above-described embodiment, data is output to the ring buffer memory 10 at the next stage at the timing OCCRRECT = 1 (FIG. 7) at which the system controller 4 recognizes the sector address SA for disk access. Since it is possible to determine whether or not
It is not necessary to additionally provide a circuit for detecting the sector address SA from the ECC-decoded data stored in M51, and the entire circuit configuration can be simplified.

(2) Second Embodiment (2-1) Recording Data Format FIGS. 21 to 24 show recording data formats in the second embodiment. In this embodiment, one cluster (3
Data is recorded in units of 2 kbytes. The configuration of this cluster will be described in detail below.

That is, 2 kbytes (2060 bytes)
Data is extracted as data for one sector, and a 4-byte overhead is added to this data as shown in FIG. The overhead includes an error detection code (EDC) for error detection.

Data of one sector of 2064 (= 2060 + 4) bytes in total is 12 as shown in FIG.
The data is x172 (= 2064) bytes. Then, 16 pieces of data for one sector are collected, and 192
(= 12 × 16) × 172 bytes of data. A 16-byte outer code (PO) is added to this 192 × 172-byte data as a parity for each byte in the vertical (column) direction. Also, 208 (= 192 + 1)
6) For x172 bytes of data and PO parity,
An inner code (PI) of 10 bytes is added as a parity for each byte in the horizontal (row) direction.

Further, in this way, 208 (= 192
Of the data that has been blocked into +16) × 182 (= 172 + 10) bytes, the 16 × 182-byte row of the outer code (PO) is divided into 16 1 × 182-byte rows, as shown in FIG. , 16 rows of 12 × 182 bytes of sector data of numbers 0 to 15 are inserted line by line and interleaved. And 13 (= 1
Data of (2 + 1) × 182 bytes is data of one sector.

Further, the 208 × 182-byte data shown in FIG. 23 is vertically divided into two, as shown in FIG. 24, and one frame is composed of 91-byte data.
The data is 8 × 2 frames of data. At the beginning of the 91-byte frame data, a 2-byte frame synchronization signal (FS) is further added. As a result, as shown in FIG. 24, one frame of data becomes a total of 93 bytes of data, and a total of 208 × (93 × 2) bytes of block data. This becomes data for one cluster (1ECC block). The size of the actual data part excluding the overhead part is 2 kbytes (= 2048 × 16/102
4 kbytes).

That is, in this example, one cluster (1
The ECC block) is composed of 16 sectors, and one sector is composed of 24 frames. Such data is recorded on the optical disk 2 in cluster units.

(2-2) Data Reproducing Device and ECC Decoding Here, FIG. 25 shows a demodulation circuit system in the case of applying the recording data format of the second embodiment to the data reproducing device 40 described in the first embodiment. 35, the demodulation circuit 6 (R
F processing circuit 130, EFM + demodulation circuit 131, sector detection circuit 7 (SBCD circuit 134, RAM controller 135, RAM 137), and ECC circuit 50 (RA
M controller 135, ECC control circuit 136, RAM
137, ECC core circuit 138, OCTL circuit 13
9) and a detailed configuration of circuits around it.

In this figure, the RF processing circuit 130 is
The RF signal input from the pickup 3 shown in FIG. 1 is received, the signal is binarized, and then the EFM + demodulation circuit 131
Output to The EFM + demodulation circuit 131 performs EFM + demodulation on the input signal and detects a synchronization pattern. The CLV control circuit 132, based on the synchronization pattern output from the EFM + demodulation circuit 131, drives interface (hereinafter abbreviated as drive IF) 133.
Control. The SBCD (subcode) circuit 134 is an EF
The sector is detected from the output of the M + demodulation circuit 131. R
The AM controller 135 corresponds to the RMIF 48 of FIG. 3 and controls the reading and writing of the RAM 137.

The RAM 137 is adapted to temporarily store data and the like when the ECC control circuit 136 executes error correction processing and the like. ECC core circuit 138
Corresponds to the ECC decoding unit 55 in FIG. 3, and uses Reed-Solomon codes (PI and PO) to perform ECA, ECD,
The SGLG or the like is generated and output to the ECC control circuit 136. The ECC control circuit 136 uses ECA, ECD, SFLG, etc. supplied from the ECC core circuit 138,
Actually correct the error. The OCTL circuit 139 performs descramble processing, EDC check, control of output data, and the like. The host CPU 140 corresponds to the system controller 4 of FIG. 1 and is adapted to control each part of the apparatus.

The reproduced signal from the optical disk 2 (FIG. 1) is
It is converted into a binarized signal in the RF processing circuit 130.
Then, from the binarized signal, the EFM + demodulation circuit 13
1, the sync pattern is detected. Then, in the CLV control circuit 132, rough servo is applied based on this synchronization pattern, and as a result, a sync code (Sync Code) (SY0 to SY7 in FIG. 26) in the data is further detected, and the result is passed through the drive interface 133. The PLL (Phase Locked
Loop) phase servo is applied.

FIG. 26 shows a configuration example of the physical sector of the optical disk 2. As shown in this figure, the physical sector consists of two Sync frames in the horizontal direction and one in the vertical direction.
It is composed of three sync frames, which is a total of 26 sync frames. Each sync frame has a sync code (SY0 to SY0) of 32 channels (16 bits (= 2 bytes when expressed in data bits before modulation)).
SY7) and a 1456 channel bit (expressed as a data bit before modulation, 728 bits (= 91 bytes)). In the data portion of the first sync frame, ID information (sector number) and IED
In addition to the (error detection code for ID) information, main data is stored.

The 32-channel bit sync pattern is a unique pattern that does not appear in the data.
The lower 22 bits are "000000000000"
It is set as "000010001".

Main data is recorded in the data portion of each sync frame on the left side of FIG. 26, and PO information (parity) is recorded in the data portion of the last sync frame on the left side. Main data and PI information are recorded in the right sync frame of FIG. 26, EDC information and PI information (parity) are recorded in the second to last sync frame of the right sync frame, and the last sync frame is recorded. In this area, PO information and PI information are recorded.

FIG. 27 shows details of data excluding PI information and PO information of each sector. ID (sector number) (4 bytes), IED (error detection code for ID (2 bytes)), RSV (reserved area) (6 bytes), main data, and EDC (4 bytes) make up one sector of data. The main data has been subjected to scramble processing.

Then, 16 such data sectors are collected, and as shown in FIG.
An O code and a 10-byte PI code are added. Further, interleaving is performed so that 16 rows including the PO code are arranged for each data sector. Then, the obtained data is, as shown in FIG. 24, the sync code SYx (x
= 0 (0, 1, 2, ..., 7), an FS (frame synchronization) code is added and EFM + modulated.
As a result, the physical sector in the ECC block is composed of 13 × 2 sync frames as shown in FIG. Since one ECC block consists of 16 sectors, the lower 4 bits of the physical sector address are 0000 to 1
It will be one of 111. As a result, the physical address of the first sector of the ECC block is 0000 in the lower 4 bits.
Becomes

In the scramble process for the main data, the exclusive OR is calculated between the scramble data generated with the value specified by the lower 4 bits to 7 bits of the physical sector address as the initial value and the main data. It is executed by

Since various symbols are used for various signals in this specification, they will be collectively described here.

Block-top (Block Top) A signal which becomes H from the head of the sector when the SYLK signal is H. C11M (Clock 11.2896 MHz) This is the operating clock of the system, and its frequency is 11.2.
896 [MHz]. DSTB (Data strobe) This is a data strobe signal which becomes H when main data is output as the stream data SD. ECA (ERR Correction Address) An error correction address signal indicating a position (address) having an error. ECCK (ECC Clock) This is an operation clock of the ECC core circuit 138. ECD (Error Correction Data) ECD (Error Correction Data) is error correction data that becomes correct data when an exclusive OR is calculated with erroneous data. ECCE (ECC Code Data End) This is a controller signal indicating the end of input data. ECOD (ECC Code ERR) This signal is H when an error cannot be corrected. ECOR (ECC Correction) This is a strobe signal indicating the output of error-correctable data (ECA, ECD). ECYE (ECC Cycle End) This is a controller signal indicating the end of the cycle of input code data. EDT (ECC Data) Read from the RAM 137 for error correction, ECC
This is the data transferred to the control circuit 36. ESTB (Error Strobe) This is an error correction result strobe signal which becomes H when the error correction result ER is transferred. ESTT (ECC Start) This is a controller signal indicating the beginning of input data. EFM + W Frame (EFM + Write Frame Counte
r) A signal representing the main frame to be written in the RAM 137. HDEN (Header Data Enable) This is a strobe signal for sector header data. main-FMSY (main Frame Sync) This signal is H at the main sync (head sync) of each PI row. MWEN (Memory Write Enable) EFM + is a write enable signal to the RAM 137 for demodulated data. MWRQ (EFM Write Request) This is a write request signal of the EFM + demodulated data to the RAM 137. OUTE (Output Flag) This is an interpolation flag (output flag). OSTT (ECC Output Start) From ESTT in a predetermined code sequence to 477 (ECC
K) is a signal output after being delayed. RDT (Read Data) Data on the read data bus of the RAM 137. SALK (Sector Address Lock) This signal indicates that the sector address (ID) is normally detected. SAUL (Sector Address Unlock) This signal has the opposite polarity of the SALK signal. SCSY (Sector Sync) This signal is H for Frame of SY0 and is for determining the beginning of a sector. SD (Stream Data) This is stream data (decoded output data). SDCK (Stream Data Clock) This is a clock of stream data. SFLG (Sector Flag) This is an ECC uncorrectable flag for PI1 correction. SINF (Sector Information) This is a sector information strobe signal which becomes H at the head of a sector. SUB (SUB Data) is data including an ID and an IED transferred to the SBCD circuit 134. SYLK (Sync Lock) This signal becomes H when the sync code is detected three times in succession. SYUL (Sync Unlock) This signal has the opposite polarity of the SYLK signal. WDT (Write Data) Data on the write data bus of the RAM 137. XHWE (Sector Header Write Enable) This is an output enable signal of sector information written from the SBCD circuit 134 to the RAM 137.

The data demodulated by the EFM + demodulation circuit 131 (FIG. 25) is the RAM controller 13 data.
Under the control of No. 5, it is stored in the RAM 137 as shown in FIG. This FIG. 28 shows about one ECC block. When reading the data stored in the RAM 137, the RAM controller 35 can obtain desired data by designating the values of the rows and columns shown in FIG. That is, in FIG. 28, the M-th
The data x in the Nth byte of the row is binary (M, N)
Can be read from the RAM 137.

When the head of the data sector recorded on the optical disk 2 is recognized by the SBCD circuit 134 based on the type and continuity of the sync code, the EFM is performed.
The data demodulated by the + demodulation circuit 131 is stored in the RAM 137 in order from the top data. FIG. 29 shows the signal timing of the main part of the circuit concerned at this time.

That is, the EFM + demodulation circuit 131 detects the lock state of the sync, as shown in FIG. First, in step SP1, it is determined whether or not the sync code (SY0 to SY7) shown in FIG. 26 can be detected in each sync frame. If the sync code can be detected, step S
In step P2, the variable SClock is incremented by 1, and the variable SC _{unlock is set} to 0. The variable SClock represents the number of times when the sync code is continuously detected, and the variable SC _unlock represents the number of times when the sync is not continuously detected.

Next, at step SP3, the variable SC
Determine if lock equals 3. That is, it is determined whether the sync has been detected three times in succession. If the variable SLock is smaller than 3, the process returns to step SP1 to repeat the subsequent processing. If it is determined in step SP3 that the variable SLock is equal to 3, it is determined that the lock state has been reached, and the SYLK signal is set to H in step SP4.
Then, in step SP5, in order to determine whether or not the sync is detected three times in succession, the variable SC
The lock is set to 2, the process returns to step SP1, and the subsequent processes are repeatedly executed.

On the other hand, in step SP1,
If it is determined that the sync code has not been detected, the process proceeds to step SP6, where the variable SC _unlock is incremented by 1 and the variable SC _lock is set to 0. In step SP7, it is determined whether the variable SC _unlock is equal to 3. That is, it is determined whether or not the sync code has not been detected three times in a row. If the number of consecutive failures is 2 or less, step S
The process returns to P1 and the subsequent processes are repeatedly executed. If the sync is not detected three times in succession, the process proceeds to step SP8 and the SYLK signal is set to L. Then, in step SP9, the variable SC _unlock is set to 2 so that the SYLK signal can be kept set to L when the sync code is not detected even at the next sync code generation timing. Then, the variable SC _unlock is set to 2, and the process returns to step SP1.

As described above, the EFM + demodulation circuit 13
1 detects the sync code and constantly monitors whether it is in the locked state.

In the above embodiment, the number of times of detection is three, but the number of times of continuous detection N, which is a reference, is set.
_LOCK and the discontinuity detection count N _UNLOCK can be set to arbitrary values.

As described above, the EFM + demodulation circuit 131 is
When the YLK signal becomes H, that is, when it becomes the lock state, the processing shown in the flow chart of FIG. 31 is executed. That is, in step SP21, it is determined whether or not the sync code SY0 arranged at the head of each sector is detected. When the sync code SY0 is detected, the process proceeds to step SP22, and the SCSY signal indicating the beginning of the sector is set to H for a predetermined time. Next, in step SP23, it is determined whether or not the SYLK signal has changed to L. If it is not L (if it is still H), the process returns to step SP21 to repeat the same processing. In step SP21, the sync code S
When it is determined that Y0 is not detected,
The processing of step SP22 is skipped.

As described above, the EFM + demodulation circuit 13
No. 1 is S shown in FIG. 29A at the head of each sector.
Generate the CSY signal.

Further, the EFM + demodulation circuit 131 is
When the LK signal becomes H, the processing shown in the flow chart of FIG. 32 is executed. First, in step SP31, the sync code of the main frame (hereinafter, the two horizontal sync frames of FIG. 26 are collectively referred to as one main frame) (hereinafter, the left side of the sync codes of FIG. 26). It is determined whether or not the sync code shown in (1) is detected as a main frame sync. When the main frame sync is detected, the process proceeds to step SP32, where the EFM + demodulation circuit 131 has m shown in FIG.
Generate the ain-FMSY signal. If it is determined in step SP31 that the main frame sync has not been detected, the processing in step SP32 is skipped.

Next, in step SP33, it is determined whether or not the SYLK signal has changed to L. If it has not changed (if it remains H), the process returns to step SP31.
The subsequent processing is repeatedly executed. SYLK signal is L
When it changes to, the generation process of the main-FMSY signal is stopped.

In this way, the EFM + demodulation circuit 131
Is the main-sync for each cycle of the main frame sync (cycle of two sync frames in the horizontal direction in FIG. 26).
Generate the FMSY signal.

The RAM controller 135 receives the SCSY signal from the EFM + demodulation circuit 131, as shown in FIG.
9 (D), set the MWEN signal to H and R
The process of writing the data of the currently detected sector to the AM 137 is started. That is, at this time R
As shown in FIG. 29E, the AM controller 135 counts the mainframe shown in FIG. 26 with a built-in EFM + W Frame counter (not shown). This count value represents the numbers in order from the top of the main frame shown in FIG.

Further, the RAM controller 135 is shown in FIG.
As shown in FIG. 9 (F), the built-in PI1 Frame counter (not shown) manages the number of the mainframe transmitted to the RAM 137.

That is, when the data of the first main frame shown in FIG. 26 (main frame of number 0 (main frame of the uppermost row in FIG. 26)) is written in the RAM 137, the ECC control circuit 136 causes the RAM controller 135 to operate. Under control, it is supplied with data for its mainframe. Then, this data is transferred to the ECC core circuit 138 and an error correction process is executed. That is, a PI1 process is executed. The data after PI1 correction is written back to the RAM 137 again.

The RAM controller 135 uses this PI1
After the correction (first PI correction) is executed, the ID and the IED data (SUB) are read out from the data of the mainframe with the number 0 stored in the RAM 137, and FIG.
At the timing of the SUB signal indicated by the number 0 in (C), the ID and IED data of the main frame of the number 0 are transferred to the SBCD circuit 134 via the data bus. As shown in FIG. 26, since the ID and IED data are arranged only at the head of each sector, this transfer process is executed only in the mainframe with the number 0.
In this way, the SBCD circuit 134 detects the address (ID) of the physical sector.

The leading sector of the ECC block is detected by the lower 4 bits of the detected physical sector address.

FIG. 33 shows bl following the transfer of the above ID.
FIG. 34 shows a timing chart in the case of detecting the ock-top, and FIG. 34 shows the processing after the detection of the block-top, and the operation of these figures will be described later.

FIG. 35 is a timing chart showing more detailed timing of the above-mentioned ID transfer. FIG. 35 (A)
As shown in FIG.
The HDEN signal indicating the timing of reading the ID and IED data from the RAM 137 is output to the circuit 134. At this time, the SBCD circuit 1 is read from the RAM 137.
For 34, total of 7th bit to 0th bit is 8
As the bit read data RDT (FIG. 35 (C)),
ID data (4 bytes) and IED data (2 bytes)
However, a clock C11 with a frequency of 11.2896 [MHz]
It is transferred in synchronization with M (FIG. 35 (F)). It is supplied from the ECC core circuit 138 to the ECC control circuit 136 that the ID data and the IED data are not in the uncorrectable state (in this case, the SFLG signal becomes H) as a result of PI1 correction. It is represented by the SFLG signal (= 1). When the SBCD circuit 134 is supplied with the ID (sequential address), the SBCD circuit 134 sends the sector information SI corresponding to the ID (sector) to the command from the host CPU 140 (command such as interpolation flag generation mode, start sector, end sector, etc.). ). For example, in the sector of the ID whose output is specified by the host CPU 140,
The bit 5 of the sector information is set to 1, and the bit 4 is set to 0.

FIG. 36 shows the structure of sector information (SI). As shown in the figure, each bit of the sector information has the following information.

Bit 7: Setting of interpolation flag (OUTF) generation mode (1: Interpolation flag generation mode) Bit 6: First sector of ECC block (set to 1 when lower 4 bits of physical sector address is 0)
(1: Start sector) Bit 5: Start sector (1 if the physical sector address matches the start sector address specified by the host CPU 140) (1: Start sector) Bit 4: End sector (physical sector address) Is set to 1 when the end sector address specified by the host CPU 140 matches) (1: end sector) Bit 3: Descrambling initialization address Bit 3
(Seventh bit of physical sector address) Bit 2: Descramble initialization address bit 2
(Sixth bit of physical sector address) Bit 1: Descramble initialization address bit 1
(Fifth bit of physical sector address) Bit 0: Bit 0 of descrambling initialization address
(4th bit of physical sector address)

After the check processing is performed by using the 4-byte ID and 2-byte IED as described later with reference to FIGS. 38 to 40, the XHWE signal shown in FIG. It is set to L by the control circuit 136. At this time,
The sector information SI is transferred from the SBCD circuit 134 to the RAM 137 as 8-bit write data WDT and written. The sector information for 16 sectors is stored so as to correspond to the upper 16 PI rows, as shown in FIG. Therefore, by designating the number of predetermined PI rows, the corresponding sector information can be obtained.

As shown in FIG. 37A, the actual sector detection is performed by the host CPU 140 by the SBCD circuit 134.
A BSA setting mode is set to a register (not shown) in the inside, and the start address BSA of the target sector and the end address ESA of the sector are set to SBCD.
A register (not shown) in the circuit 134 extracts the reproduced data and compares it with the sector address FW locked sector address. When it is confirmed from the comparison result that the detected sector address is of the target sector, the comparison result is written back to the RAM 137 as sector information (bits 4 and 5).

Further, this sector information is stored in the ECC circuit 50.
It is sent to the OCTL 139 together with the ECC decoded data whose ECC decoding has been completed by and is used for the control when outputting the ECC decoded data. At this time, the host CPU 140
In anticipation of ECC interleaving, the disk access position is track jumped to a position in front of the intended sector on the optical disk 2. At this time, the host C
If the target sector is not specified by the PU 140, by canceling the BSA setting mode in advance, the EC
Data can be output from the point when C-decoded data can be read.

Of the sector information, bits 4 and 5 are OCT
When the bit 5 of the sector information is "1" and the bit 4 is "0", which is referred to by L139, that is, when the sector from the sector address BSA to the ESA is detected, the host C
The PU 140 is set to output the data of the target sector. Here, when the sector address ESA is not designated, the bit 0 holds "0". During this time,
The ECC decoded data will continue to be output to the ring buffer memory 10. Here, for example, a data output control register (not shown) provided in the OCTL 139 may be used to control the data output regardless of the states of the bits 0 and 1.

Here, as shown in FIG. 37B, the start sector address BSA and the end sector address ES
The setting of A can be reset from the host CPU 140 after the track jump, other than when the track jump is performed. For example, when the access positions on the disk are close to each other, such as when skipping unnecessary data during the fast-forward operation, the current sector address SA is recognized and then the sector addresses BSA and / or ESA are reset. As a result, data can be output from the sector address BSA without performing a track jump.

The ID and IED check processing in the SBCD circuit 134 will be described below with reference to the flow charts of FIGS. 38 to 40.

The SBCD circuit 134, by the processing shown in the flow chart of FIG. 38, continuously has N or more (three in this embodiment) sectors in which the IED check result is normal (ID has no error). Is determined.

Therefore, in the first step SP41, it is determined whether or not the IED check that has just been taken in is normal. If the IED check is normal, the process proceeds to step SP42, where the variable SA _lock representing the number of sectors with normal ID is incremented by one. Then, the variable SA _{unlock indicating the} number of consecutive sectors having an abnormal ID (ID has an error) is set to 0.

Next, in step SP43, the variable SA
_It is determined whether _lock is equal to 3. Step SP42
When it is determined that the variable SA _lock incremented in step 3 is not equal to 3, the process returns to step SP41 to repeat the subsequent processing. In step SP43,
When it is determined that the variable SA _lock is equal to 3, that is, when the sector having the normal ID is reproduced three times in succession, the process proceeds to step SP44 and the flag IECOK is set to H. In step SP45, the variable SA _lock is set to 2 in order to detect the number of times the next IED check is normal, and step SP41.
And the subsequent processing is repeatedly executed.

If it is determined in step SP41 that the IED is not normal, the process proceeds to step SP46, where the variable SA _unlock is incremented by 1 and the variable SA _lock is set to 0. And step SP47
In, it is determined whether or not the variable SA _unlock is equal to 3, and if it is not equal, the process returns to step SP41 and the subsequent processes are repeatedly executed.

At step SP47, the variable SA
_{If unlock} is determined to be equal to 3, ie IE
When the sector in which the D check is not normal is detected three times in a row, the process proceeds to step SP48, and the flag IECOK is set to L. Next, in step SP49, when the next IED check is not normal, the variable SA _unlock is set to 2 so that it is possible to continuously detect that the number of consecutive IED checks is three. , Step S
The process returns to P41, and the subsequent processes are repeatedly executed.

As described above, the SBCD circuit 134
Sets the flag IECOK to H when the IED check is normal for three or more consecutive times, and sets the flag IECOK when it is not normal for three or more consecutive times.
Is set to L.

The SBCD circuit 134 further determines the continuity of IDs (addresses) by the processing shown in FIG.
That is, the ID of each sector in one ECC block
Are specified to be sequentially incremented by one. Therefore, this continuity is determined as follows.

First, in step SP61, ID
(Sector address) is detected. I
If D is detected, step SP62 follows and the I
Store D so that it can be compared with the next ID.
Then, in step SP63, the I detected this time is detected.
It is determined whether D is larger than the ID previously detected and stored in step SP62 by one. If the current ID is one greater than the previous ID, step SP6
In step 4, the variable N _S indicating that correct IDs are continuously detected is incremented by 1. In addition, a variable N _{NS indicating the} number of times the ID is not detected or is not continuous.
Is set to 0.

Then, in step SP65, it is determined whether the variable N _S is equal to 3 or not (3
If the ID which has been incremented by 1 continuously is not detected), the process returns to step SP61 to repeat the subsequent processing. When it is determined that the variable N _S is equal to 3, the process proceeds to step SP66, and the flag AS indicating that the ID is continuously correct is set to H.
Then, in step SP67, when the next ID is detected, the variable N _S is set to 2 so that the correct ID can be detected three times in succession again, and the process returns to step SP61. Repeat the subsequent processing.

When it is determined in step SP61 that the ID has not been detected, or in step SP63 that the ID detected this time has not reached a value larger by 1 than the previously detected ID (judged to be discontinuous). In the case), the process proceeds to step SP68 to determine whether the flag SALK is H or not. This flag SALK is shown in FIG.
As will be described later with reference to, when the IED check is normal for three consecutive times or more and the ID continuity is maintained for three or more times, it is set to H.

At step SP68, the flag SAL is set.
If it is determined that K is set to H, step S
Proceeding to P69, the process of interpolating ID is executed. That is, the ID has not been detected, or the ID
Since it is a case where is not continuous, 1 in the previous ID
Is added to generate an ID, which is used instead of the detected ID. When the flag SALK is set to L, such an interpolation process is not performed and the process of step SP69 is skipped.

Next, in step SP70, the variable N
Increment _NS by 1 and set variable N _S to 0
Set to. Then, in step SP71, it is determined whether or not the variable N _NS is equal to 3. If it is determined that the variable N _NS is not equal to 3, the process returns to step SP61 to repeatedly execute the subsequent processing. On the other hand, if it is determined that N _NS is equal to 3, the process proceeds to step SP72 and the flag AS is set to L. And step SP
In 73, if the next ID is not detected, the variable N _NS is set to 2 and the process returns to step SP61 so that it can be continuously detected that it has not been detected three times in succession. , Repeat the subsequent processing.

As described above, the SBCD circuit 134
Sets the flag AS to H when the continuity of IDs is secured, and sets it to L when the continuity of IDs is not secured.

The SBCD circuit 134 uses the two flags IECK and AS generated as described above to generate the flag SALK.

That is, in step SP81 of FIG. 40, it is determined whether or not the flag IECOK is H, and if it is determined to be H, the process proceeds to step SP82 and whether or not the flag AS is H. To be judged. When it is determined in step SP82 that the flag AS is H, the flow proceeds to step SP83, and the flag ASLK is set to H.
Set to.

On the other hand, if it is determined in step SP81 that the flag IECOK is L, or if it is determined in step SP82 that the flag AS is L, the process proceeds to step SP84 to set the flag SALK. Set to L.

As described above, in the SBCD circuit 34, the IEC is normal for three times or more, and
When the ID is continuously incremented by 1 three times or more, the flag SALK is set to H and the IEC is not normal three times or more, or the ID is discontinuous three times or more. If so, the flag SALK is set to L.

The host CPU 140 refers to the above-mentioned ID data together with the state of SALK, and detects the position where the laser beam is currently irradiated (access position on the optical disk 2).

The result of PI1 correction is SA in FIG.
It is also possible to add to the conditions of _lock or SA _unlock . Furthermore, although the number of SA _locks or SA _unlocks is set to 3 times as described above, the host CPU 140
It is also possible to set different values depending on.

When the state of SALK is SALK = L (at this time, SALK = H), SYLK = L
(At this time, SYUL = H), the RAM 37
The writing of the EFM + demodulated data from the EFM + demodulation circuit 31 and the control of the ECC are reset. Thereafter, the unlocked state is released (SAUL =
L) and SYLK = H, the writing of EFM + demodulated data to the RAM 137 is restarted.

Unlock is the host CPU 14
It is also possible to force execution by setting 0. For example,
The ECC control can be reset by putting the host CPU 140 into the unlocked state after executing the jump between tracks.

The unlocking state can be released by the host CPU 140 or automatically without the intervention of the host CPU 140.

When SYLK is in the H state (lock state) and the bit 6 of the sector information is 1 (the beginning of the sector), the SBCD circuit 134 outputs SYLK =
Until it becomes L (until the lock is removed), block-top is set to H state as shown in FIG. blo
When ck-top = L, SCSY and main-
When both FMSY are in the H state (beginning of a sector), the value of EFM + W frame is set to 0 after 12. That is, in this case, EFM + W f
The value of frame repeats a value of 0 to 12 for each mainframe.

On the other hand, if block-top = H, as shown in FIG. 34, EFM + W Frame.
The value of is continuously incremented even when the value becomes 13 or more. As a result, as shown in FIG. 28, the data of each mainframe of each ECC block is stored in the RAM1.
It will be sequentially stored at 37 different addresses.

In the same manner, EFM + R of demodulated data
Writing to the AM 137 is performed and PI1 correction is performed. And the data of 1 ECC block (2
When the PI1 correction for the 08th row data) is completed, next, the ECC process (PO correction) in the PO column direction is executed.

When reading data in the PO column direction, it is necessary to cancel the interleaving of the PO row (FIG. 23). Therefore, for example, when reading the column of the N-th byte shown in FIG. 28, first, after reading the data of the column of the N-th byte from the top to the bottom of the figure while skipping the interleaved PO rows. , Again, only the code of the PO row in the same column of the Nth byte is read, and the ECC core circuit 1
38.

Then, when the ECC core circuit 138 finishes the PO correction (when the processing of all 172 columns except the PI column (10 columns) at the right end of FIG. 28 is finished), then PI2 correction (PI correction 2 Run the second time). The reason why the ECC processing in the PI row direction is performed twice is to improve the error correction capability.

In PO correction, erasure correction is executed according to the error flag (PI1 flag) generated based on the result of PI1 correction. Further, also in PI2 correction, erasure correction is executed using an error flag (PO flag) generated according to the result of PO correction. The reason for performing such erasure correction is to improve the error correction capability as in the case described above.

The PI series data for which the PI2 correction processing has been completed is transferred from the RAM 137 to the OCTL circuit 139, and the descrambling processing for the main data is performed as shown in FIG.
Using bits 3 to 0 of the sector information shown in 6,
It is executed in each sector unit. Also, at this time, OCTL
The circuit 139 performs the EDC calculation. And
Whether or not there is an error in the target sector is determined based on the result of the calculation and the presence / absence of an error flag added to the main data. The host CPU 140 determines whether to read the data from the optical disk 2 again based on the determination result. As a result, when it is determined that the data is read again from the optical disk 2, the optical disk 2
Is accessed again. When it is determined that the data is not read again, the sector data including the error is output to the multiplexed data separation circuit 13 (FIG. 1).

The ECC core circuit 138 is composed of a general-purpose Reed-Solomon code error correction LSI, and has a code length, a parity number, and a correction mode (normal correction only or normal correction and erasure correction modes).
It is possible to program such as. Also,
The ECC core circuit 138 can also decode multi-code consecutively encoded data (a plurality of code sequences having different code lengths) in real time. As the Reed-Solomon code error correction LSI, for example, Sony
(Trademark) CXD307-111G
Formed by using ASIC (Application Speciali
The zed integrated circuit) is called an ECC core. In addition,
This ECC core is used in the ECC core circuit 138 shown in FIG.

FIG. 41 shows the timing of signals during the execution of the error correction operation. In this figure, E
STT (FIG. 41 (A)) is a code (PI line or PO).
Control signal indicating the start of the
DE (FIG. 41 (B)) is a code (PI line or PO line)
Is a control signal indicating the end of the control signal. ECYE (Fig. 4
1 (C) is a control signal indicating the end of the code (PI row or PO row) cycle. These are all from the RAM controller 135 to the ECC control circuit 13
6 to the ECC core circuit 138. ECC
The core circuit 138 identifies the data supplied from the RAM 137 by these control signals.

As shown in FIG. 41, the PI code is EST.
182 ECCKs are transferred between T and EDCE. The PO code is also transferred by 208 ECCKs from ESTT to ECDE.

When the code lengths of the code of the PI row and the code of the PO column are different, the code cycle length of the code of the PI row and the code of the PO column, whichever has the longer code length (in this embodiment, PO is used). 41), the data to be corrected (EDT) and the error flag (PI1 flag, PI2 flag, PO flag) for erasure correction can be adjusted by any code sequence as shown in FIG. Even if you attach it, you can enter it at the same timing. Further, it is possible to set arbitrary values as parameters such as code length and number of parity. That is, when changing the setting, if new setting data is supplied to the ECC core circuit 138 at the timing when ESTT = H, the ECC
The core circuit 138 automatically changes the internal setting based on the supplied data.

The data correction result is output in a cycle of 477 ECCK as shown by the following equation. throughput = 2 × NCYC + 3 × PCCYC + 13 = 2 × 208 + 3 × 16 + 13 = 477 (ECCK)

Here, NCYC is the code of PI line or P
Indicates the longer code length of the O column code.
YC indicates the longer parity number. As shown in FIG. 41, OSTT (FIG. 41 (D)) is equivalent to ESTT (FIG. 4).
The ECC is delayed from the timing of 1 (A) by the time of the data output cycle (at the timing of outputting the correction result).
It is output from the core circuit 138 to the ECC control circuit 136, and in this embodiment, the OSTT is delayed by 477 ECCK with respect to the ESTT.

If the error detection processing is executed and the detected error can be corrected, the ECC core circuit 138 determines that the EC
For the C control circuit 136, the OSTT (FIG. 42 (E))
= O at the timing of H. CODEERR (Fig. 42
(G)) = L and then outputs ECOR (FIG. 42).
(F)) = H data of 8 bits representing the error pattern (correct data is obtained when exclusive OR is performed with erroneous data) ECD [7: 0] (FIG. 4)
2 (H)) and an error position (8-bit data indicating a position (address) where an error occurs) ECA [7:
0] (FIG. 42 (I)) is output.

In the erasure correction mode,
Error position ECA of data corresponding to the position in which the error flag EFLG (FIG. 42 (C)) is input
[7: 0] (FIG. 42 (I)) data is always output, but if the data at that position is correct, the error pattern is ECD [7: 0] = 00 (H).

When error correction is impossible, the timing chart is not shown, but
(FIG. 42 (E)) becomes the H state, and at the same time, the O. CO
DEERR (FIG. 42 (G)) = H, and then EC
OR (FIG. 42 (F)) is not in the H state. Also,
O. The output of CODEERR (Fig. 42 (G)) is OST.
T (FIG. 42 (E)) is latched until it becomes H state again, and ECOR (FIG. 42 (F)), ECD [7: 0] (FIG. 42 (H)) and ECA [7: 0] (FIG. 42 (I))
Continues to be output until the OSTT (FIG. 42 (E)) becomes the H state next time.

43 to 45 are timing charts of control at the time of executing the ECC processing. Here, FIG.
PI1-shown in (B), FIG. 44 (B) and FIG. 45 (B)
R, PO-R, or PI2-R are respectively PI
1 (first PI correction), PO (PO correction), or P
The error-corrected data EDT [7: 0] and EFLG (FIG. 42) of each I2 (second PI correction) series.
(C) shows the timing of transfer from the RAM 137 to the ECC core circuit 138 via the ECC control circuit 136.

43 (A), 44 (A) and 45.
As shown in (A), EFM + demodulation circuit 131 to RA
1PI row of data EFM + W (182 for M137)
MWRQ signal is 1 to write byte data)
It is supplied 82 times, and as a result, the EFM + demodulated data for one PI row is written in the RAM 137. And this one
While writing data for PI lines, RA has already been completed.
The data of the ECC block that has been written to M137 is read out, and the EC is read via the ECC control circuit 136.
It is transferred to the C core circuit 138. That is, while the data for one PI row is written in the RAM 137 in a loose manner, the reading of the data of another PI row or PO column which has already been written is rapidly performed three times. Further, when the data of the PI row at the head of the sector is transferred, the subcode data (ID and IED) is also read. When one of these writing and reading is performed, the other is stopped.

For example, in the case of performing PI1 correction of the ECC block, the data of 1 PI row is read during the period of writing the data of 1 PI row. That is, data for one PI row is read from the RAM 137 and transferred to the ECC core circuit 138 via the ECC control circuit 136. Note that FIG. 43B and FIG.
In (B) and FIG. 45 (B), the read data PI1-R for this PI1 correction is read 208
I am trying to use one ECCK, but this ECCK
This is because the number of is matched to the length of the PO column, which is the longest data length, and when transferring the data of the PI row,
Practically, only 182 ECCKs of these are used for actual data transfer, and the remaining ECCKs are not actually used for data transfer.

FIG. 46 shows a procedure for writing and reading data to and from the RAM 137 by the RAM controller 135 at the time of ECC correction processing. The RAM controller 135 transfers data for one PI line from the RAM 137 to the ECC core circuit 138 in step SP101. . In the case of this embodiment, since the PI code (parity) and the PO code (parity) are added to each ECC block, the first P for the first ECC block is added.
Same ECC until I series correction and write back are completed
Block PO series data PO-R or PI2 series read data PI2-R cannot be transferred. Therefore, in this case, the next 2 × 208 EC
No data is transferred at the timing of CK. Then, if subcode data (SUB) is present next, this is transferred.

Therefore, the RAM controller 135 is shown in FIG.
In step SP101 and SP102, the PI1-R data of 208 lines of the first ECC block is sequentially transferred in step SP103 while sequentially transferring the data of one PI line of the first ECC block and the SUB code data as needed. Is transferred, and the steps SP101 and SP10 concerned are determined until a positive result is obtained.
2 and SP103 are repeated. Step SP10
If a positive result is obtained in step 3, this means that the first E
This indicates that the data transfer for 208 PI rows of the CC block is all completed, and at this time, the RAM controller 135 moves to step SP104 and transfers PI1-R of the second ECC block following the first ECC block and the second ECC block. Transfer the ECC block PO-R 1 of the following 182
It starts in the period of MWRQ.

That is, in the next 182 MWRQ period, PI1-R of the second ECC block following the first ECC block is transferred first, and then PO-R of the first ECC block is transferred twice. (PO data for two columns is transferred).

When such an operation is performed in each 182 MWRQ period and a total of 172 columns of PO data of the first ECC block are transferred, the RAM controller 1
35, a positive result is obtained in step SP105 of FIG. 46, and in the subsequent step SP106, as shown in FIG. 45, the data PI2 of the PI2 series of the first ECC block.
-Transfer R. This data PI2-R is shown in FIG.
Data is transferred at the same timing as the transfer timing of the data PO-R of the first ECC block shown in FIG. The data PI1-R at this timing is the data of the next ECC block (second ECC block). In this way, the first ECC block PI2-R
Is transferred for 208 PI lines, and P of the first ECC block
When the processing of I1-R, PO-R, and PI2-R is completed, a positive result is obtained in step SP107 of FIG. 46, at which time the RAM controller 135 returns to step SP101 and continues the processing for the ECC block that follows.

ECCK (FIG. 42A) is output from the RAM controller 135 to the ECC core circuit 138 only during the data transfer period. Further, as described above, the correction result of the transferred data is
It will be output after 477 clocks (ECCK). Therefore, the result (FIG. 43 (C), FIG. 44 (C), FIG. 45 (C)) of determining whether or not the data of a certain series includes an error, It will be output when the data is transferred (FIG. 43 (B),
44 (B) and 45 (B)). This output is stored in the ERR FIFO circuit 136B (FIG. 47) described later.

As described above, the EC is read from the RAM 137.
When the data to be error-corrected is input to the C control circuit 136, the ECC control circuit 136 performs PI1 correction of the data for one PI row, for example, and outputs the correction result after 477 ECCK (FIG. 43 (C), FIG. 44 (C), FIG.
(C)). This correction result is the ECC control circuit 1 described later.
36 is transferred to the ERR FIFO 136B as a buffer and temporarily stored. And this data is
Further, the data read from the ERR FIFO 136B is transferred to the RAM 137 again as the data for which the error correction is completed, and is written as the data PI1-W as shown in FIGS. 44 (D) and 45 (D). Similarly, the data for which the PO correction or the PI2 correction is completed is written in the RAM 137 as the data PO-W or PI2-W, respectively.

As described above, the error-corrected data written in the RAM 137 is further stored in FIG.
As shown in FIGS. 44 (E) and 45 (E), 182S
It is read for each PI row in the cycle of DCK and output from the OCTL circuit 139.

FIG. 47, in which parts corresponding to those in FIG. 25 are assigned the same reference numerals, is a block diagram showing the flow of signals when error correction processing is executed. The ECC control circuit 136
ERR COUNT 136A, ERR FIFO 136
B, FLAG RAM 136C, and EX-OR (exclusive OR) circuit 136D.

Under the control of the RAM controller 135, the demodulated data output from the EFM + demodulation circuit 131 is R
Written to AM 137. The SUB data (ID and IED) stored at the beginning of each sector is stored in the RAM 137.
Is read out from and is transferred to the SBCD circuit 134. S
The BCD circuit 134 uses the sector information S as shown in FIG.
Generate I. This sector information SI is the SBCD circuit 1
34, and written in the RAM 137.

The RAM controller 135 is the RAM 13
The data for 1 PI line written in 7 (storage means) is used as the error correction data EDT for every 8 bits, ECC
It is supplied to the ECC core circuit 138 via the control circuit 136 (error correction means) (in FIG. 47, for convenience, E
DT data is shown fed directly to the ECC core circuit 138). The ECC core circuit 138 has 1PI
When the data for a row is supplied, the PI code is used to
Bit error correction data ECD (FIG. 42 (H)),
8-bit error correction address ECA (Fig. 42 (I))
Generate The error correction data ECD and the error correction address ECA are transmitted from the ECC core circuit 138 to the ERR FIFO (First In First Ou) of the ECC control circuit 136.
t) Transferred to 136B and written.

Next, in order to actually perform error correction, RA
The M controller 135 reads the PI from the RAM 137.
The row data EDT is read and the EX-OR circuit 136D is read.
To supply. This EX-OR circuit 136D has an ERR
The error correction data ECD and the error correction address ECA are supplied from the FIFO 136B. EX-OR circuit 1
36D performs error correction by calculating the exclusive OR of the error correction data ECD and the data EDT read from the RAM controller 135 at the bit designated by the error correction address ECA. The error-corrected data is transferred from the EX-OR circuit 136D to the RAM 137 via the RAM controller 135.
Will be written back again.

Further, the ECC core circuit 138 generates an error correction result ER composed of 8-bit data as shown in FIG. 48 from the ECD and ECA, and supplies it to the ERR COUNT 136A of the ECC control circuit 136 for storage. Then, this 1-byte error correction result ER is
Via the RAM controller 135, to the RAM 137,
It is written as shown in FIG. 28 corresponding to the PI row.

The following information is stored in each bit of the 8-bit data of the error correction result ER shown in FIG. Bit 7: Uncorrectable (0: Correctable / 1: Uncorrectable)
(It is set to 1 when the error correction of the series is impossible) Bit 6: PO (0: PI / 1: PO) (The series is P
Information bit for determining whether I or PO) Bit 5: PI2 (0: PI1 / 1: PI2) (Information bit for determining whether the series is PI1 or PI2) Bit 4: Correction number (5th bit of error correction number (MS
Value of B) Bit 3: Correction number (4th bit value of error correction number of 4 bits) Bit 2: Correction number (3rd bit value of error correction number of 4 bits) Bit 1: Correction number (4) Value of the second bit of the number of error corrections of the bit) Bit 0: Number of corrections (the value of the first bit of the number of error corrections of 4 bits)

An error flag (PI1 flag) (bit 7 of the error correction result ER) indicating the result of determination as to whether or not the data is uncorrectable by PI1 correction is stored in the ERR COUNT 136A as a part of the error correction result ER. Besides, it is also stored in the FLAG RAM 136C (flag storage means). The above PI1 correction is shown in FIG.
This is performed for 208 PI rows shown in FIG.

Next, the RAM controller 135 sends the RA
The 208-byte data of the first PO column is read from M137, and is supplied to the ECC core circuit 138 as EDT via the ECC control circuit 136. The PI1 flag written in the FLAGRAM 136C is also read and supplied to the ECC core circuit 138. E
The CC core circuit 138 uses the pattern PO and the PI1 flag to perform E for normal correction or erasure correction.
Generate CD and ECA. This ECD and ECA are EC
ERR of the C core circuit 138 to the ECC control circuit 136
It is supplied to the FIFO 136B and stored therein. Also, EC
The error correction result ER of the PO column generated by the C core circuit 138 based on ECD and ECA is ERR CO
It is transferred to UNT 136A and stored. Then, the PO flag corresponding to bit 7 of the error correction result ER among them is also written in the FLAG RAM 136C.

The PO read from the RAM 137
The column data EDT is supplied to the EX-OR circuit 136D. The EX-OR circuit 136D also has an ERR FI
ECD and ECA are supplied from FO136B. EX-
The OR circuit 136D calculates the exclusive OR of ECD and EDT in response to the bit of the address designated by the ECA, and corrects the error. The error-corrected data is written back to the RAM 137.

The error correction result ER of the PO column
Is read from ERR COUNT 136A and RA
Written to M137. Error correction result ER for PO column
As shown in FIG. 28, P in the 172th row is arranged in order from the top.
The data is sequentially written in the position corresponding to the I row. PO above
The correction is performed on the 172 PO columns.

Next, in the case of performing PI2 correction,
After PI1 correction and PO correction are performed, the data of the first 1PI row is read from the RAM 137 as EDT and supplied to the ECC core circuit 138. The PO flag written in the FLAGRAM 136C is also read and supplied to the ECC core circuit 138. The ECC core circuit 138 uses this PO flag and parity PI to
ECD and ECA are generated, and the ECC control circuit 13
6 to the ERR FIFO 136B.

The ECD and ECAH written in the ERR FIFO 136B are supplied to the EX-OR circuit 136D, the exclusive OR operation is performed with the PI row data read from the RAM 137, and error correction is executed. . The data for which the error correction is completed is the EX-OR circuit 1
RAM from 36D via RAM controller 135
It is written back to 137.

The ECC core circuit 138 also uses the ECD and E
The error correction result ER is generated from CA, supplied to the ERR COUNT 136A of the ECC control circuit 136, and stored therein. The PI2 flag corresponding to bit 7 is
It is also written in the FLAG RAM 136C.

The error correction result ER of the PI2 row written in the ERR COUNT 136A is ERR COUNT
It is read from T136A and written in the RAM 137. The error correction result ER of the PI2 row is written in a position corresponding to each PI row of 208 rows of the ECC block, as shown in FIG. The above PI2 correction is
This is performed for all 208 PI lines.

FIG. 49 is a timing chart showing a state of bus arbitration (arbitration) when accessing the RAM 137. In FIG. 49, EFMREQ (FIG. 49 (A)) indicates that EFM + demodulation circuit 131 requests writing of EFM + demodulation data to RAM 137.
This is a signal output to the RAM controller 135. OUTREQ (FIG. 49 (B)) is the OCTL circuit 1
When the RAM 39 requests reading of the ECC-processed data from the RAM 137, the RAM controller 13
It is a signal output to 5. In addition, ECCREQ (Fig. 49
In (C), the ECC control circuit 136 has the ECC core circuit 1
38, data is transferred to 38, RAM 137 is accessed for error correction, RAM 137 is accessed for error-corrected data,
Alternatively, the SUB transfer (ID
And the signal output to the RAM controller 135 of the IED.

The RAM controller 135 presets the priority order (PriorityLevel) for these three signals, and when these requests are made at the same time, the access right of the RAM 137 is assigned in accordance with the priority order. Acknowledge ACK (authorization) signals are sequentially output. EFMACK
(FIG. 49 (D)), OUTACK (FIG. 49 (E)), E
CCACK (FIG. 49 (F)) is the EFMRE, respectively.
It is an authorization signal for Q, OUTREQ, or ECCREQ. In this example, the priorities are:
The order is OUTREQ, EFMREQ, and ECCREQ. Therefore, as shown in FIG. 49, the RAM controller 135 outputs the ACK signal for the REQ signal in this order. These signals are transmitted / received in synchronization with C11M (FIG. 49 (G)) as the system clock.

Thus, in this embodiment, the RAM1
The access right of 37 is EFMRE every predetermined cycle.
It is given in correspondence with any one of Q, ECCREQ, and OUTREQ. However, this cycle is
It is also possible to change according to the configuration, type, or access speed.

FIG. 50 shows the number of times the RAM 137 is accessed when PI1 correction, PI2 correction, and PO correction are executed on 1 ECC block data. As shown in FIG. 50, RAM1 required when PI1 correction, PO correction and PI2 correction are executed
37 times of access is 21 per 1 ECC block
4716 times, the average of one mainframe is 1033
Times. For example, the number of times the RAM 37 is accessed during the write operation of EFM + demodulated data is 182 per mainframe, and the ECC execution cycle length is 208 bytes (208 mainframes), so 37856 (= 182 × 208). ) Is the number of accesses required per block. In this way, the number of accesses required for each operation is calculated, and the sum of these is the above-mentioned value.

FIG. 51 is a timing chart showing the timing of outputting the data of the error correction result ER from the RAM 137 via the OCTL circuit 139. This figure is
182SDC of 3 (E), FIG. 44 (E), and FIG. 45 (E)
The part preceding the period K is shown with the time axis enlarged. In this figure, SDCK (Fig. 51 (A)) is ER
7 shows a clock signal when the above data is output as stream data. SINF (FIG. 51 (B)) is a sector information strobe signal, which is SIN at the beginning of the sector.
It indicates that F = H and the data to be transferred is sector information (SI). ESTB (Fig. 51 (C))
Is an error correction result strobe signal, and ESTB =
When it becomes H, it indicates that the error correction result ER is transferred. The error correction result ER in each PI line
Since 1 byte is assigned to each of PI1 correction, PO correction, and PI2 correction, is a total of 3 bytes. Since these data are output in the order stored in FIG. 28, it is possible to determine which series of results (data) by checking the bits 5 and 6 (FIG. 48) of the error correction result ER. You can In the PI line where the result of PO correction is not output,
At the timing of outputting the PO correction result, ESTB = L.

DSTB (FIG. 51 (D)) is a signal SD
[7: 0] (FIG. 51 (E)) is a data strobe signal that sets DSTB = H when it is main data.
The three signals SINF, ESTB, or DSTB are:
It is generated by the OCTL circuit 139. Note that FIG.
As shown in (E), the sector information SI and the error correction result ER are output immediately before the data in the PI row direction is transmitted by 182SDCK.

OUTF (interpolation flag) (FIG. 51 (F))
Is an error flag for the main data, and FIG.
PI and P stored in the FLAG RAM 136C of
Based on the O uncorrectable flag, the main data having an error is added with an interpolation flag and then output.

The OCTL circuit 139 determines from the bits 4 and 5 (FIG. 36) of the sector information generated by the SBCD circuit 134 whether or not the data of the sector which has been decoded is the data to be output. Bits 4 and 5 of the sector information respectively indicate an end sector and a start sector, as shown in FIG. Therefore, the OCTL circuit 139 outputs the data of the sector whose bit 4 = 0 and bit 5 = 1 as the data of the sector whose output is designated (should be output).

The OCTL circuit 139 also determines whether or not the presence or absence of an error flag in the main data, the EDC result, and the like satisfy the conditions preset by the host CPU 140, and if so, decode the decoded data. Output. If the set output condition is not satisfied, the output of the decoded data is stopped and the host CP
Notify U140 of abnormality.

The data output conditions are set as follows, for example. (1) Data of a sector whose output is specified. (2) No error is detected from the ECC result. (3) No error flag is added to the main data. When the output conditions are set as described above, data satisfying all of these conditions is finally output. Further, regardless of the above conditions, the output can be forcibly prohibited by the host CPU 140.

The OCTL circuit 139 sequentially outputs main data, sector information SI and error correction result ER in accordance with the sector data output procedure as shown in FIG.
First, the OCTL circuit 139 analyzes the end sector detection result stored in the bit 4 of the sector information SI (FIG. 36) and the start sector detection result stored in the bit 5 in the OCTL circuit 139 in step SP111. , Sector 4 in which bit 4 is 0 and bit 5 is 1 is determined to be the sector data to be output. As a result, if it is determined in the next step SP112 that the decoded data is not the data to be output, the process proceeds to step SP114 and the data output is stopped. If it is determined that the decoded data is the data to be output that satisfies the output condition, the process proceeds to step SP113.

The OCTL circuit 139 is connected to the step SP113.
At the strobe signal SINF of the sector information SI (see FIG. 51).
(B)), strobe signal EST of error correction result ER
B (FIG. 51C), strobe signal D of main data
STB (FIG. 51 (D)) is output in order. As a result, O
In the next step SP115, the CTL circuit 139 receives the sector information SI, the error correction result ER and the main data (D0,
Data is output in the order of D1, D2 ...) and all sectors
When the data output is completed, the sector data output procedure is completed.

(2-3) Operation and effects of the second embodiment With the above configuration, the RAM1 is operated within the 182 MWRQ period.
Data transferred from 37 to the ECC core circuit 138 (P
I1-R, PO-R and PI2-R (Fig. 43, Fig. 44,
Fig. 45)) shows R depending on the transfer clock (ECCK).
It is read from AM137. At this time, each data (PI
1-R, PO-R, and PI2-R), the transfer clock (ECCK) is stopped for a predetermined period between transfer sections, so that the data (PI1-R, PO-R, and PO-R) is stopped during the stop period. PI2-R) transfer is stopped. That is, a period in which no data is transferred is formed between the respective data (PI1-R, PO-R, and PI2-R) for a predetermined period.

During this period, the RAM controller 1
35 is RAM1 after the execution of PI1 correction (PI1-W)
The sector address information (ID) and the error detection code (IED) for the ID stored in the number 0 mainframe in 37 are SUB (FIG. 43 (B), FIG. 45 (B)).
At the timing of, the data is read and transferred to the SBCD circuit 134. The SBCD circuit 134 uses the sector address information ID
Is detected, the start sector address BSA of that sector is detected.
And end sector address ESA and host CPU 140
To compare with the sector address of the target sector to be output which is designated in advance. That is, when the sector is the target sector, the bit 5 of the sector information SI is set to "1" to indicate that it is the start sector address BSA of the target sector, and the detection bit 4 of the end sector address ESA is set. Is set to "0". And SB
The CD circuit 134 sets in the bits 4 and 5 of the sector information SI whether or not the sector data in which the sector address information ID is detected is the target sector, and then stores the sector information SI in the RAM 137 so as to correspond to a predetermined PI row. It is stored in a small area provided in.

Here, the RAM controller 135 uses the EF
EC when writing M + demodulated data to RAM 137
The sector data decoded in the C circuit 50 is transferred to the OCTL circuit 139. OCTL circuit 139
Is the sector information SI in the transferred sector data.
Is detected, whether or not the sector data is the target sector is determined according to the information of bits 4 and 5 of the sector information SI, and the output to the ring buffer memory 10 at the next stage is controlled.

Thus, in the SBCD circuit 134,
In the small area provided in the RAM 137, the start sector address BSA and the end sector address ESA are detected to generate sector information SI regarding whether or not the target sector is preset by the host CPU 140. By storing the decoded data in the OCTL circuit 139, the output of the decoded data can be controlled in the OCTL circuit 139 based on the sector information SI. As a result, for example, the step of comparison processing with the sector address of the target sector preset by the host CPU 140 based on the detected sector address information ID can be omitted.

According to the above configuration, the ECC-decoded EC
When the main data of the C block data is output to the ring buffer memory 10 in the next stage, the SBCD circuit 1 is used in advance.
In 34, the information as to whether the sector data is the target sector at the time of ECC decoding is recorded in the bits 4 and 5 of the sector information SI, so that the sector address information ID and the target sector are again output at the time of data output. It is possible to omit the step of comparing with the sector address of No. 1 to determine whether data can be output. Thus sector-by-sector ECC
When outputting the decode, it is not necessary to newly provide a circuit for detecting the sector address information ID from the ECC decoded data and comparing the sector address information ID with the sector address, so that the entire circuit configuration can be simplified and the sector data can be processed. Access can be made quickly and reliably.

Further, according to the above embodiment, the RAM 13
By storing the sector information SI in a small area provided in 7, it is not necessary to provide a special memory area for sector detection, and the memory capacity can be saved.

Further, according to the above-mentioned embodiment, since the PI series and the PO series are blocked and the ECC processing is performed, the ECC of the C1 series and the C2 series is obtained.
The ring buffer memory 1 immediately after the completion of the decoding of one ECC block without waiting for the completion of the decoding of the diagonal C2 sequence straddling the next ECC block as in the case of encoding.
Whether data can be output to 0 can be determined.

(3) Other Embodiments In the above embodiment, C1 / C2 convolution / Reed-Solomon coding, or error correction inner code is added in the row direction and error correction outer code is added in the column direction. Although the case where the data encoded by the above is decoded is described, the present invention is not limited to this and can be widely applied to the decoding of the encoded data to which the error correction code is added generally by interleaving or cross interleaving. In the above embodiment,
The case where the encoded data is an error correction code has been described, but the present invention is not limited to this, and can be widely used for decoding encoded data in general.

Further, in the above-mentioned embodiment, the case where the data reproducing device 40 decodes and reproduces the encoded data recorded in the optical disk 2 has been described. However, the present invention is not limited to this, and generally the code The present invention can be applied to a case where encoded data is read from a recording medium in which encoded data is recorded, decoded and reproduced.

[0205]

As described above, according to the present invention, during the decoding of the encoded data recorded on the recording medium, the data information of the data to be read is detected and stored in the data information storage means. By doing so, it is possible to realize a data decoding apparatus and method that can control the output of decoded data based on the data information independently of the decoding of encoded data.

Further, according to the present invention, during decoding of the encoded data recorded on the recording medium,
By detecting the data information of the data to be read and storing it in the data information storage means, it is possible to control the output of the decoded data based on the data information independently of the decoding of the encoded data. Therefore, it is possible to realize a data reproducing device that can reproduce the decoded data quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a data reproducing device.

FIG. 2 is a block diagram showing the configuration of the ECC circuit of FIG.

FIG. 3 is a block diagram for explaining the connection of the demodulation circuit, sector detection circuit, and ECC circuit of FIG.

FIG. 4 is a schematic diagram used to explain data stored in the RAM of FIG.

5 is a schematic diagram for explaining an ECC result by the ECC circuit of FIG.

FIG. 6 is a timing chart for explaining execution control of ECC decoding by the ECC circuit of FIG.

FIG. 7 is a timing chart used for explaining error output by the ECC circuit of FIG.

FIG. 8 is a table provided for explaining access to RAM of the ECC circuit of FIG.

9 is a timing chart used for explaining the priority order of access to the RAM of the ECC circuit of FIG.

FIG. 10 is a schematic diagram showing a frame structure of reproduction data.

FIG. 11 is a schematic diagram for explaining a sector format of demodulated data.

FIG. 12 is a chart for explaining sector information.

FIG. 13 is a timing chart used for explaining setting of a sector address.

FIG. 14 is a timing chart used for explaining sector detection and data output.

FIG. 15 is a timing chart used for explaining sector detection and data output.

FIG. 16 is a timing chart used for explaining sector detection and data output.

FIG. 17 is a timing chart used for explaining sector detection and data output.

FIG. 18 is a timing chart used for explaining sector detection and data output.

FIG. 19 is a timing chart used for explaining sector detection and data output.

FIG. 20 is a timing chart for explaining sector detection and data output.

FIG. 21 is a schematic diagram showing the structure of sector data according to the second embodiment.

FIG. 22 is a schematic diagram showing the configuration of an ECC block of the second embodiment.

FIG. 23 is a schematic diagram showing interleaving of PO parity (outer code) according to the second embodiment.

FIG. 24 is a schematic diagram showing the data structure of a 32 Kbyte block before EFM modulation according to the second embodiment.

FIG. 25 is a block diagram showing the configuration of the demodulation circuit system of the second embodiment.

FIG. 26 is a schematic diagram showing a configuration of a physical sector of an EFM modulation signal according to a second embodiment.

FIG. 27 is a schematic diagram showing a data configuration of each sector of the second embodiment.

FIG. 28 is a schematic diagram for explaining the storage state in the RAM of the second embodiment.

FIG. 29 is a signal waveform diagram showing an operation of writing the EFM demodulation output of the second embodiment into RAM.

FIG. 30 is a flowchart showing a lock detection processing procedure of the second embodiment.

FIG. 31 is a flow chart showing the procedure of SCSY signal generation processing according to the second embodiment.

FIG. 32 is a flowchart showing a main-FMSY signal generation processing procedure according to the second embodiment.

FIG. 33 is a signal waveform diagram for explaining a block-top detection operation of the second example.

FIG. 34 is a signal waveform diagram for explaining a processing operation after block-top detection in the second embodiment.

FIG. 35 is a signal waveform diagram for explaining the transfer operation of the SUB of the second example.

FIG. 36 is a schematic diagram showing the structure of sector information according to the second embodiment.

FIG. 37 is a timing chart for explaining setting of a sector address according to the second embodiment.

FIG. 38 is a flow chart showing the procedure of the IED continuous normality detection determination process of the second embodiment.

FIG. 39 is a flowchart showing an ID (address) continuity determination processing procedure according to the second embodiment.

FIG. 40 is a flow chart showing a SALK generation processing procedure of the second embodiment.

FIG. 41 is a signal waveform diagram for explaining the error correcting operation of the second embodiment.

FIG. 42 is a signal waveform diagram for explaining the error correction operation of the second embodiment.

FIG. 43 is a timing chart for explaining a control operation of ECC processing of the second embodiment.

FIG. 44 is a timing chart for explaining the control operation of the ECC processing according to the second embodiment.

FIG. 45 is a timing chart for explaining the control operation of the ECC process of the second example.

FIG. 46 is a flowchart showing the processing procedure of the RAM controller for the ECC processing according to the second embodiment.

FIG. 47 is a block diagram showing the configuration of the error correction circuit system of the second embodiment.

FIG. 48 is a schematic diagram showing an error correction result of the second embodiment.

FIG. 49 is a signal waveform diagram for explaining the bus arbitration of the second embodiment.

FIG. 50 is a schematic diagram showing the number of RAM accesses in the 1ECC block correction of the second embodiment.

FIG. 51 is a signal waveform diagram for explaining the output of the error correction result of the second embodiment.

FIG. 52 is a flow chart for explaining output of sector data according to the second embodiment.

FIG. 53 is a block diagram showing a conventional data reproducing device.

FIG. 54 is a block diagram showing the ECC circuit of FIG. 53.

FIG. 55 is a schematic diagram for explaining ECC decoding by the ECC circuit in FIG. 54.

56 is a schematic diagram for explaining ECC decoding by the ECC circuit in FIG. 54.

FIG. 57 is a schematic diagram for explaining ECC decoding by the ECC circuit in FIG. 54.

FIG. 58 is a schematic diagram for explaining ECC decoding by the ECC circuit in FIG. 54.

[Explanation of symbols]

1, 40 ... Data reproducing device, 2 ... Optical disk, 3 ...
… Pickup 4 …… System controller 5,3
5 ... Demodulation circuit system, 6 ... Demodulation circuit, 7 ... Sector detection circuit, 8, 50 ... ECC circuit, 9 ... Track jump jump determination circuit, 10 ... Ring buffer memory, 11 ...
Ring buffer control circuit, 13 ... Multiplexed data separation circuit, 14 ... Header separation circuit, 15 ... Separation circuit control circuit, 16 ... Switching circuit, 17 ... Video code buffer, 18 ... Video decoder, 19 ... … Audio code buffer, 20… Audio decoder, 22
...... Tracking servo circuit, 24, 26, 28, 3
0,51 ... RAM, 25,27,29,52 ... EC
C decoder, 42 ... RF processing circuit, 44, 131 ...
EFM + demodulation circuit, 46 ... CLV control circuit, 48 ...
RMIF, 53 ... Error register, 54 ... ECC control unit, 55 ... ECC decoding unit, 56, 139 ... OCT
L circuit, 134 ... SBCD circuit, 135 ... RAM controller, 136 ... ECC control circuit, 137 ... R
AM, 138 ... ECC core circuit, 140 ... Host C
PU.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoru Kimura 6-7-35 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (29)

[Claims] 1. A data decoding apparatus for decoding coded data recorded on a recording medium, comprising: a decoding memory for storing the coded data and decoded data decoded from the coded data; and the coded data. A data information detection circuit that detects the data information of the data to be read from the decoded data that is generated during decoding, a data information storage unit that stores the data information, and the decoded data based on the data information. And a data output control circuit for controlling the output of the data decoding device. 2. The data decoding apparatus according to claim 1, wherein the recording medium is a disk recording medium. 3. The data information is sector information about the disk recording medium.
The data decoding device according to. 4. The data decoding device according to claim 2, wherein the data information detection circuit detects a sector of data to be read on the disk recording medium based on the data information. 5. The sector information comprises sector address information and error correction result and / or read sector address information of the disk recording medium.
The data decoding device according to. 6. The data decoding apparatus according to claim 1, wherein the memory has a first-in first-out (FIFO) function. 7. The data decoding apparatus according to claim 1, wherein the coded data is interleave coded. 8. The data decoding apparatus according to claim 1, wherein the coded data is error correction coded data. 9. The error correcting code is a C1 / C2 convolutional / Reed-Solomon code.
The data decoding device according to. 10. The data according to claim 1, wherein the error correction code is formed by adding an error correction inner code in a row direction of the encoded data and an error correction outer code in a column direction. Decoding device. 11. The data decoding apparatus corrects the data in the row direction, to which the inner code for error correction is added, by a first block in units of rows, and corrects the data in the column direction to which the outer code for error correction is added. Data is error-corrected by the first block in units of columns, and the error-correction inner code is error-corrected by the first block in units of rows. The data decoding apparatus according to claim 10, wherein the error correction is performed again. 12. The data decoding device, when the row direction data for one row or the column direction data for one column is completely transferred from the memory, the error stored in the register at the timing. The data decoding device according to claim 10, wherein error correction is performed based on the position and the error pattern. 13. A data decoding method for decoding coded data recorded on a recording medium, wherein the coded data read from the recording medium is stored in a decoding memory to decode the coded data. Data characterized by detecting data information of data to be read from the decoded data generated on the way, storing the data information, and controlling output of the decoded data based on the data information. Decryption method. 14. The data decoding method according to claim 13, wherein the recording medium is a disk recording medium. 15. The data decoding method according to claim 14, wherein the data information is sector information about the disk recording medium. 16. The data decoding method according to claim 13, wherein the data information detection circuit detects a sector of data to be read based on the data information. 17. The data decoding method according to claim 15, wherein the sector information comprises sector address information of the disk recording medium, an error correction result, and / or read sector address information. 18. The data decoding method according to claim 13, wherein the memory has a first-in first-out (FIFO) function. 19. The data decoding method according to claim 13, wherein the coded data is interleave coded. 20. The data decoding method according to claim 13, wherein the coded data is error correction coded data. 21. The data decoding method according to claim 20, wherein the error correction code is a C1 / C2 convolutional / Reed-Solomon code. 22. The error correction code comprises an error correction inner code added in the row direction of the encoded data and an error correction outer code added in the column direction.
The data decoding method described in. 23. In the data decoding method, the data in the row direction to which the inner code for error correction is added is error-corrected by a first block for each row, and the data in the column direction to which the outer code for error correction is added is corrected. Data is error-corrected by the first block in units of columns, and the error-correction inner code is error-corrected by the first block in units of rows. 23. The data decoding method according to claim 22, wherein the error correction is performed again. 24. The data decoding method according to claim 13, wherein the data decoding method decodes moving image data that has been compression-encoded. 25. A data reproducing apparatus for reading and reproducing an image signal and / or an audio signal composed of encoded data recorded on a recording medium, wherein the encoded data and decoded data decoded from the encoded data are stored. A decoding memory, a data information detection circuit for detecting data information of the data to be read from the decoded data generated during the decoding of the encoded data, and a data information storage means for storing the data information. A data reproducing device having a data output control circuit for controlling the output of the decoded data based on the data information. 26. The data reproducing apparatus according to claim 25, wherein the error correction code is a C1 / C2 convolutional / Reed-Solomon code. 27. The error correction code is formed by adding an error correction inner code in the row direction of encoded data and an error correction outer code in the column direction of the encoded data.
A data reproducing apparatus according to claim 1. 28. The data reproducing device corrects the data in the row direction to which the inner code for error correction is added by a first block for each row, and to correct the data in the column direction to which the outer code for error correction is added. Data is error-corrected by the first block in units of columns, and the error-correction inner code is error-corrected by the first block in units of rows. 26. The data reproducing apparatus according to claim 25, wherein error correction is performed again. 29. The data reproducing apparatus, when the row direction data for one row or the column direction data for one column is completely transferred from the memory, the error stored in the register at the timing. The data reproducing apparatus according to claim 25, wherein error correction is performed based on a position and error correction pattern.