JPH09265735A - Data decoding device and method therefor and data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect error information on a disk accessing with a high speed to the disk in a data decoding device and method therefor. SOLUTION: When encoded data S1 recorded in a recording medium 2 are read and decoded, decoded data S2 are corresponded to decoding information ER in frames and are stored in a memory 51, and by reading the decoded data and the decoding information ER from the memory 51 in frame-synchronization with address data of the recording medium 2 corresponding to the decoded data, the decoding information ER of the decoded data corresponding to the address data of the recording medium 2.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD The invention belongs to the related art (FIG. 39) Problems to be solved by the invention (FIGS. 40 to 44) Means for solving the problems Embodiments of the invention (1) First embodiment (FIGS. 1 to 1) 7) (1-1) Overall configuration of data reproducing apparatus (FIG. 1) (1-2) ECC circuit and ECC decoding (FIGS. 2 to 7) (1-3) Operation and effect of the first embodiment (2) Second embodiment (FIGS. 8 to 38) (2-1) Recording data format (FIGS. 8 to 11) (2-2) Data reproducing device and ECC decoding (FIGS. 1, 9, and 11 to 38) (2-3) Operations and effects of the second embodiment (FIGS. 29 to 3)
1, FIG. 35 and FIG. 37) (3) Other Embodiments Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding apparatus, a method therefor, and a data reproducing apparatus, and is suitable for use in, for example, reproducing a moving image that has been digitalized and recorded on a disk.

[0003]

2. Description of the Related Art Conventionally, for example, MPEG (Moving Pictures Ex
pert Group) There is a disk in which moving images according to the standard are digitalized and recorded at a variable rate. The MPEG used here is an I-picture (Intra-Picture) that is an intra-frame coded image for image data, and a P-picture (Predictive-Pictur) that is an inter-frame forward prediction coded image.
e), B picture (Bidirect)
Ionally predictive-Picture) is defined as three types, and the screen group structure GOP (Group Of
Pictures)). Similarly, the MPEG standard is applied to audio data, but for audio data other than MPEG, for example, ATRAC (Aditive TRansfor
m Acoustic Coding) for digitalization and compression coding. ATRAC is a trademark.

FIG. 39 shows a data reproducing apparatus 1 for reproducing data recorded on a disk at a variable rate. The data reproducing apparatus 1 irradiates the data recorded on the optical disk 2 with a laser beam by the pickup 3 and reproduces the data from the reflected light. Playback signal S1 output by the pickup 3
Is input to the demodulation circuit 6 of the decoding circuit system 5 controlled by the system controller 4 and demodulated. The data demodulated by the demodulation circuit 6 is input to an ECC (Error Correction Code) circuit 8 via a sector detection circuit 7,
Error detection and error correction are performed.

If the sector number which is the address assigned to the sector of the optical disk 2 is not normally detected in the sector detection circuit 7, a sector number abnormality signal is output to the track jump determination circuit 9. ECC
The circuit 8 outputs an error occurrence signal to the track jump determination circuit 9 when uncorrectable data is generated. The error-corrected data is sent from the ECC circuit 8 to the ring buffer memory 10 and recorded.

At this time, the ring buffer control circuit 11
The address of each sector is read from the output of the sector detection circuit 7, and the write address on the ring buffer memory 10 corresponding to the address (hereinafter, write pointer WP
Is specified). In addition, the ring buffer control circuit 11 controlled by the system controller 4 reads out the address of the data written in the ring buffer memory 10 (hereinafter, referred to as "the read buffer address") based on the code request signal R10 from the multiplexed data separation circuit 13 in the subsequent stage. A read pointer RP) is designated, data is read from the read pointer RP and supplied to the multiplexed data separation circuit 13.

The header separation circuit 14 of the multiplexed data separation circuit 13 separates the pack header and the packet header from the data supplied from the ring buffer memory 10 and supplies the separated data to the separation circuit control circuit 15. The separation circuit control circuit 15 sequentially switches and connects the input terminal G and the output terminals (switched terminals) H1 and H2 of the switching circuit 16 in accordance with the stream ID (Stream IDentifier) information of the packet header supplied from the header separation circuit 11. By doing so, the time-division multiplexed data is correctly separated and supplied to the corresponding code buffer.

Here, the video code buffer 17 is a multiplexed data demultiplexing circuit 1 depending on the remaining amount of the code buffer inside.
A code request R1 is generated for 3. Then, the received data is stored. Also, the video decoder 18
It receives the code request R1 from and outputs the internal data. The video decoder 18 reproduces a video signal from the supplied data and outputs it from the output terminal OUT1.

The audio code buffer 19 depends on the remaining amount of the code buffer inside the multiplexed data separation circuit 13.
A code request R2 is generated. Then, the received data is stored. Also, the audio decoder 2
The code request R2 from 0 is accepted, and the internal data is output. The audio decoder 20 reproduces an audio signal from the supplied data and outputs it from the output terminal OUT2.

As described above, the video decoder 18 requests data from the video code buffer 17, and the video code buffer 17 sends a request to the multiplexed data separation circuit 13,
The multiplexed data separation circuit 13 is a ring buffer control circuit 1.
Make a request to 1. At this time, data flows from the ring buffer memory 10 this time in the opposite direction to the request.

[0011]

Data decoding in the demodulation circuit system 5 will now be described. First, the disk 2
The reproduction signal S1 read from the
It is converted into a binary signal by processing and EFM + (8,16 conversion)
Sync pattern is detected. Based on the synchronization pattern detected from the reproduction signal S1, the reproduction signal has a constant linear velocity.
(Constant Liner Velosity, CLV) method rough servo can be applied. When the sector detection circuit 7 detects a sync header with EFM + as an interface of the system controller 4, a PLL (Phase Locked Loop) servo is applied. After that, when the sync header is detected several times in succession, the EFM + demodulated data S2 is deinterleaved (hereinafter referred to as deinterleave).

As shown in FIG. 40, the EFM + demodulated data S2 sent to the ECC circuit 8 is first temporarily stored in the RAM 24 and then, in the ECC decoders 25, 27 and 29, the C1 / C2 convolution / Reed-Solomon code ( CIRC Pl
us) to decode ECC of 3 sequences C11 (first C1 sequence), C2 and C12 (second C1 sequence).

For ECC decoding in the ECC circuit 8, for example, as shown in FIG. 41, the data S2 after EFM + demodulation is written in the RAM 24 in the order of 00, 01, ..., A8, A9, and (EFM + Writ
e), when two frames of EFM + demodulated data are stored in the RAM 24, 00 ', 02', ~ A8 'of frame 1
ECC of deinterleaved C1 sequence data by transferring data to the ECC decoder 25 in the order 01, 03, ... A9
Perform decryption. Here, in the error correction, the error position and the correction pattern are read from the ECC decoder 25, the erroneous data is read from the RAM (Random Access Memory) 24 (C1 read), and the exclusive OR with the correction pattern is taken. , RA again, as shown in FIG.
Execute by writing back to M26 (C1 Write). Here, the ECC decoding of the C1 sequence is performed by the ECC decoder 25.
Only two code sequence lengths are executed.

When the C1 sequence ECC decoding is executed for the C2 code sequence length, the C2 sequence ECC decoding can be executed. Next, the data on the RAM 26 is 00 ', 01', 02 ', 0
3 ', ~ A9' are read in this order (C2 read), ECC
The decoder 27 executes C2 sequence ECC decoding. Here, the erasure correction can be performed by transferring the uncorrectable flag for each frame to the ECC decoder in the subsequent stage in synchronization with the data. For erasure correction of the C2 series, the uncorrectable flag of C1 is used. The error correction operation is similar to that of C1. As shown in FIG. 43, when the C2 sequence ECC decoding result is written to the RAM 28 (C2 Write) and the C2 sequence ECC decoding is executed for the C1 code sequence length, the C12 sequence ECC decoding becomes feasible and the ECC decoder According to 29, 00 ', 01, 02, 03,
~ A9 are read in this order (C12 read)
ECC decoding is performed.

Here, for erasure correction of the C12 series, the uncorrectable flag of C2 is used. And C1
When the error correction of No. 2 is completed, as shown in FIG.
ECC of C12 series in the order of 00, 01, 02, 03, to A9 in M30
The decryption result is written. In this way, the RAM 30 has EC
The decoded data of each sequence C11, C2, and C12 of C is stored and read out in the order of 00, 01, 02, 03, to A9 (O
UT read), descramble processing is performed, and the data is sent to the ring buffer memory 10, whereby necessary sector data is written.

By the way, the number of errors generated in the ECC circuit 8 varies depending on the precision of cutting the disk. Therefore, by utilizing this fact, the number of errors generated in the ECC circuit 8 can be measured to evaluate the disk after manufacturing. In this case, by using the sector address as a parameter to know the disk position,
The position where the error occurred can be detected.

Here, when ECC is convolutionally coded with C1 and C2 sequences, ECC decoding is C1-C2-C.
Iterative error correction is executed in each ECC decoding sequence as in 1. That is, in the convolutional code, for example, C
The ECC decoding of the C2 series is executed after the ECC decoding of the 1 series is executed. Similarly, after executing the C2 and C1 sequences, 2
Execute the ECC decoding of the C1 sequence for the second time. Therefore, if the result is output immediately after executing ECC decoding, the same C
There will be a time difference in the detection timing of the ECC result for one sequence.

Therefore, when the ECC result is made to correspond to the position on the disk, the system controller 4 first records the sector address detected by the sector detection circuit 7 and simultaneously takes in the ECC result. Then, the time lag between the sector address and the ECC result must be calculated and the ECC result for the sector address must be analyzed.
There was a problem that the calculation became complicated.

Since the amount of data supplied to the ECC circuit 8 per unit time increases or decreases in accordance with the disk rotation speed, the execution control timing of the ECC may be changed accordingly. Therefore, when accessing the disk at a high speed, for example, when only the C1 series is executed with priority, if the error result is output immediately after the ECC is executed, the error result of each C11, C2, and C12 series will be recorded on the disk. There is a problem that it is difficult to judge whether the error result corresponds to the sector address. The present invention has been made in consideration of the above points, and proposes a data decoding apparatus and method and a data reproducing apparatus capable of easily detecting an error position of a disk while accessing the disk at high speed. Is.

[0020]

In order to solve such a problem, according to the present invention, in a data decoding device for reading and decoding encoded data recorded on a recording medium, a decoding circuit for decoding the encoded data, and a recording device A memory for storing the encoded data read from the medium, the decoded data and the decoding information output from the decoding circuit, and the decoding data and the decoding information are stored in the memory by associating the decoding information with the decoding information in frame units. Memory control means for reading the information from the memory in frame synchronization with the address data of the recording medium corresponding to the decoded data.

Further, in the present invention, in the data decoding method for reading and decoding the coded data recorded on the recording medium, when decoding the coded data, the decoded data and the decoding information are associated with each other in a frame unit and stored in the memory. The decoded data and the decoded information are stored and read in frame synchronization with the address data of the recording medium corresponding to the decoded data.

Thus, when decoding the encoded data read from the recording medium, the decoding information of the decoded data corresponding to the address data of the recording medium can be read, and thus the decoding information corresponding to the address data of the recording medium can be read. The state of the recording medium can be easily analyzed.

Further, in the present invention, in a data reproducing apparatus for reading coded data recorded on a recording medium, decoding and reproducing and outputting the coded data, a decoding circuit for decoding the coded data and the coded data read from the recording medium. In addition, the memory for storing the decoded data and the decoding information output from the decoding circuit, the decoding information is associated with the decoding information on a frame-by-frame basis and stored in the memory, and the decoding data and the decoding information are associated with the decoding data. And a memory control unit for reading from the memory in frame synchronization with the address data of the recording medium.

Thus, in the data reproducing apparatus, when the encoded data is read from the recording medium and decoded, the decoding information of the decoded data corresponding to the address data of the recording medium can be read out, and thus the address data of the recording medium can be read. It is possible to realize a disk reproducing device that can easily analyze the state of the recording medium from the corresponding decryption information.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment (1-1) Overall Structure of Data Reproducing Device 4 in FIG. 1 in which parts corresponding to those in FIG.
Reference numeral 0 indicates a data reproducing device using the data decoding device according to the present invention. The data reproducing device 40 reproduces the image and audio data recorded at a variable rate from the optical disc 2. The disk reproducing device 40 irradiates the optical disk 2 with a laser beam, reads the recorded data from the reflected light by the pickup 3, and reproduces it. Reproduction signal S1 reproduced by the pickup 3
Is sent to the demodulation circuit 6 of the demodulation circuit system 35 controlled by the system controller 4. The reproduction signal S1 is demodulated by the demodulation circuit 6 and sent to the sector detection circuit 7.

The sector detection circuit 7 detects the address recorded in each sector from the supplied data and outputs it to the ring buffer control circuit 11, and at the same time, the EC in the subsequent stage.
The data is output to the C circuit 50 in a state in which the sector is synchronized. The ring buffer control circuit 11 controlled by the system controller 4 controls writing and reading of the ring buffer memory 9 and monitors a code request signal R10 requesting data output from the multiplexed data separation circuit 13. . Here, the sector detection circuit 7
Outputs the sector number abnormality signal to the track jump determination circuit 9 via the ring buffer control circuit 11 when the address cannot be detected or the detected addresses are not continuous.

The ECC circuit 50 detects an error in the data supplied from the sector detection circuit 7, performs error correction using the redundant bit added to the data, and outputs the FIFO (Fir)
It is output to the ring buffer memory 10 for the track jump having the st in first out) function. The data in the ring buffer memory 10 is supplied to the multiplexed data separation circuit 13. At this time, the ECC circuit 50 detects the sector header data and sends it to the system controller 4 through the sector detection circuit 7. Here, if the ECC circuit 50 cannot correct the data error, it outputs the error generation signal E10 to the system controller 4.

The track jump judgment circuit 9 monitors the output of the ring buffer control circuit 11 and outputs a track jump signal JP1 to the tracking servo circuit 22 when a track jump is necessary to determine the reproduction position of the pick up 3 with respect to the optical disk 2. It's designed to trigger truck jumps. Here, the system controller 4 sends the sector number abnormality signal from the sector detection circuit 7 or the ECC.
When the error occurrence signal from the circuit 50 is detected, the track jump determination circuit 9 outputs the track jump signal to the tracking servo circuit 22 to track the reproduction position of the pick-up 3.

The header separation circuit 14 to the multiplexed data separation circuit 13 separates the packet header and the packet header from the data supplied from the ring buffer memory 9 and supplies them to the separation circuit control circuit 15 and time-division multiplexed. Data is supplied to the input terminal G of the switching circuit 16. Output terminal of switching circuit 16 (switched terminal)
H1 and H2 are connected to the input terminals of the video code buffer 17 and the audio code buffer 19, respectively. Here, the output terminal is set to H by the switching circuit 16.
When switched to 1, the video code output is sent to the video decoder 18 through the video code buffer 17 and output from the output terminal OUT1. When the output terminal is switched to H2 by the switching circuit 16, the audio code output is sent to the audio decoder 20 through the audio code buffer 19 and output from the output terminal OUT2.

The code request signal 21 generated by the video decoder 18 is input to the video code buffer 17, and the code request signal R2 generated by the video code buffer 17 is input to the multiplexed data separation circuit 13. Similarly, the code request signal R2 generated by the audio decoder 20 is the audio code buffer 1
9, the code request signal R2 generated by the audio code buffer 19 is sent to the multiplexed data separation circuit 1
3 has been entered.

By the way, if the data consumption per unit time of the video decoder 18 decreases, for example, if the data processing relating to a simple screen continues, the ring buffer memory 1
Reads from 0 are also reduced. In this case, the amount of data stored in the ring buffer memory 10 increases and there is a risk of overflow. Therefore, the track jump determination circuit 9 calculates the amount of data currently stored in the ring buffer memory 10 by the write pointer WP and the read pointer RP, and when the data exceeds a predetermined reference value set in advance. , It is judged that the ring buffer memory 10 may overflow,
A tracking jump command is output to the tracking servo circuit 22.

In addition, the track jump determination circuit 9 uses the sector number abnormal signal or ECC from the sector detection circuit 7.
When the error occurrence signal from the circuit 7 is detected, the amount of data remaining in the ring buffer memory 10 is obtained from the write pointer WP and the read pointer RP, and the optical disk 2 makes one revolution from the current track position. The amount of data required to guarantee the reading of the multiplexed data separation circuit 13 from the ring buffer memory 10 is calculated (while waiting for one rotation of the optical disk 2). Here, when the amount of remaining data in the ring buffer memory 10 is large, underflow does not occur in the ring buffer memory 10 even if data is read from the ring buffer memory 10 at the highest transfer rate. Therefore, the track jump judgment circuit 8 judges that the error recovery is possible by reproducing the error occurrence position again by the pick-up 3, and outputs the track jump command to the tracking servo circuit 22.

When the track jump command is output from the track jump determination circuit 9, the tracking servo circuit 22 jumps the reproduction position by the pick-up 3. Then, in the ring buffer control circuit 11, the reproduction position of the optical disk 2 makes one rotation and the sector detection circuit 7
Writing of new data to the ring buffer memory 10 is prohibited until the sector number obtained from the above becomes the sector number at the time of track jump, and the data already stored in the ring buffer memory 10 is multiplexed if necessary. The data is transferred to the encoded data separation circuit 13.

After the track jump, even if the sector number obtained from the sector detection circuit 7 matches the sector number at the time of track jump, the amount of data stored in the ring buffer memory 10 exceeds a predetermined reference value. The writing of data to the ring buffer memory 10 is not restarted, and the track jump is executed again.

(1-2) ECC Circuit and ECC Decoding The ECC circuit 50 shown in FIG. 2 decodes ECC by C1 / C2 convolutional / Reed-Solomon code (CIRC +). EC
The C circuit 50 includes a RAM 51, which is a ring buffer, and an EF.
ECC by performing error correction on M + demodulated data
An ECC decoder 52 for decoding and an error register 53 for storing an error correction impossible flag, an error correction pattern and an error position are formed.

The actual ECC decoding will be described using the ECC circuit 50 and its peripheral circuits shown in FIGS. 2 and 3. In the ECC decoding, the reproduction signal S1 is first processed by the RF processing circuit 42.
After RF processing and binarization processing at EFM + at demodulation circuit 6.
Detect the synchronization pattern of. When the EFM synchronization pattern is detected, the CLV control circuit 46 applies rough servo. Subsequently, when the demodulation circuit 6 detects an EFM + sync pattern, PLL (Phase Locked Loop) servo is applied. After that, when the sync pattern is detected several times in succession, the data S2 after EFM demodulation is deinterleaved and then RMIF (Random access Memory InterFace)
The data is written in the RAM 51 of the ECC circuit 50 via the frame 48 in frame units. And OCTL (output control circuit) 5
It is output to the ring buffer memory 10 through 6 and stored.

In the ECC circuit 50, the RAM 5 is passed through the RMIF 48 controlled by the system controller 4.
A write address of the decoded data S10 to 1 is generated. Here, the data read from the RAM 51 is RMI.
It is transferred to the ECC control unit 54 and the ECC decoding unit 55 through F48. If an error is detected here and the error can be corrected, the error position and the error correction pattern are transferred from the ECC decoding unit 55 to the ECC control unit 52.
Is output to In this case, the error position and the error correction pattern are output to the RAM 51, which is a frame memory, in frame units and stored in the error register 53 (FIG. 2). For error correction, the error position and the correction pattern are read from the error register 53, the error data corresponding to the error position is read from the RAM 51, the exclusive OR (EXOR OR, EXOR) with the correction pattern SP is taken, and the RAM 51 is read again. It is executed by writing back (Fig. 2). When an uncorrectable error is detected, the uncorrectable flag of the frame is stored in the error register 53 for use in the ECC erasure correction in the subsequent stage.

As a result, the error register 53 stores the ECC for each ECC series C11, C2, and C12.
The error position and the correction pattern are accumulated as data necessary for solving When the error positions and correction patterns SP necessary and sufficient for solving the ECC are aligned, error correction is executed with the data S2 stored in the RAM 51 (FIG. 2).

As a result, the decoded data S10 and the sector header data SH are separated from the ECC circuit 50 for which the ECC decoding is completed, and the ring buffer memory 1
0 and sent to the sector detection circuit 6. Further, the sector header data SH is sent to the ring buffer control circuit 11 through the sector detection circuit 6. Here, the ring buffer control circuit 11 writes the decoded data S10 sent from the ECC circuit 50 on the basis of the sector header data SH in the ring buffer memory 10.

Here, the data storage address (memory address RA) is determined by the RMIF 48 as shown in FIG.
The data order Dn in the C1 direction based on the data address of AM51 and the frame output number Fn in the C1 code unit

[Equation 1]

[Equation 2]

(Equation 3)

(Equation 4) It can be calculated by

In the RAM 51, the RMIF 48 displays the results of the three ECC decoding sequences C11, C2, and C12 in the A of the frame including the head data of the sequence.
Write to any of A, AB, AC, AD, AE, and AFth addresses. Here, for example, the ECC result is AA, A
When writing to B and AC, three series C11 and C of ECC decoding are performed by frame number Fn and data order AA, AB and AC.
The memory address RA of the RAM 51 for the results of 2 and C12 can be easily generated.

As shown in FIG. 5, 8-bit data is used as the ECC result ER. For example ECC result ER
The output of BIT is 0, 1, 2 and 3 with ECC
The number of corrections, the presence or absence of an error in bit 4, the ECC result of the C12 series in bit 5, the information indicating whether this ECC result belongs to the C1 series or the C2 series in bit 6, and the uncorrectable information in bit 7 are set. . Thus ECC result ER
By setting, it is possible to monitor the number of ECC corrections at the same time in addition to the error presence.

FIGS. 6A and 6B show examples of the output timing of the ECC result ER. After performing ECC decoding, the three series C11, C2 and C1 together with the sector address data
The result of 2 ECC decoding is output in frame units. RAM
User data DAT, sector address data ADD, and ECC result ER read from 51 through RMIF 48
Are output from the bus 60 through the OCTL 56. At this time, strobe signal (AST
(B, DSTB, ESTB) is added to determine the content of the data. Here, FIG. 6B is an enlarged view of one frame period of FIG. 6A.

In the disk reproducing device 40, since it is necessary to secure a data amount from the ring buffer memory 10 to guarantee the reading to the multiplexed data separation circuit 13, the RFCK is used for recording (cutting) the disk. It is set so that the channel bit rate during playback is higher than the reference channel bit rate of 26.6 (Mbit / s).

When the ECC decoding by the ECC circuit 50 is completed, the OCTL 56 first normalizes the ECC decoding of the error strobe signal ESTB which gives the output timing of the ECC result ER which is the error information of the encoded data recorded on the optical disk 2. Output for executed frames. For example, as shown in FIG. 6B, after a track jump, for a frame in which only C11 can be executed due to a difference in interleave length, data is output with ESTB = 1 corresponding to the ECC result ER of C11.

Next, the address strobe signal ASTB which gives the output timing of the sector address ADD is output. Here, by capturing the address strobe signal ASTB = 1 minute data, the optical disk 2 corresponding to the read frame is read.
You can check the position above. Since the sector address ADD exists at the beginning of the data block which becomes one sector in several frames, the address strobe signal ASTB is the sector address.
ASTB = 1 only for the frame including ADD (FIG. 6 (A)). The subsequently output data strobe signal DSTB is a strobe signal for the user data DAT (FIG. 6 (B)). FIG. 7 shows an example of the sector format of the data output from the bus 60. Error result E
After sending 3 bytes of R, data sync SYNC, header HEAD
ER and user data USER DATA are output for each frame.

In this way, the user data DAT decoded by the RMIF 48 and the series of the user data DAT
Since the ECC result ER is frame-synchronized with the data of the sector address ADD and is read from the RAM 51 as the output data S10, the ECC result ER corresponding to the sector address ADD of the optical disk 2 can be easily detected.
Thus, analysis of ECC error for disk reproduction can be easily performed.

(1-3) Operation and Effect of First Embodiment In the above-mentioned configuration, the data of the optical disk 2 mounted on the disk reproducing device 40 is read by the pick-up 3 and by the demodulation circuit 6. With EFM + demodulation,
After the sector header of the data is read by the sector detection circuit 7, the EFM + demodulated data S2 is sent to the ECC circuit 50.

The ECC circuit 50 deinterleaves the EFM + demodulated data S2 and temporarily stores it in the RAM 51, and then E
The CC decoder 52 executes ECC decoding of three sequences of C11, C2 and C12 (FIG. 2). RMIF here
The RAM 48 stores the ECC result ER obtained as a result of ECC decoding in the RAM.
On 51, 3 sequences of ECC decoding C11, C2 and C
The 12 ECC results are written in, for example, AA, AB, AC of the frame including the head data of the series. By this, the frame number Fn and the data order AA, AB, AC
The memory address RA of the RAM 51 for the results of the three ECC decoding sequences C11, C2, and C12 can be easily generated.

The data thus stored in the RAM 51 is transferred from the OCTL 56 to the bus 6 by the RMIF 48.
It is output to the ring buffer memory 7 through 0. 6A and 6B show the output timing of the ECC result. That is, after the ECC decoding is executed, the result of the ECC decoding of the three sequences C11, C2 and C12 is output in frame units together with the sector address data of the optical disk 2 in which the encoded data is recorded. That is, when the ECC decoding is completed, the OCTL circuit 56 first outputs the error strobe signal ESTB which gives the output timing of the ECC result ER to the frame in which the ECC decoding is normally executed.

Next, the address strobe signal ASTB which gives the output timing of the sector address of the optical disk 2 is output. The position of the disk corresponding to the read frame can be confirmed by taking in the data for the address strobe signal ASTB = 1. Then, the data strobe signal DS, which is the strobe signal for the user data.
Output TB. As a result, sector format data as shown in FIG. 7 is output in frame units. As a result, when the sector address ADD of the optical disk 2 corresponding to the ECC result ER is read, the ECC result ER which is the error information of the decoded data read from the optical disk 2 can be easily obtained, and the ECC error corresponding to the decoded data Analysis can be done easily.

According to the above configuration, when the ECC decoding is executed in the ECC circuit 50, the RMIF 48 causes the RA
3 sequences of ECC decoding C11, C2 and C12 on M51
The ECC result is written in the frame including the first data of the series, and the frame number Fn and the data order AA, AB,
The AC can easily generate the memory address RA of the RAM 51 for the ECC result ER of each of the three ECC decoding sequences C11, C2, and C12. In this way, after the ECC decoding, the output user data DAT and the ECC result ER corresponding to the user data DAT are frame-synchronized and output together with the data of the sector address ADD of the optical disk 2. , The ECC result ER corresponding to the sector address ADD of the optical disk 2 can be easily detected. Thus, even when accessing the disk at high speed, the ECC error can be analyzed almost at the same time as the reproduction of the main data.

(2) Second Embodiment (2-1) Recording Data Format FIGS. 8 to 11 show recording data formats in the second embodiment. In this embodiment, one cluster (32
Data is recorded in units of (k bytes).
The configuration of this cluster will be described in detail below.

That is, 2 kbytes (2060 bytes)
Data is extracted as data for one sector, and a 4-byte overhead is added to this data as shown in FIG. This overhead includes an error detection code (EDC) for error detection.

This total of 2064 (= 2060 + 4) bytes worth of data for one sector is 12 × as shown in FIG.
The data is 172 (= 2064) bytes. Then, 16 pieces of data for one sector are collected, and 192
(= 12 × 16) × 172 bytes of data. A 16-byte outer code (PO) is added to this 192 × 172-byte data as a parity for each byte in the vertical (column) direction. Also, 208 (= 192 + 1)
6) For x172 bytes of data and PO parity,
An inner code (PI) of 10 bytes is added as a parity for each byte in the horizontal (row) direction.

Further, in this way, 208 (= 192
In the block data of +16) × 182 (= 172 + 10) bytes, the row of the outer code (PO) of 16 × 182 bytes is divided into 16 rows of 1 × 182 bytes, as shown in FIG. , 16 rows of 12 × 182 bytes of sector data of numbers 0 to 15 are inserted line by line and interleaved. And 13 (= 1
Data of (2 + 1) × 182 bytes is data of one sector.

Further, the 208 × 182-byte data shown in FIG. 10 is vertically divided into two, as shown in FIG. 11, and one frame is made up of 91-byte data.
The data is 8 × 2 frames of data. At the beginning of the 91-byte frame data, a 2-byte frame synchronization signal (FS) is further added. As a result, as shown in FIG. 11, one frame of data becomes a total of 93 bytes of data, and a total of 208 × (93 × 2) bytes of block data. This becomes data for one cluster (1ECC block). The size of the actual data part excluding the overhead part is 2 kbytes (= 2048 × 16/102
4 kbytes).

That is, in this example, one cluster (1
The ECC block) is composed of 16 sectors, and one sector is composed of 24 frames. Such data is recorded on the optical disk 2 in cluster units.

(2-2) Data Reproducing Device and ECC Decoding Here, FIG. 12 shows a demodulation circuit system in the case of applying the recording data format of the second embodiment to the data reproducing device 40 described in the first embodiment. 35, the demodulation circuit 6 (R
F processing circuit 130, EFM + demodulation circuit 131, sector detection circuit 7 (SBCD circuit 134, RAM controller 135, RAM 137), and ECC circuit 50 (RA
M controller 135, ECC control circuit 136, RAM
137, ECC core circuit 138, OCTL circuit 13
9) and a detailed configuration of circuits around it.

In this figure, the RF processing circuit 130 is
The RF signal input from the pickup 3 shown in FIG. 1 is received, the signal is binarized, and then the EFM + demodulation circuit 131
Output to The EFM + demodulation circuit 131 performs EFM + demodulation on the input signal and detects a synchronization pattern. The CLV control circuit 132, based on the synchronization pattern output from the EFM + demodulation circuit 131, drives interface (hereinafter abbreviated as drive IF) 133.
Control. The SBCD (subcode) circuit 134 is an EF
The sector is detected from the output of the M + demodulation circuit 131. R
The AM controller 135 corresponds to the RMIF 48 of FIG. 3 and controls the reading and writing of the RAM 137.

The RAM 137 is adapted to temporarily store data and the like when the ECC control circuit 136 executes error correction processing and the like. ECC core circuit 138
Corresponds to the ECC decoding unit 55 in FIG. 3, and uses Reed-Solomon codes (PI and PO) to perform ECA, ECD,
The SGLG or the like is generated and output to the ECC control circuit 136. The ECC control circuit 136 uses ECA, ECD, SFLG, etc. supplied from the ECC core circuit 138,
Actually correct the error. The OCTL circuit 139 performs descramble processing, EDC check, control of output data, and the like. The host CPU 140 corresponds to the system controller 4 of FIG. 1 and is adapted to control each part of the apparatus.

The reproduced signal from the optical disk 2 (FIG. 1) is
It is converted into a binarized signal in the RF processing circuit 130.
Then, from the binarized signal, the EFM + demodulation circuit 13
1, the sync pattern is detected. Then, in the CLV control circuit 132, rough servo is applied on the basis of this synchronization pattern, and as a result, a sync code (Sync Code) (SY0 to SY7 in FIG. 16) in the data is further detected and is passed through the drive interface 133. The PLL (Phase Locked
Loop) phase servo is applied.

FIG. 13 shows a configuration example of the physical sector of the optical disk 2. As shown in this figure, the physical sector consists of two Sync frames in the horizontal direction and one in the vertical direction.
It is composed of three sync frames, which is a total of 26 sync frames. Each sync frame has a sync code (SY0 to SY0) of 32 channels (16 bits (= 2 bytes when expressed in data bits before modulation)).
SY7) and a 1456 channel bit (expressed as a data bit before modulation, 728 bits (= 91 bytes)). In the data portion of the first sync frame, ID information (sector number) and IED
In addition to the (error detection code for ID) information, main data is stored.

The 32 channel bit sync pattern is a unique pattern that does not appear in the data.
The lower 22 bits are "000000000000"
It is set as "000010001".

Main data is recorded in the data portion of each sync frame on the left side of FIG. 13, and PO information (parity) is recorded in the data portion of the last sync frame on the left side. Main data and PI information are recorded in the sync frame on the right side of FIG. 13, EDC information and PI information (parity) are recorded in the second to last sync frame of the right sync frame, and the last sync frame is recorded. In this area, PO information and PI information are recorded.

FIG. 14 shows details of data excluding PI information and PO information of each sector. ID (sector number) (4 bytes), IED (error detection code for ID (2 bytes)), RSV (reserved area) (6 bytes), main data, and EDC (4 bytes) make up one sector of data. The main data has been subjected to scramble processing.

Then, 16 such data sectors are collected, and as shown in FIG.
A code and a 10-byte PI code are added. further,
16 rows including the PO code are interleaved so as to be arranged for each data sector. Then, as shown in FIG. 11, the obtained data is sync code SYx (x =
FS (frame synchronization) code represented by 0, 1, 2, ..., 7) is added and EFM + modulated. As a result, the physical sector in the ECC block is composed of 13 × 2 sync frames as shown in FIG.
Since 1 ECC block consists of 16 sectors,
The lower 4 bits of the physical sector address are 0000 to 111
It will be one of 1. As a result, the lower 4 bits of the physical address of the first sector of the ECC block is 0000.

In the scrambling process for the main data, an exclusive OR is calculated between the main data and the scramble data generated by using the lower 4 bits to 7 bits of the physical sector address as an initial value. It is executed by

Since various symbols are used for various signals in this specification, they will be collectively described here.

Block-top (Block Top) A signal which becomes H from the head of the sector when the SYLK signal is H. C11M (Clock 11.2896 MHz) This is the operating clock of the system, and its frequency is 11.2.
896 [MHz]. DSTB (Data strobe) This is a data strobe signal which becomes H when main data is output as the stream data SD. ECA (ERR Correction Address) An error correction address signal indicating a position (address) having an error. ECCK (ECC Clock) This is an operation clock of the ECC core circuit 138. ECD (Error Correction Data) ECD (Error Correction Data) is error correction data that becomes correct data when an exclusive OR is calculated with erroneous data. ECCE (ECC Code Data End) This is a controller signal indicating the end of input data. ECOD (ECC Code ERR) This signal is H when an error cannot be corrected. ECOR (ECC Correction) This is a strobe signal indicating the output of error-correctable data (ECA, ECD). ECYE (ECC Cycle End) This is a controller signal indicating the end of the cycle of input code data. EDT (ECC Data) Read from the RAM 137 for error correction, ECC
This is the data transferred to the control circuit 36. ESTB (Error Strobe) This is an error correction result strobe signal which becomes H when the error correction result ER is transferred. ESTT (ECC Start) This is a controller signal indicating the beginning of input data. EFM + W Frame (EFM + Write Frame Counte
r) A signal representing the main frame to be written in the RAM 137. HDEN (Header Data Enable) This is a strobe signal for sector header data. main-FMSY (main Frame Sync) This signal is H at the main sync (head sync) of each PI row. MWEN (Memory Write Enable) EFM + is a write enable signal to the RAM 137 for demodulated data. MWRQ (EFM Write Request) This is a write request signal of the EFM + demodulated data to the RAM 137. OUTE (Output Flag) This is an interpolation flag (output flag). OSTT (ECC Output Start) From ESTT in a predetermined code sequence to 477 (ECC
K) is a signal output after being delayed. RDT (Read Data) Data on the read data bus of the RAM 137. SALK (Sector Address Lock) This signal indicates that the sector address (ID) is normally detected. SAUL (Sector Address Unlock) This signal has the opposite polarity of the SALK signal. SCSY (Sector Sync) This signal is H for Frame of SY0 and is for determining the beginning of a sector. SD (Stream Data) This is stream data (decoded output data). SDCK (Stream Data Clock) This is a clock of stream data. SFLG (Sector Flag) This is an ECC uncorrectable flag for PI1 correction. SINF (Sector Information) This is a sector information strobe signal which becomes H at the head of a sector. SUB (SUB Data) is data including an ID and an IED transferred to the SBCD circuit 134. SYLK (Sync Lock) This signal becomes H when the sync code is detected three times in succession. SYUL (Sync Unlock) This signal has the opposite polarity of the SYLK signal. WDT (Write Data) Data on the write data bus of the RAM 137. XHWE (Sector Header Write Enable) This is an output enable signal of sector information written from the SBCD circuit 134 to the RAM 137.

The data demodulated by the EFM + demodulation circuit 131 (FIG. 12) is stored in the RAM controller 13.
Under the control of No. 5, it is stored in the RAM 137 as shown in FIG. This FIG. 15 shows about one ECC block. When reading the data stored in the RAM 137, the RAM controller 35 can acquire desired data by designating the values of the row and column shown in FIG. That is, in FIG.
The data x in the Nth byte of the row is binary (M, N)
Can be read from the RAM 137.

When the head of the data sector recorded on the optical disk 2 is recognized by the SBCD circuit 134 based on the type and continuity of the sync code, the EFM is performed.
The data demodulated by the + demodulation circuit 131 is stored in the RAM 137 in order from the top data. FIG. 16 shows the timing of the signals of the main part of the circuit concerned at this time.

That is, the EFM + demodulation circuit 131 detects the lock state of the sync, as shown in FIG. First, in step SP1, it is determined whether or not the sync code (SY0 to SY7) shown in FIG. 13 can be detected in each sync frame. If the sync code can be detected, step S
In step P2, the variable SC _lock is incremented by 1, and the variable SC _{unlock is set} to 0. The variable SC _lock represents the number of times when the sync code is continuously detected, and the variable SC _unlock represents the number of times when the sync is not continuously detected.

Next, in step SP3, the variable SC
_It is determined whether _lock is equal to 3. That is, it is determined whether the sync has been detected three times in succession. Variable SC
_{If lock} is smaller than 3, the process returns to step SP1 to repeat the subsequent processing. Step S
If it is determined in P3 that the variable SC _lock is equal to 3, it is determined that the _lock state has been reached, and step SP4 is entered.
At, the SYLK signal is set to H. Then, in step SP5, in order to determine whether or not the sync is detected three times in succession, the variable SC _lock is set to 2, the process returns to step SP1, and the subsequent processes are repeatedly executed.

On the other hand, in step SP1,
If it is determined that the sync code has not been detected, the process proceeds to step SP6, where the variable SC _unlock is incremented by 1 and the variable SC _lock is set to 0. In step SP7, it is determined whether the variable SC _unlock is equal to 3. That is, it is determined whether or not the sync code has not been detected three times in a row. If the number of consecutive failures is 2 or less, step S
The process returns to P1 and the subsequent processes are repeatedly executed. If the sync is not detected three times in succession, the process proceeds to step SP8 and the SYLK signal is set to L. Then, in step SP9, the variable SC _unlock is set to 2 so that the SYLK signal can be kept set to L when the sync code is not detected even at the next sync code generation timing. Then, the variable SC _unlock is set to 2, and the process returns to step SP1.

As described above, the EFM + demodulation circuit 13
1 detects the sync code and constantly monitors whether it is in the locked state.

In the above embodiment, the number of times of detection is three, but the number of consecutive detection times N, which is a reference, is N.
_LOCK and the discontinuity detection count N _UNLOCK can be set to arbitrary values.

As described above, the EFM + demodulation circuit 131
When the YLK signal becomes H, that is, when it becomes a lock state, the processing shown in the flow chart of FIG. 18 is executed. That is, in step SP21, it is determined whether or not the sync code SY0 arranged at the head of each sector is detected. When the sync code SY0 is detected, the process proceeds to step SP22, and the SCSY signal indicating the beginning of the sector is set to H for a predetermined time. Next, in step SP23, it is determined whether or not the SYLK signal has changed to L. If it is not L (if it is still H), the process returns to step SP21 to repeat the same processing. In step SP21, the sync code S
When it is determined that Y0 is not detected,
The processing of step SP22 is skipped.

As described above, the EFM + demodulation circuit 13
1 is S shown in FIG. 16A at the head of each sector.
Generate the CSY signal.

Further, the EFM + demodulation circuit 131 is
When the LK signal becomes H, the processing shown in the flow chart of FIG. 19 is executed. First, in step SP31, the sync code of the main frame (hereinafter, the two horizontal sync frames in FIG. 13 are collectively referred to as one main frame) (hereinafter, the left side of the sync codes in FIG. 13). It is determined whether or not the sync code shown in (1) is detected as a main frame sync. When the main frame sync is detected, the process proceeds to step SP32, where the EFM + demodulation circuit 131 has m shown in FIG.
Generate the ain-FMSY signal. If it is determined in step SP31 that the main frame sync has not been detected, the processing in step SP32 is skipped.

Next, in step SP33, it is determined whether or not the SYLK signal has changed to L. If it has not changed (if it remains H), the process returns to step SP31.
The subsequent processing is repeatedly executed. SYLK signal is L
When it changes to, the generation process of the main-FMSY signal is stopped.

In this way, the EFM + demodulation circuit 131
Is the main-sync for each cycle of the main frame sync (the cycle of two sync frames in the horizontal direction in FIG. 13).
Generate the FMSY signal.

The RAM controller 135 receives the SCSY signal from the EFM + demodulation circuit 131, as shown in FIG.
6 (D), set the MWEN signal to H and R
The process of writing the data of the currently detected sector to the AM 137 is started. That is, at this time R
As shown in FIG. 16 (E), the AM controller 135 counts the mainframe shown in FIG. 13 with a built-in EFM + W Frame counter (not shown). This count value represents the number in order from the top of the main frame shown in FIG.

The RAM controller 135 is similar to that shown in FIG.
As shown in FIG. 6 (F), the built-in PI1 Frame counter (not shown) manages the number of the mainframe transmitted to the RAM 137.

That is, when the data of the first main frame (main frame numbered 0 (main frame in the uppermost row in FIG. 16) shown in FIG. 13 is written in the RAM 137, the ECC control circuit 136 causes the RAM controller 135 to operate. Under control, it is supplied with data for its mainframe. Then, this data is transferred to the ECC core circuit 138 and an error correction process is executed. That is, a PI1 process is executed. The data after PI1 correction is written back to the RAM 137 again.

The RAM controller 135 uses this PI1
After the correction (first PI correction) is executed, the ID and the IED data (SUB) are read out from the data of the mainframe with the number 0 stored in the RAM 137, and FIG.
At the timing of the SUB signal indicated by the number 0 in (C), the ID and IED data of the main frame of the number 0 are transferred to the SBCD circuit 134 via the data bus. As shown in FIG. 13, since the ID and IED data are arranged only at the head of each sector, this transfer process is executed only in the mainframe with the number 0.
In this way, the SBCD circuit 134 detects the address (ID) of the physical sector.

Then, the leading sector of the ECC block is detected by the lower 4 bits of the address of the detected physical sector.

In FIG. 20, the transfer of the above ID is followed by bl.
FIG. 21 shows a timing chart in the case of detecting the ock-top, and FIG. 21 shows the processing after the detection of the block-top, and the operation of these figures will be described later.

FIG. 22 is a timing chart showing more detailed timing of the above-mentioned ID transfer. FIG. 22 (A)
As shown in FIG.
The HDEN signal indicating the timing of reading the ID and IED data from the RAM 137 is output to the circuit 134. At this time, the SBCD circuit 1 is read from the RAM 137.
For 34, total of 7th bit to 0th bit is 8
As the bit read data RDT (FIG. 22 (C)),
ID data (4 bytes) and IED data (2 bytes)
However, a clock C11 with a frequency of 11.2896 [MHz]
It is transferred in synchronization with M (FIG. 22 (F)). It is supplied from the ECC core circuit 138 to the ECC control circuit 136 that the ID data and the IED data are not in the uncorrectable state (in this case, the SFLG signal becomes H) as a result of PI1 correction. It is represented by the SFLG signal (= 1). When the SBCD circuit 134 is supplied with the ID (sequential address), the SBCD circuit 134 sends the sector information SI corresponding to the ID (sector) to the command from the host CPU 140 (command such as interpolation flag generation mode, start sector, end sector, etc.). ). For example, in the sector of the ID whose output is specified by the host CPU 140,
The bit 5 of the sector information is set to 1, and the bit 4 is set to 0.

FIG. 23 shows the structure of sector information (SI). As shown in the figure, each bit of the sector information has the following information.

Bit 7: Setting of interpolation flag (OUTF) generation mode (1: Interpolation flag generation mode) Bit 6: First sector of ECC block (set to 1 when lower 4 bits of physical sector address is 0)
(1: Start sector) Bit 5: Start sector (1 if the physical sector address matches the start sector address specified by the host CPU 140) (1: Start sector) Bit 4: End sector (physical sector address) Is set to 1 when the end sector address specified by the host CPU 140 matches) (1: end sector) Bit 3: Descrambling initialization address Bit 3
(Seventh bit of physical sector address) Bit 2: Descramble initialization address bit 2
(Sixth bit of physical sector address) Bit 1: Descramble initialization address bit 1
(Fifth bit of physical sector address) Bit 0: Bit 0 of descrambling initialization address
(4th bit of physical sector address)

After the check processing is performed by using the 4-byte ID and the 2-byte IED as described later with reference to FIGS. 24 to 26, the XHWE signal shown in FIG. It is set to L by the control circuit 136. At this time,
The sector information SI is transferred from the SBCD circuit 134 to the RAM 137 as 8-bit write data WDT and written. The sector information for 16 sectors is stored so as to correspond to the upper 16 PI rows, as shown in FIG. Therefore, by designating the number of predetermined PI rows, the corresponding sector information can be obtained.

Next, the ID and IED check processing in the SBCD circuit 134 will be described with reference to the flow charts of FIGS.

The SBCD circuit 134 performs the processing shown in the flow chart of FIG. 24 so that the number of sectors where the IED check result is normal (there is no error in the ID) is N or more (3 in this embodiment). Is determined.

Therefore, in the first step SP41, it is determined whether or not the IED check that has just been taken in is normal. If the IED check is normal, the process proceeds to step SP42, where the variable SA _lock representing the number of sectors with normal ID is incremented by one. Then, the variable SA _{unlock indicating the} number of consecutive sectors having an abnormal ID (ID has an error) is set to 0.

Next, in step SP43, the variable SA
_It is determined whether _lock is equal to 3. Step SP42
When it is determined that the variable SA _lock incremented in step 3 is not equal to 3, the process returns to step SP41 to repeat the subsequent processing. In step SP43,
When it is determined that the variable SA _lock is equal to 3, that is, when the sector having the normal ID is reproduced three times in succession, the process proceeds to step SP44 and the flag IECOK is set to H. In step SP45, the variable SA _lock is set to 2 in order to detect the number of times the next IED check is normal, and step SP41.
And the subsequent processing is repeatedly executed.

When it is determined in step SP41 that the IED check is not normal, the process proceeds to step SP46, where the variable SA _unlock is incremented by 1 and the variable SA _lock is set to 0. Then, in step SP47, it is determined whether or not the variable SA _unlock is equal to 3. If they are not equal, step SP4
The process returns to 1 and the subsequent processes are repeatedly executed.

At step SP47, the variable SA
_{If unlock} is determined to be equal to 3, ie IE
When the sector in which the D check is not normal is detected three times in a row, the process proceeds to step SP48, and the flag IECOK is set to L. Next, in step SP49, when the next IED check is not normal, the variable SA _unlock is set to 2 so that it is possible to continuously detect that the number of consecutive IED checks is three. , Step S
The process returns to P41, and the subsequent processes are repeatedly executed.

As described above, the SBCD circuit 134
Sets the flag IECOK to H when the IED check is normal for three or more consecutive times, and sets the flag IECOK when it is not normal for three or more consecutive times.
Is set to L.

The SBCD circuit 134 further determines the continuity of the ID (address) by the processing shown in FIG.
That is, the ID of each sector in one ECC block
Are specified to be sequentially incremented by one. Therefore, this continuity is determined as follows.

First, in step SP61, ID
(Sector address) is detected. I
If D is detected, step SP62 follows and the I
Store D so that it can be compared with the next ID.
Then, in step SP63, the I detected this time is detected.
It is determined whether D is larger than the ID previously detected and stored in step SP62 by one. If the current ID is one greater than the previous ID, step SP6
In step 4, the variable N _S indicating that correct IDs are continuously detected is incremented by 1. In addition, a variable N _{NS indicating the} number of times the ID is not detected or is not continuous.
Is set to 0.

Then, in step SP65, it is determined whether the variable N _S is equal to 3 or not (3
If the ID which has been incremented by 1 continuously is not detected), the process returns to step SP61 to repeat the subsequent processing. When it is determined that the variable N _S is equal to 3, the process proceeds to step SP66, and the flag AS indicating that the ID is continuously correct is set to H.
Then, in step SP67, when the next ID is detected, the variable N _S is set to 2 so that the correct ID can be detected three times in succession again, and the process returns to step SP61. Repeat the subsequent processing.

When it is determined in step SP61 that the ID has not been detected, or in step SP63 that the ID detected this time has not reached a value larger by 1 than the previously detected ID (judged to be discontinuous). In the case), the process proceeds to step SP68 to determine whether the flag SALK is H or not. This flag SALK is shown in FIG.
As will be described later with reference to, when the IED check is normal for three consecutive times or more and the ID continuity is maintained for three or more times, it is set to H.

At step SP68, the flag SAL is set.
If it is determined that K is set to H, step S
Proceeding to P69, the process of interpolating ID is executed. That is, the ID has not been detected, or the ID
Since it is a case where is not continuous, 1 in the previous ID
Is added to generate an ID, which is used instead of the detected ID. When the flag SALK is set to L, such an interpolation process is not performed and the process of step SP69 is skipped.

Next, in step SP70, the variable N
Increment _NS by 1 and set variable N _S to 0
Set to. Then, in step SP71, it is determined whether or not the variable N _NS is equal to 3. If it is determined that the variable N _NS is not equal to 3, the process returns to step SP61 to repeatedly execute the subsequent processing. On the other hand, if it is determined that N _NS is equal to 3, the process proceeds to step SP72 and the flag AS is set to L. And step SP
In 73, if the next ID is not detected, the variable N _NS is set to 2 and the process returns to step SP61 so that it can be continuously detected that it has not been detected three times in succession. , Repeat the subsequent processing.

As described above, the SBCD circuit 134
Sets the flag AS to H when the continuity of IDs is secured, and sets it to L when the continuity of IDs is not secured.

The SBCD circuit 134 uses the two flags IECK and AS generated as described above to generate the flag SALK.

That is, in step SP81 of FIG. 26, it is determined whether or not the flag IECOK is H, and if it is determined to be H, the process proceeds to step SP82 and whether or not the flag AS is H. To be judged. When it is determined in step SP82 that the flag AS is H, the flow proceeds to step SP83, and the flag ASLK is set to H.
Set to.

On the other hand, if it is determined in step SP81 that the flag IECOK is L, or if it is determined in step SP82 that the flag AS is L, the process proceeds to step SP84 to set the flag SALK. Set to L.

As described above, in the SBCD circuit 34, when the IED check is normal for three consecutive times or more and the ID is continuously incremented by one for three consecutive times or more, the flag SALK is set. Is set to H,
IED check is not normal 3 times or more in a row,
Alternatively, if the IDs are consecutively discontinuous three times or more, the flag SALK is set to L.

The host CPU 140 refers to the above-mentioned ID data together with the state of SALK, and detects the position where the laser beam is currently irradiated (access position on the optical disk 2).

The result of PI1 correction is SA in FIG.
It is also possible to add to the conditions of _lock or SA _unlock . Furthermore, although the number of SA _locks or SA _unlocks is set to 3 times as described above, the host CPU 140
It is also possible to set different values depending on.

When the state of SALK is SALK = L (at this time, SALK = H), SYLK = L
(At this time, SYUL = H), the RAM 37
The writing of the EFM + demodulated data from the EFM + demodulation circuit 31 and the control of the ECC are reset. Thereafter, the unlocked state is released (SAUL =
L) and SYLK = H, the writing of EFM + demodulated data to the RAM 137 is restarted.

The unlock is the host CPU 14
It is also possible to force execution by setting 0. For example,
The ECC control can be reset by putting the host CPU 140 into the unlocked state after executing the jump between tracks.

Further, the cancellation of the unlocked state can be selected to be executed by the host CPU 140 or automatically executed without intervention of the host CPU 140.

When SYLK is in the H state (lock state) and bit 6 of the sector information is 1 (the beginning of the sector), the SBCD circuit 134 causes the SYLK = SYLK =
Block-top is set to H as shown in FIG. 20 until it becomes L (until the lock is removed). blo
When ck-top = L, SCSY and main-
When both FMSY are in the H state (beginning of a sector), the value of EFM + W frame is set to 0 after 12. That is, in this case, EFM + W f
The value of frame repeats a value of 0 to 12 for each mainframe.

On the other hand, if block-top = H, as shown in FIG. 21, EFM + W Frame.
The value of is continuously incremented even when the value becomes 13 or more. As a result, as shown in FIG. 15, the data of each main frame of each ECC block is stored in the RAM1.
It will be sequentially stored at 37 different addresses.

Similarly, EFM + R of demodulated data
Writing to the AM 137 is performed and PI1 correction is performed. And the data of 1 ECC block (2
When the PI1 correction for the 08th row data) is completed, next, the ECC process (PO correction) in the PO column direction is executed.

When reading data in the PO column direction, it is necessary to cancel the interleaving of the PO rows (FIG. 10). Therefore, for example, when reading the Nth byte column shown in FIG. 15, first, after reading the data of the Nth byte column from the top to the bottom of the figure while skipping the interleaved PO rows. , Again, only the code of the PO row in the same column of the Nth byte is read, and the ECC core circuit 1
38.

Then, when the ECC core circuit 138 finishes the PO correction (when the processing of all 172 columns except the PI column (10 columns) at the right end of FIG. 15 is finished), then PI2 correction (PI correction of 2) is performed. Run the second time). The reason why the ECC processing in the PI row direction is performed twice is to improve the error correction capability.

In PO correction, erasure correction is executed according to the error flag (PI1 flag) generated based on the result of PI1 correction. Further, also in PI2 correction, erasure correction is executed using an error flag (PO flag) generated according to the result of PO correction. The reason for performing such erasure correction is to improve the error correction capability as in the case described above.

The PI series data for which the PI2 correction processing has been completed is transferred from the RAM 137 to the OCTL circuit 139, and the descrambling processing for the main data is performed as shown in FIG.
Using bits 3 to 0 of the sector information shown in 3,
It is executed in each sector unit. Also, at this time, OCTL
The circuit 139 performs the EDC calculation. And
Whether or not there is an error in the target sector is determined based on the result of the calculation and the presence / absence of an error flag added to the main data. The host CPU 140 determines whether to read the data from the optical disk 2 again based on the determination result. As a result, when it is determined that the data is read again from the optical disk 2, the optical disk 2
Is accessed again. When it is determined that the data is not read again, the sector data including the error is output to the multiplexed data separation circuit 13 (FIG. 1).

The ECC core circuit 138 is composed of a general-purpose Reed-Solomon code error correction LSI, and has a code length, parity number, and correction mode (normal correction only or normal correction and erasure correction modes).
It is possible to program such as. Also,
The ECC core circuit 138 can also decode multi-code consecutively encoded data (a plurality of code sequences having different code lengths) in real time. As the Reed-Solomon code error correction LSI, for example, Sony
(Trademark) CXD307-111G
Formed by using ASIC (Application Speciali
The zed integrated circuit) is called an ECC core. In addition,
This ECC core is used in the ECC core circuit 138 shown in FIG.

FIG. 27 shows the timing of signals during execution of the error correction operation. In this figure, E
The STT (FIG. 27A) is a code (PI line or PO).
Control signal indicating the start of the
DE (FIG. 27 (B)) is a code (PI line or PO line)
Is a control signal indicating the end of the control signal. ECYE (Fig. 2
7 (C) is a control signal indicating the end of the code (PI row or PO row) cycle. These are all from the RAM controller 135 to the ECC control circuit 13
6 to the ECC core circuit 138. ECC
The core circuit 138 identifies the data supplied from the RAM 137 by these control signals.

As shown in FIG. 27, the PI code is EST.
182 ECCKs are transferred between T and EDCE. The PO code is also transferred by 208 ECCKs from ESTT to ECDE.

When the code lengths of the code of the PI row and the code of the PO column are different, the code cycle length of the code of the PI row or the code of the PO column, whichever has the longer code length (in the case of this embodiment, PO is used). 27), the data to be corrected (EDT) and the error flag (PI1 flag, PI2 flag, PO flag) for erasure correction can be adjusted by any code sequence as shown in FIG. Even if you attach it, you can enter it at the same timing. Further, it is possible to set arbitrary values as parameters such as code length and number of parity. That is, when changing the setting, if new setting data is supplied to the ECC core circuit 138 at the timing when ESTT = H, the ECC
The core circuit 138 automatically changes the internal setting based on the supplied data.

The data correction result is output in a cycle of 477 ECCK as shown by the following equation. throughput = 2 × NCYC + 3 × PCCYC + 13 = 2 × 208 + 3 × 16 + 13 = 477 (ECCK)

Here, NCYC is the code of PI line or P
Indicates the longer code length of the O column code.
YC indicates the longer parity number. As shown in FIG. 30, the OSTT (FIG. 27D) is the same as the ESTT (FIG. 2D).
7 (A)), the ECC is delayed by the time of the data output cycle (at the timing of outputting the correction result).
It is output from the core circuit 138 to the ECC control circuit 136, and in this embodiment, the OSTT is delayed by 477 ECCK with respect to the ESTT.

If the error detection processing is executed and the detected error can be corrected, the ECC core circuit 138 determines that the EC
For the C control circuit 136, the OSTT (Fig. 28 (E))
= O at the timing of H. CODEERR (Fig. 28
(G)) = L and then outputs ECOR (FIG. 28).
(F)) = H bit data representing the error pattern at the position (H) (data that gives correct data when exclusive OR with erroneous data) ECD [7: 0] (Fig. 2)
8 (H)) and an error position (8-bit data indicating a position (address) with an error) ECA [7:
0] (FIG. 28 (I)) is output.

In the erasure correction mode,
Error position ECA of data corresponding to the position in which the error flag EFLG (Fig. 28 (C)) is input.
[7: 0] data is always output, but if the data at that position is correct, the error pattern is ECD [7:
0] = 00 (H).

When the error correction is impossible, the timing chart is not shown, but the OSTT is not shown.
(FIG. 28 (E)) is in the H state, and at the same time, the O. CO
DEERR (FIG. 28 (G)) = H, and then EC
OR (FIG. 28 (F)) does not become H state. Also,
O. The output of CUDEERR (Fig. 28 (G)) is OST.
T (FIG. 28 (E)) is latched until it becomes H state again, and ECOR (FIG. 28 (F)), ECD [7: 0] (FIG. 28 (H)) and ECA [7: 0] (FIG. 28 (I))
Continues to be output until the OSTT (FIG. 28 (E)) becomes the H state next time.

29 to 31 are timing charts of control at the time of executing the ECC processing. Here, FIG.
PI1- shown in (B), FIG. 30 (B) and FIG. 31 (B)
R, PO-R, or PI2-R are respectively PI
1 (first PI correction), PO (PO correction), or P
The error-corrected data EDT [7: 0] and EFLG (FIG. 28) of each I2 (second PI correction) series.
(C) shows the timing of transfer from the RAM 137 to the ECC core circuit 138 via the ECC control circuit 136.

29 (A), 30 (A) and 31.
As shown in (A), EFM + demodulation circuit 131 to RA
1PI row of data EFM + W (182 for M137)
MWRQ signal is 1 to write byte data)
It is supplied 82 times, and as a result, the EFM + demodulated data for one PI row is written in the RAM 137. And this one
While writing data for PI lines, RA has already been completed.
The data of the ECC block that has been written to M137 is read out, and the EC is read via the ECC control circuit 136.
It is transferred to the C core circuit 138. That is, while the data for one PI row is written in the RAM 137 in a loose manner, the reading of the data of another PI row or PO column which has already been written is rapidly performed three times. Further, when the data of the PI row at the head of the sector is transferred, the subcode data (ID and IED) is also read. When one of these writing and reading is performed, the other is stopped.

For example, when the PI1 correction of the ECC block is performed, the data for one PI row is read during the period for writing the data for one PI row. That is, data for one PI row is read from the RAM 137 and transferred to the ECC core circuit 138 via the ECC control circuit 136. Note that FIG. 29B and FIG.
In (B) and FIG. 31 (B), the read data PI1-R for this PI1 correction is read 208
I am trying to use one ECCK, but this ECCK
This is because the number of is matched to the length of the PO column, which is the longest data length, and when transferring the data of the PI row,
Practically, only 182 ECCKs of these are used for actual data transfer, and the remaining ECCKs are not actually used for data transfer.

FIG. 32 shows a procedure for writing and reading data to and from the RAM 137 by the RAM controller 135 at the time of ECC correction processing. The RAM controller 135 transfers data for one PI line from the RAM 137 to the ECC core circuit 138 in step SP101. . In the case of this embodiment, since the PI code (parity) and the PO code (parity) are added to each ECC block, the first P for the first ECC block is added.
Same ECC until I series correction and write back are completed
Block PO series data PO-R or PI2 series read data PI2-R cannot be transferred. Therefore, in this case, the next 2 × 208 EC
No data is transferred at the timing of CK. Then, if subcode data (SUB) is present next, this is transferred.

Accordingly, the RAM controller 135 is shown in FIG.
In step SP101 and SP102, the PI1-R data of 208 rows of the first ECC block is sequentially transferred in step SP103 while sequentially transferring the data of one PI row of the first ECC block and the SUB code data as needed. Is transferred, and the steps SP101 and SP10 concerned are determined until a positive result is obtained.
2 and SP103 are repeated. Step SP10
If a positive result is obtained in step 3, this means that the first E
This indicates that the data transfer for 208 PI rows of the CC block is all completed, and at this time, the RAM controller 135 moves to step SP104 and transfers PI1-R of the second ECC block following the first ECC block and the second ECC block. Transfer the ECC block PO-R 1 of the following 182
It starts in the period of MWRQ.

That is, in the next 182 MWRQ period, PI1-R of the second ECC block following the first ECC block is transferred first, and then PO-R of the first ECC block is transferred twice. (PO data for two columns is transferred).

When such an operation is performed in each 182 MWRQ period and a total of 172 columns of PO data of the first ECC block are transferred, the RAM controller 1
35 obtains a positive result in step SP105 of FIG. 32, and in the subsequent step SP106, as shown in FIG. 34, the PI2 series data PI2 of the first ECC block.
-Transfer R. This data PI2-R is shown in FIG.
Data is transferred at the same timing as the transfer timing of the data PO-R of the first ECC block shown in FIG. The data PI1-R at this timing is the data of the next ECC block (second ECC block). In this way, the first ECC block PI2-R
Is transferred for 208 PI lines, and P of the first ECC block
When the processing of I1-R, PO-R, and PI2-R is completed, a positive result is obtained in step SP107 of FIG. 32, at which time the RAM controller 135 returns to step SP101 and continues the processing for the ECC block that follows.

ECCK (FIG. 28A) is output from the RAM controller 135 to the ECC core circuit 138 only during the data transfer period. Further, as described above, the correction result of the transferred data is
It will be output after 477 clocks (ECCK). Therefore, the result of the determination as to whether or not the data of a certain series includes an error (FIG. 29C, FIG. 30C, and FIG. 31C) is the result of the series two after the series. It will be output when the data is transferred (FIG. 29 (B),
FIG. 30 (B) and FIG. 31 (B)). This output is stored in the ERR FIFO circuit 136B (FIG. 33) described later.

As described above, from the RAM 137 to the EC
When the data to be error-corrected is input to the C control circuit 136, the ECC control circuit 136 performs PI1 correction of the data for one PI line, for example, and outputs the correction result after 477ECCK (FIG. 29C). 30 (C), FIG. 31
(C)). This correction result is the ECC control circuit 1 described later.
36 is transferred to the ERR FIFO 136B as a buffer and temporarily stored. And this data is
Further, the data read from the ERR FIFO 136B is transferred to the RAM 137 again as the data for which the error correction is completed, and is written as the data PI1-W as shown in FIGS. 30 (D) and 31 (D). Similarly, the data for which the PO correction or the PI2 correction is completed is written in the RAM 137 as the data PO-W or PI2-W, respectively.

As described above, the error-corrected data written in the RAM 137 is further stored in FIG.
As shown in FIGS. 30 (E) and 31 (E), 182S
It is read for each PI row in the cycle of DCK and output from the OCTL circuit 139.

FIG. 33 in which parts corresponding to those in FIG. 12 are assigned the same reference numerals is a block diagram showing the flow of signals when error correction processing is executed. The ECC control circuit 136
ERR COUNT 136A, ERR FIFO 136
B, FLAG RAM 136C, and EX-OR (exclusive OR) circuit 136D.

The demodulated data output from the EFM + demodulation circuit 131 is R under the control of the RAM controller 135.
Written to AM 137. The SUB data (ID and IED) stored at the beginning of each sector is stored in the RAM 137.
Is read out from and is transferred to the SBCD circuit 134. S
The BCD circuit 134 uses the sector information S as shown in FIG.
Generate I. This sector information SI is the SBCD circuit 1
34, and written in the RAM 137.

The RAM controller 135 is the RAM 13
The data for 1 PI line written in 7 (storage means) is used as the error correction data EDT for every 8 bits, ECC
It is supplied to the ECC core circuit 138 via the control circuit 136 (error correction means) (in FIG. 33, for convenience, E
DT data is shown fed directly to the ECC core circuit 138). The ECC core circuit 138 has 1PI
When the data for a row is supplied, the PI code is used to
Bit error correction data ECD (FIG. 28 (H)),
8-bit error correction address ECA (Fig. 28 (I))
Generate The error correction data ECD and the error correction address ECA are transmitted from the ECC core circuit 138 to the ERR FIFO (First In First Ou) of the ECC control circuit 136.
t) Transferred to 136B and written.

Next, in order to actually perform error correction, RA
The M controller 135 reads the PI from the RAM 137.
The row data EDT is read and the EX-OR circuit 136D is read.
To supply. This EX-OR circuit 136D has an ERR
The error correction data ECD and the error correction address ECA are supplied from the FIFO 136B. EX-OR circuit 1
36D performs error correction by calculating the exclusive OR of the error correction data ECD and the data EDT read from the RAM controller 135 at the bit designated by the error correction address ECA. The error-corrected data is transferred from the EX-OR circuit 136D to the RAM 137 via the RAM controller 135.
Will be written back again.

Further, the ECC core circuit 138 generates an error correction result ER composed of 8-bit data as shown in FIG. 34 from the ECD and ECA, and supplies it to the ERR COUNT 136A of the ECC control circuit 136 for storage. Then, this 1-byte error correction result ER is
Via the RAM controller 135, to the RAM 137,
It is written as shown in FIG. 15 corresponding to the PI row.

The following information is stored in each bit of the 8-bit data of the error correction result ER shown in FIG. Bit 7: Uncorrectable (0: Correctable / 1: Uncorrectable)
(It is set to 1 when the error correction of the series is impossible) Bit 6: PO (0: PI / 1: PO) (The series is P
Information bit for determining whether I or PO) Bit 5: PI2 (0: PI1 / 1: PI2) (Information bit for determining whether the series is PI1 or PI2) Bit 4: Correction number (5th bit of error correction number (MS
Value of B) Bit 3: Correction number (4th bit value of error correction number of 4 bits) Bit 2: Correction number (3rd bit value of error correction number of 4 bits) Bit 1: Correction number (4) Value of the second bit of the number of error corrections of the bit) Bit 0: Number of corrections (the value of the first bit of the number of error corrections of 4 bits)

An error flag (PI1 flag) (bit 7 of the error correction result ER) indicating the result of determination as to whether or not the data is uncorrectable by PI1 correction is stored in the ERR COUNT 136A as a part of the error correction result ER. Besides, it is also stored in the FLAG RAM 136C (flag storage means). The above PI1 correction is shown in FIG.
This is performed for 208 PI rows shown in FIG.

Next, the RAM controller 135 uses the RA
The 208-byte data of the first PO column is read from M137, and is supplied to the ECC core circuit 138 as EDT via the ECC control circuit 136. The PI1 flag written in the FLAGRAM 136C is also read and supplied to the ECC core circuit 138. E
The CC core circuit 138 uses the pattern PO and the PI1 flag to perform E for normal correction or erasure correction.
Generate CD and ECA. This ECD and ECA are EC
ERR of the C core circuit 138 to the ECC control circuit 136
It is supplied to the FIFO 136B and stored therein. Also, EC
The error correction result ER of the PO column generated by the C core circuit 138 based on ECD and ECA is ERR CO
It is transferred to UNT 136A and stored. Then, the PO flag corresponding to bit 7 of the error correction result ER among them is also written in the FLAG RAM 136C.

The PO read from the RAM 137
The column data EDT is supplied to the EX-OR circuit 136D. The EX-OR circuit 136D also has an ERR FI
ECD and ECA are supplied from FO136B. EX-
The OR circuit 136D calculates the exclusive OR of ECD and EDT in response to the bit of the address designated by the ECA, and corrects the error. The error-corrected data is written back to the RAM 137.

Also, the error correction result ER of the PO column
Is read from ERR COUNT 136A and RA
Written to M137. Error correction result ER for PO column
18 shows P of 172 rows in order from the top as shown in FIG.
The data is sequentially written in the position corresponding to the I row. PO above
The correction is performed on the 172 PO columns.

Next, in the case of performing PI2 correction,
After PI1 correction and PO correction are performed, the data of the first 1PI row is read from the RAM 137 as EDT and supplied to the ECC core circuit 138. The PO flag written in the FLAGRAM 136C is also read and supplied to the ECC core circuit 138. The ECC core circuit 138 uses this PO flag and parity PI to
ECD and ECA are generated, and the ECC control circuit 13
6 to the ERR FIFO 136B.

The ECD and ECAH written in the ERR FIFO 136B are supplied to the EX-OR circuit 136D, the exclusive OR operation is performed with the PI row data read from the RAM 137, and error correction is executed. . The data for which the error correction is completed is the EX-OR circuit 1
RAM from 36D via RAM controller 135
It is written back to 137.

The ECC core circuit 138 also uses the ECD and E
The error correction result ER is generated from CA, supplied to the ERR COUNT 136A of the ECC control circuit 136, and stored therein. The PI2 flag corresponding to bit 7 is
It is also written in the FLAG RAM 136C.

The error correction result ER of the PI2 row written in the ERR COUNT 136A is ERR COUNT.
It is read from T136A and written in the RAM 137. The error correction result ER of the PI2 row is written in the position corresponding to each PI row of the 208 rows of the ECC block, as shown in FIG. The above PI2 correction is
This is performed for all 208 PI lines.

FIG. 35 is a timing chart showing a state of bus arbitration (arbitration) when accessing the RAM 137. In FIG. 35, EFMREQ (FIG. 35 (A)) indicates that when the EFM + demodulation circuit 131 requests writing of EFM + demodulation data to the RAM 137,
This is a signal output to the RAM controller 135. OUTREQ (FIG. 35B) is an OCTL circuit 1
When the RAM 39 requests reading of the ECC-processed data from the RAM 137, the RAM controller 13
It is a signal output to 5. In addition, ECCREQ (Fig. 35
In (C), the ECC control circuit 136 has the ECC core circuit 1
38, data is transferred to 38, RAM 137 is accessed for error correction, RAM 137 is accessed for error-corrected data,
Alternatively, the SUB transfer (ID
And the IED transfer) to perform the RAM controller 13
5 is a signal output to.

The RAM controller 135 presets the priority order (PriorityLevel) for these three signals, and when these requests are made at the same time, the access right of the RAM 137 is assigned according to the priority order. Acknowledge ACK (authorization) signals are sequentially output. EFMACK
(FIG. 35 (D)), OUTACK (FIG. 35 (E)), E
CCACK (FIG. 35 (F)) is the EFMRE
It is an authorization signal for Q, OUTREQ, or ECCREQ. In this example, the priorities are:
The order is OUTREQ, EFMREQ, and ECCREQ. Therefore, as shown in FIG. 38, the RAM controller 135 outputs an ACK signal for the REQ signal in this order. These signals are transmitted / received in synchronization with C11M (FIG. 35 (G)) as the system clock.

As described above, in this embodiment, the RAM 1
The access right of 37 is EFMRE every predetermined cycle.
It is given in correspondence with any one of Q, ECCREQ, and OUTREQ. However, this cycle is
It is also possible to change according to the configuration, type, or access speed.

FIG. 36 shows the number of times the RAM 137 is accessed when PI1 correction, PI2 correction, and PO correction are executed on 1 ECC block data. As shown in FIG. 36, RAM1 required when PI1 correction, PO correction and PI2 correction are executed
37 times of access is 21 per 1 ECC block
4716 times, the average of one mainframe is 1033
Times. For example, the number of times the RAM 37 is accessed during the write operation of EFM + demodulated data is 182 per mainframe, and the ECC execution cycle length is 208 bytes (208 mainframes), so 37856 (= 182 × 208). ) Is the number of accesses required per block. In this way, the number of accesses required for each operation is calculated, and the sum of these is the above-mentioned value.

FIG. 37 is a timing chart showing the timing of outputting the error correction result ER data from the RAM 137 via the OCTL circuit 139. This figure is
182SDC of 9 (E), FIG. 30 (E), and FIG. 31 (E)
The part preceding the period K is shown with the time axis enlarged. In this figure, SDCK (Fig. 37 (A)) is ER
7 shows a clock signal when the above data is output as stream data. SINF (FIG. 37 (B)) is a sector information strobe signal, which is SIN at the beginning of the sector.
It indicates that F = H and the data to be transferred is sector information (SI). ESTB (Fig. 37 (C))
Is an error correction result strobe signal, and ESTB =
When it becomes H, it indicates that the error correction result ER is transferred. The error correction result ER in each PI line
Since 1 byte is assigned to each of PI1 correction, PO correction, and PI2 correction, is a total of 3 bytes. Since these data are output in the order stored in FIG. 15, it is possible to determine which series of results (data) by checking the bits 5 and 6 (FIG. 34) of the error correction result ER. You can In the PI line where the result of PO correction is not output,
At the timing of outputting the PO correction result, ESTB = L.

DSTB (FIG. 37 (D)) is a signal SD
[7: 0] (FIG. 37 (E)) is a data strobe signal that sets DSTB = H when it is main data.
The three signals SINF, ESTB, or DSTB are:
It is generated by the OCTL circuit 139. Note that FIG.
As shown in (E), the sector information SI and the error correction result ER are output immediately before the data in the PI row direction is transmitted by 182SDCK.

OUTF (interpolation flag) (FIG. 37 (F))
Is an error flag for the main data, and FIG.
PI and P stored in the FLAG RAM 136C of
Based on the O uncorrectable flag, the main data having an error is added with an interpolation flag and then output.

The OCTL circuit 139 determines from the bits 4 and 5 (FIG. 23) of the sector information generated by the SBCD circuit 134 whether or not the data of the sector for which decoding has been completed is the data to be output. Bits 4 and 5 of sector information respectively indicate an end sector and a start sector, as shown in FIG. Therefore, the OCTL circuit 139 outputs the data of the sector whose bit 4 = 0 and bit 5 = 1 as the data of the sector whose output is designated (should be output).

The OCTL circuit 139 also determines whether or not the presence or absence of an error flag in the main data, the EDC result, and the like satisfy the conditions preset by the host CPU 140, and if so, decode the decoded data. Output. If the set output condition is not satisfied, the output of the decoded data is stopped and the host CP
Notify U140 of abnormality.

The data output conditions are set as follows, for example. (1) Data of a sector whose output is specified. (2) No error is detected from the ECC result. (3) No error flag is added to the main data. When the output conditions are set as described above, data satisfying all of these conditions is finally output. Further, regardless of the above conditions, the output can be forcibly prohibited by the host CPU 140.

The OCTL circuit 139 sequentially outputs the main data, the sector information SI and the error correction result ER according to the sector data output procedure as shown in FIG.
First, in step SP111, the OCTL circuit 139 analyzes the end sector detection result stored in the bit 4 of the sector information SI in the OCTL circuit 139 and the start sector detection result stored in the bit 5, and the bit 4 is detected. It is determined that the sector data which is 0 and the bit 5 is 1 is the sector data to be output. As a result, if it is determined in the next step SP112 that the decoded data is not the data to be output, the process proceeds to step SP114 and the data output is stopped.
The output of data is stopped by stopping the output of the data strobe signal by the OCTL circuit 139, for example. If it is determined that the decoded data is the data to be output that satisfies the output condition, step SP1
Proceed to 13.

The OCTL circuit 139 is connected to the step SP113.
At the strobe signal SINF of the sector information SI (FIG. 37).
(B)), strobe signal EST of error correction result ER
B (FIG. 37 (C)), strobe signal D of main data
STB (FIG. 37 (D)) is output in order. As a result, O
In the next step SP115, the CTL circuit 139 receives the sector information SI, the error correction result ER and the main data (D0,
Data is output in the order of D1, D2 ...) and all sectors
When the data output is completed, the sector data output procedure is completed.

(2-3) Operation and effects of the second embodiment With the above configuration, data (PI1-R, PO-R and PI2-) transferred from the RAM 137 to the ECC core circuit 138 within the data transfer period of 182 MWRQ. R (Fig. 2
9, FIG. 30, FIG. 31)) is a transfer clock (ECC).
K) and read from the RAM 137. At this time, the transfer clock (ECCK) is stopped for a predetermined period between transfer sections of each data (PI1-R, PO-R, and PI2-R), so that the data (PI1-R) is stopped during the stop period. , PO-R and PI2-
R) transfer is stopped. That is, each data (PI1
-R, PO-R, and PI2-R), a period in which data is not transferred is formed for a predetermined period.

During this period, the RAM controller 1
35 transfers the main data to the ECC control unit 136 through the ECC core circuit 138, so that the ERR F
The corresponding data in the RAM 137 is read according to the error position information and the correction pattern in the IFO (error register) 136B, and the EX-OR circuit 136D executes the exclusive OR operation to perform the error correction. ,
The ECC process is executed by writing the corrected data in the RAM 137 again.

After executing the PI1 correction (PI1-W), the RAM controller 135 stores the sector address information ID stored in the main frame of the number 0 stored in the RAM 137 and the error detection code for the sector address information ID. IED to SUB (FIG. 29 (B), FIG. 30)
(B), read at the timing of FIG.
It is transferred to the CD circuit 134. The SBCD circuit 134 is
When the address ID of the physical sector is detected, the host CPU
Sector information SI according to the interpolation flag generation mode designated by 140, start sector, end sector, etc.
RAM1 so that it corresponds to a predetermined PI line
Write back to 37. Here, the RAM controller 135
When writing the EFM + demodulated data to the RAM 137, the main data error-corrected according to OUTREQ (FIG. 35B) is used as the sector information SI and the error correction result ER.
Along with reading from the RAM 137, the OCTL circuit 13
Transfer to 9.

When the OCTL circuit 139 determines that the decoded sector data is the data to be output based on the sector information SI, it generates a strobe signal for each data and outputs the strobe signal SIN for the sector information SI.
F, the strobe signal ESTB of the error correction result ER, and the strobe signal DSTB of the main data are output in this order.
As a result, as shown in FIG. 37, the sector information SI, the error correction result ER, and the main data (D0, D1, D2 ...
The data is output in the order of ...).

As described above, when outputting sector data, the sector information SI is followed by the error correction result ER of 3 bytes of PI correction, PO correction and PI2 correction, and further main data. At this time, by analyzing bits 5 and 6 of the error correction result ER, the error correction result P
Whether it is I or PO (bit 6) and whether it is PI1 or PI2 (bit 5) can be easily discriminated. Further, in the main data D0 at the head of the sector data, the sector address information I
Since D is included, the physical address (address on the optical disk 2) corresponding to the error correction result ER can be easily identified.

According to the above configuration, the sector information SI is output immediately before the main data of the decoded ECC block data is output.
By outputting the error correction result ER and the error correction result ER, the sector unit error correction result ER of the main data and the sector address information on the optical disk 2 can be obtained almost at the same time as the main data output. The ECC error analysis corresponding to the address information can be easily performed.

(3) Other Embodiments In the above embodiments, C1 / C2 convolution / Reed-Solomon coding, or error correction inner code is added in the row direction and error correction outer code is added in the column direction. Although the case of decoding the data is described, the present invention is not limited to this, and can be applied to decoding of error-correction-coded data in general. Further, in the above-described embodiment, the case of decoding the coded data that has been error correction coded has been described, but the present invention is not limited to this, and may be widely used in decoding of coded data in general. .

In the above embodiment, the case where the data reproducing device 40 decodes and reproduces the encoded data recorded on the optical disk 2 has been described. However, the present invention is not limited to this, and the code is generally encoded. The present invention can be applied to a case where encoded data is read from a recording medium in which encoded data is recorded, decoded and reproduced.

[0177]

As described above, according to the present invention, when the encoded data recorded on the recording medium is read from the recording medium and decoded, the decoding information of the decoded data is associated with the address data of the recording medium. Therefore, it is possible to realize the data decoding device and the method thereof which can be read and thus can easily analyze the state of the recording medium from the decoding information corresponding to the address data of the recording medium.

Further, according to the present invention, in the data reproducing apparatus for reproducing the image signal and / or the audio signal, when the coded data is read from the recording medium and decoded, the decoded data corresponding to the address data of the recording medium is decoded. Thus, it is possible to realize a data reproducing device which can read information and can easily analyze the state of the recording medium from the decoded information corresponding to the address data of the recording medium.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a data reproducing device according to a first embodiment.

FIG. 2 is a block diagram showing the configuration of the ECC circuit of FIG.

FIG. 3 is a block diagram for explaining the connection of the demodulation circuit, sector detection circuit, and ECC circuit of FIG.

FIG. 4 is a schematic diagram showing data stored in the RAM of FIG.

5 is a chart provided for explaining error information data by the ECC circuit of FIG.

FIG. 6 is a timing chart used for explaining output of error information data by the ECC circuit of FIG.

FIG. 7 is a schematic diagram for explaining an output format of data output from the ECC circuit of FIG.

FIG. 8 is a schematic diagram showing a structure of sector data according to a second embodiment.

FIG. 9 is a schematic diagram showing a configuration of an ECC block according to a second embodiment.

FIG. 10 is a schematic diagram showing interleaving of PO parity (outer code) according to the second embodiment.

FIG. 11 is a schematic diagram showing the data structure of a 32 Kbyte block before EFM modulation according to the second embodiment.

FIG. 12 is a block diagram showing the configuration of the demodulation circuit system of the second embodiment.

FIG. 13 is a schematic diagram showing a configuration of a physical sector after EFM modulation according to the second embodiment.

FIG. 14 is a schematic diagram showing a data structure of each sector of the second embodiment.

FIG. 15 is a schematic diagram for explaining a storage state in a RAM according to a second embodiment.

FIG. 16 is a signal waveform diagram showing an operation of writing the EFM demodulation output of the second embodiment into RAM.

FIG. 17 is a flow chart showing a lock detection processing procedure of the second embodiment.

FIG. 18 is a flow chart showing a procedure for generating an SCSY signal according to the second embodiment.

FIG. 19 is a flowchart showing a main-FMSY signal generation processing procedure according to the second embodiment.

FIG. 20 is a signal waveform diagram for explaining a block-top detection operation of the second embodiment.

FIG. 21 is a signal waveform diagram for explaining a processing operation after block-top detection in the second embodiment.

FIG. 22 is a signal waveform diagram for explaining the transfer operation of the SUB of the second embodiment.

FIG. 23 is a table showing a configuration of sector information according to the second embodiment.

FIG. 24 is a flow chart showing the procedure of the IED continuous normality detection determination process of the second embodiment.

FIG. 25 is a flow chart showing an ID (address) continuity determination processing procedure according to the second embodiment.

FIG. 26 is a flow chart showing a SALK generation processing procedure of the second embodiment.

FIG. 27 is a signal waveform diagram for explaining the error correction operation of the second embodiment.

FIG. 28 is a signal waveform diagram for explaining the error correction operation of the second embodiment.

FIG. 29 is a timing chart for explaining the control operation of the ECC processing according to the second embodiment.

FIG. 30 is a timing chart for explaining a control operation of ECC processing of the second embodiment.

FIG. 31 is a timing chart for explaining the control operation of the ECC process of the second embodiment.

FIG. 32 is a flow chart showing an execution procedure of ECC processing of the second embodiment.

FIG. 33 is a block diagram showing the configuration of the error correction circuit system of the second embodiment.

FIG. 34 is a diagram for explaining an error correction result of the second embodiment.

FIG. 35 is a signal waveform diagram for explaining the bus arbitration of the second embodiment.

FIG. 36 is a schematic diagram showing the number of RAM accesses in the 1ECC block correction of the second embodiment.

FIG. 37 is a signal waveform diagram for explaining the output of the error correction result of the second embodiment.

FIG. 38 is a flow chart showing a processing procedure by the output control circuit of the data output of the second embodiment.

FIG. 39 is a block diagram showing a conventional data reproducing device.

40 is a block diagram showing the ECC circuit of FIG. 39. FIG.

41 is a schematic diagram showing data stored in a RAM for explaining data decoding by the ECC circuit in FIG. 40. FIG.

42 is a schematic diagram showing data stored in a RAM for explaining data decoding by the ECC circuit of FIG. 40. FIG.

43 is a schematic diagram showing data stored in a RAM for explaining data decoding by the ECC circuit in FIG. 40. FIG.

44 is a schematic diagram showing data stored in a RAM for explaining data decoding by the ECC circuit in FIG. 40.

[Explanation of symbols]

1, 40 ... Data playback device, 2 ... Disk, 3 ...
Pickup 4 ... System controller 5, 35
... demodulation circuit system, 6 ... demodulation circuit, 7 ... sector detection circuit, 8, 50 ... ECC circuit, 9 ... track jump determination circuit, 10 ... ring buffer memory, 11 ... ring buffer control circuit, 13 ... Multiplexed data separation circuit, 14 ... Header separation circuit, 15 ... Separation circuit control circuit, 16 ... Switching circuit, 17 ... Video code buffer, 18 ... Video decoder, 19 ... Audio code pattern Hua, 20 ... Audio Decoder, 22
...... Tracking servo circuit, 24, 26, 28, 3
0,51 ... RAM, 25,27,29,52 ... EC
C decoder, 42 ... RF processing circuit, 44, 131 ...
EFM + demodulation circuit, 46 ... CLV control circuit, 48 ...
RMIF, 53 ... Error register, 54 ... ECC control unit, 55 ... ECC decoding unit, 56, 139 ... OCT
L circuit, 134 ... SBCD circuit, 135 ... RAM controller, 136 ... ECC control circuit, 137 ... R
AM, 138 ... ECC core circuit, 140 ... Host C
PU.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11B 20/18 574 G11B 20/18 574B H04N 5/92 H04N 5/92 H (72) Inventor Sato Shigeji 6-7-35 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (28)

[Claims] 1. A data decoding apparatus for reading and decoding coded data recorded on a recording medium, a decoding circuit for decoding the coded data, the coded data read from the recording medium, and the decoding circuit. A memory for storing the decoded data and the decoding information output by the above, and storing the decoded data and the decoding information in the memory by associating the decoding information with the decoding information in frame units. A data decoding device, comprising: memory control means for reading from the memory in frame synchronization with address data of the corresponding recording medium. 2. The data decoding apparatus according to claim 1, wherein the encoded data is error correction encoded data. 3. The data decoding device according to claim 1, wherein the encoded data is variable length data. 4. The error correcting code is a C1 / C2 convolutional / Reed-Solomon code.
The data decoding device according to. 5. The memory control means stores the decoded data in the memory in association with the decoded data for each error correction code sequence of the C1 / C2 convolutional / Reed-Solomon code. Item 4. The data decoding device according to Item 4. 6. The data decoding apparatus according to claim 1, wherein the memory has a first-in first-out (FIFO) function. 7. The data decoding device according to claim 1, wherein the recording medium is a disk recording medium. 8. The data according to claim 1, wherein the memory control means reads the decoded data and the decoded information from the memory in synchronization with a sector address of the recording medium. Decoding device. 9. The data according to claim 1, wherein the error correction code is formed by adding an error correction inner code in the row direction of the encoded data and an error correction outer code in the column direction. Decoding device. 10. The decoding circuit error-corrects the data in the row direction to which the inner code for error correction is added by a first block for each row, and the data in the column direction to which the outer code for error correction is added. Error correction is performed column by column by the first block, and the row direction data is added again by the row unit to the data in the row direction to which the error correction inner code, which is error corrected by the first block by the row, is added. The data decoding device according to claim 9, wherein error correction is performed. 11. The error position stored in the register at the timing when the decoding circuit completes the transfer of the row direction data for one row or the column direction data for one column from the memory. 10. The data decoding device according to claim 9, further comprising: performing error correction based on the error pattern. 12. A data decoding method for reading and decoding coded data recorded on a recording medium, wherein when decoding the coded data, the decoded data and the decoding information are stored in a memory in association with each other in frame units, A data decoding method, characterized in that the decoded data and the decoded information are read in frame synchronization with address data of the recording medium corresponding to the decoded data. 13. The data decoding method according to claim 12, wherein the encoded data is error correction encoded data. 14. The data decoding method according to claim 12, wherein the encoded data is variable length data. 15. The data decoding method according to claim 13, wherein the error correction code is a C1 / C2 convolutional / Reed-Solomon code. 16. The method according to claim 12, wherein the encoded data, the decoded data, and the decoded information are written in and read from the memory in a first-in first-out (FIFO) format. Data decoding method. 17. The memory control means includes the C1 / C2.
16. The data decoding method according to claim 15, wherein the decoded data for each error correction code sequence of the convolutional / Reed-Solomon code is associated with the decoding information and stored in the memory. 18. The data decoding method according to claim 12, wherein the recording medium is a disk recording medium. 19. The error correction code comprises an error correction inner code added in the row direction of the encoded data and an error correction outer code added in the column direction.
The data decoding method described in. 20. In the data decoding method, the data in the row direction to which the inner code for error correction is added is error-corrected by a first block for each row, and the data in the column direction to which the outer code for error correction is added is added. Data is error-corrected by the first block in units of columns, and the error-correction inner code is error-corrected by the first block in units of rows. 20. The data decoding method according to claim 19, wherein error correction is performed again. 21. When transfer of the row direction data for one row or the column direction data for one column is completed from the memory, based on the error position and error pattern stored in the register at the timing. 20. The data decoding method according to claim 19, wherein error correction is executed. 22. The data decoding method according to claim 19, wherein the error correction outer code is interleaved between the first row-direction data and the second row-direction data. 23. The data decoding method according to claim 12, wherein the data decoding method decodes moving image data that has been compression-encoded. 24. In a data reproducing apparatus for reproducing an image signal and / or an audio signal, a decoding circuit for decoding the coded data, the coded data read from the recording medium, and output from the decoding circuit. A memory for storing the decoded data and the decoded information, and the decoded data is stored in the memory in association with the decoded information on a frame-by-frame basis,
And a memory control means for reading the decoded data and the decoded information from the memory in frame synchronization with the address data of the recording medium corresponding to the decoded data. Data playback device. 25. The data reproducing apparatus according to claim 24, wherein the error correction code is a C1 / C2 convolutional / Reed-Solomon code. 26. The error correction code comprises an error correction inner code added in the row direction of the encoded data and an error correction outer code added in the column direction.
A data reproducing apparatus according to claim 1. 27. The decoding circuit error-corrects the data in the row direction to which the inner code for error correction is added by a first block for each row, and the data in the column direction to which the outer code for error correction is added. Error correction is performed column by column by the first block, and the row direction data is added again by the row unit to the data in the row direction to which the error correction inner code, which is error corrected by the first block by the row, is added. The data reproducing apparatus according to claim 24, wherein error correction is performed. 28. The error position stored in the register at the timing when the decoding circuit completes the transfer of one row of the row direction data or one column of the column direction data from the memory. 25. The data reproducing apparatus according to claim 24, wherein error correction is performed based on the error correction pattern.