JPH09282224A - Memory capacity recognizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check the capacity of an extended memory in a short time by a simple program by writing an integer value obtained by dividing maximum memory capacity by unit capacity, in the initial address of the memory and subtracting the numerical value set by write processing in the case of address update processing. SOLUTION: A CPU writes data in the top address of the extended memory and reads out these data so as to judge whether the extended memory is mounted or not (steps S1-S4). Next, data are written in the start address (steps S5 and S6), the capacity of the extended memory is added to this start address and defined as a new address, data are written in this address, read out layer and judged (steps S7 and S8) and this processing is repeated until the read data become '0'. Then, when the read data become '0' (step S8), the capacity of the extended memory is defined as a capacity for which '1' is added to the data at the top address (step S9).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory capacity recognition device for additional memory.

[0002]

2. Description of the Related Art Today, personal computers (hereinafter referred to as
(Personally referred to as a personal computer) has become widespread, and many application programs are commercially available. In particular, recently, the capacity of various application programs has increased, and a large RAM memory is required for their use. For this reason, RAM memory is often added in order to comfortably drive the personal computer. In such cases, shims (SIMMs (single in-line memory modules)) are commonly used as additional memory. When this additional memory is mounted on a computer, the capacity of the mounted additional memory is checked first.

Conventionally, the following two methods have been proposed for this capacity check. (A) First, there is a case where the board itself of the additional memory is equipped with a capacity detection mechanism. In this case, by switching the switching mechanism (switch) provided in the additional memory, the additional memory is mounted on the main body board so that the connected port on the main body side detects the capacity of the additional memory. (B) On the other hand, there is also a method of checking the capacity of the additional memory by software. For example, FIG. 13 is a diagram for explaining this method. 16MB, 8MB, 4M in the figure
5 types of additional memory of B, 2MB, 1MB are shown, and in case of 16MB, all addresses (A23 to A0)
However, 8MB does not use the address (A23), 4MB does not use the addresses (A22, A23), 2MB does not use the addresses (A23 to A21), and 1MB does not use the addresses (A23 to A20). Indicates not to use.

It should be noted that the computer does not know which capacity of memory has been added. Therefore, the conventional memory capacity recognition method writes the value X at the start address “0 0000H” (A19 to A0) for each 1 MB unit,
Addresses corresponding to 1 MB to 16 MB are sequentially read.
That is, the address "10 0000H" of the first MB is read, and if the value X is written in this address "10 0000H", it is determined that the 1 MB memory has been added.
If the value X is not written in the above address, the value of the next 2 MB address "20 0000H" is read and determined. If the value of the address "20 0000H" is also not X, then the address "40 000" is sequentially entered in the order of 4 MB and 8 MB.
Perform the same processing for "0H" and "80 0000H" to check the capacity of the expansion memory.

[0005]

The conventional capacity check method for the additional memory has the following problems. First, in the method (a), since the additional memory is equipped with the capacity detection mechanism, the additional memory itself is expensive. In addition, the computer needs a port for judging the capacity, and if the switch is operated by mistake, the memory capacity cannot be accurately checked.

On the other hand, in the case of the method (b), the expansion memory may be 1 MB. For example, when a memory of 2 MB or more is expanded, the addresses "20 0000H", "40 0000H",
When the data of "800000H" is read, the same value X is read. Therefore, as a result, the address "10 0000
It is necessary to write different values for "H", "20 0000H", "40 0000H", and "80 0000H".
Therefore, a complicated program is required to check the capacity of the additional memory. In addition, it takes a long time to check the capacity.

The present invention has been made in view of the above circumstances, and provides a memory capacity recognizing device capable of checking the capacity of an additional memory in a short time with a simple program without using an expensive additional memory. Is to provide.

[0008]

According to the present invention, a memory having a predetermined capacity is defined as one unit, and a memory having an integral multiple of the unit capacity can be arbitrarily selected and added to an electronic device memory. In the capacity identifying device, a writing process of writing data corresponding to an integer value obtained by dividing the maximum expandable memory capacity by the unit capacity into an initial address of the memory, an address updating process of updating an address for each unit capacity, At the time of the address update process, a subtraction process for subtracting the numerical value set by the write process, and when the subtracted value by the subtraction process reaches a predetermined value, data remaining at the initial address is added to the memory capacity of the electronic device. This can be achieved by providing a memory capacity recognition method that performs recognition processing for recognizing.

That is, a numerical value (data) corresponding to an integer value obtained by dividing the maximum expandable memory capacity by the unit capacity is set for the initial address of the memory whose capacity is to be recognized, and the subtraction process is performed for each unit capacity. When the address is updated, the value is decremented by one, for example, until the decrement value becomes "0". At this time, for example, if the value initially set in the initial address is maintained, the expanded memory capacity Is recognized as the maximum memory capacity. On the other hand, if a memory with a capacity smaller than the maximum memory capacity is added, new data is written to the initial address by the time the subtraction value becomes "0", and that value is the capacity of the added memory. Becomes

For example, when the numerical value set in the initial address by the writing process is smaller than the maximum memory capacity by one unit capacity and the numerical value becomes a predetermined value by the subtraction process, the memory capacity is set to the numerical value set in the initial address. +
The capacity may be one. in this case,
For example, if the maximum memory capacity is 16 MB, the numerical value set to the initial address is 15, and the memory capacity when the numerical value becomes a predetermined value (for example, “0”) by the subtraction processing is the numerical value set to the initial address. It can be seen that the capacity is 16 MB since the capacity is +1.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a system configuration diagram of a memory capacity recognition device of one embodiment. The memory capacity recognition device of the present embodiment is used not only when a memory is added to a computer such as a personal computer but also when a RAM memory is added to a printer device, a scanner, a mobile terminal device, or the like.

In FIG. 1, a CPU 1 is a central processing unit of equipment to which the memory capacity checking apparatus of this embodiment is applied, and controls processing of equipment according to a program stored in a ROM 2. Also, a check program of a memory capacity described later is registered in the ROM 2. The RAM 3 stores the data generated during the control processing of the CPU 1, and also stores the system program read from the hard disk or the like. The expansion memory 4 is a memory mounted to expand the capacity of the RAM 3 and has a predetermined memory capacity.

FIG. 2 is a diagram showing the structure of the additional memory 4, 5 indicates an additional memory having a memory capacity of 16 MB, and 6
Indicates an additional memory with a memory capacity of 8 MB, 7 indicates an additional memory with a memory capacity of 4 MB, 8 indicates an additional memory with a memory capacity of 2 MB, and 9 indicates an additional memory with a memory capacity of 1 MB. In * A shown in the figure, all address data are 0.
Means inputting an address that is. Further, which of the additional memories 5 to 9 shown in FIG. 1 is installed as the additional memory 4 in FIG. 1 is unknown before the memory capacity check described later.

Normally, when the additional memory 4 is added to a device such as a computer or a printer, the power of the device is reset and the initial setting process of the device is performed. At this time, ROM2
The memory capacity recognition program registered in function. FIG. 3 is a flow chart for explaining this program processing, and the CPU 1 executes this program to recognize the capacity of the additional memory 4.

First, the top address "00" of the expansion memory 4
The data "AA" is written in "0000H" (step (hereinafter referred to as S) 1), and then the top address "00 0
By reading the data written in "000H", CP
U1 determines whether the read data is "AA" (S
2). This judgment is to judge whether or not the additional memory 4 is mounted on the main body board of the device.
When "A" cannot be read (NO in S2), it is determined that the additional memory 4 is not installed.

On the other hand, when the data read from the top address is "AA" (YES in S2), the CPU
1 writes different data "55" to the top address (S3), reads the data written to the top address again, and determines whether this data is "55" (S4). In this way, the reason why data is written twice at the top address and the data is read and judged is to reliably judge the mounting state of the additional memory 4. Therefore, if this determination (S4) is NO, it is of course determined that the additional memory 4 is not installed.

On the other hand, if it is determined that the additional memory 4 is mounted on the main body board by checking the mounting of the additional memory 4 twice (YES in S4), the CPU 1 next starts the start address "00 0000H" (this In this case, the start address is the same as the above-mentioned top address)
(H) "(where H indicates a hexadecimal number) is set to write data (S5), and data" 0F (H) "is written to the start address (S6).

Next, the CPU 1 adds "10 0000H" to the above-mentioned start address "00 0000H" to make a new address "10 0000H", and writes data "0E" to this address (S7). After that, the data of this address "10 0000H" is read and it is judged whether this data is "0" (S8). However, as described above, at this time the address "10
The data read from "0000H" is "0E", and the first judgment (S8) is NO.

Therefore, the CPU 1 performs the process again (S6,
S7) is executed, the data "0D" is written to the new address "20 0000H", the data at this address "20 0000H" is read, and it is determined whether this data is "0" (S8). However, this judgment is also NO, and after that, the CPU
1 repeats the above-described processing (S6 to S8) until the data read from the updated address becomes "0".
The data read from the updated address is "0"
When (S8 is YES), the capacity of the extension memory 4 is set to the capacity obtained by adding 1 to the data of the top address (S8).
9).

Here, the above-described processing (S5 to S9) will be described using a specific memory map. 4A shows the case where the expansion memory 4 is 16 MB, FIG. 4B shows the case where the expansion memory 4 is 8 MB, and FIG. 4C shows the case where the expansion memory 4 is 4 MB. Further, FIG. 5A shows the case where the extension memory 4 is 2 MB, and FIG. 5B shows the case where the extension memory 4 is 1 MB. First, the expansion memory 4 has 16
The case of MB will be described. In this case, FIG.
As shown in (a), the first start address "00 000
Data "0F" is written to "0H" (S5), data "0E" is written to the next address "10 0000H" (S7), and data "0F" is sequentially written to address "20 0000H".
D ", data" 0C "at address" 30 0000H ", ...
・ Data “0” is written to the address “F0 0000H”. Therefore, after writing the data “0” to the last address “F0 0000H”, the judgment (S8) becomes YES,
At this time, the data "0F", that is, the data 15 in decimal notation, is written in the start address at this time, and the capacity of the additional memory 4 becomes 16 (15 + 1) (S9). Therefore, the additional memory 4 installed in the device by the above processing
Is easily found to be 16 MB of memory.

Next, a case where the expansion memory 4 is 8 MB will be described. Also in this case, the same data "0F" as described above is written to the first start address "00 0000H" (S5), and the data "0E" is written to the next address "10 0000H" (S7). Sequential address "20
Data "0D" is written to "0000H", data "0C" is written to address "30 0000H", ...
・ Data “08” is written to the address “70 0000H”. However, in the case of the 8 MB memory, the address "80 0000H" to be written next is the start address "00 0000H" to which the data "0F" was previously written. Further, the next address "90 0000H" is the address "10 0000H" to which the data "0E" is written. That is, in the case of the 8 MB additional memory 6, the address (A23) as shown in FIG.
Is not connected, therefore, when data is supplied to the addresses "80 0000H" to "F0 0000H" indicated by * 1 in FIG. 4B, the above-mentioned start address "00 0000H" to address "70
New subtraction data is written by "0000H".

Therefore, the address "00 0000H"("800000H"
The data “07” is written in “0000H”, the data “06” is written in the address “10 0000H” (“90 0000H”), and new data “05”, “04”,
..., "0" is written. Therefore, when the data “0” is written to the last address “70 0000H” (“F0 0000H”), the data “07”, that is, the data 7 in decimal number is written to the start address “00 0000H”. The capacity of the expansion memory 4 becomes 8 (7 + 1) (S9), and it is immediately understood that 8 MB of memory has been expanded in the expansion memory 4.

Next, a case where the extension memory 4 is 4 MB will be described. In this case as well, similar to the case of 8 MB, data “0F” to “0C” are sequentially written from the first start address “00 0000H” to the fourth address “300000H”. The write address "40 0000H" is returned to the start address "00 0000H" where the data "0F" was previously written. That is, 4
In the case of the expanded memory 7 of the MB, the addresses (A23, A22) are not connected as shown in FIG.
Addresses indicated by * 2 in (c) "40 0000H" to "70 000"
0H "," 80 0000H "~" B0 0000H "," C0 0000H "~
When data is supplied to "F0 0000H", new subtracted data is repeatedly supplied to the above-mentioned start address "00 0000H" to address "30 0000H".

Therefore, "30 0000H"("F00000H")
When the data “0” is written to the start address “00 0000H”, the data “03”, that is, the data 3 is written in decimal, and the capacity of the extension memory 4 is 4
It is easy to see that it is (3 + 1) MB.

Next, a case where the expansion memory 4 is 2 MB will be described. This example is shown in FIG. 5 (a) as described above, but more specifically in FIG. 6 to FIG. 9 including the change of the memory contents. First, FIG. 6A shows that data “0F” is written to the first start address “00 0000H”, and FIG. 6B shows that data “0E” is written to the next address “100000H”. . When the memory capacity is 2MB, the address to write the next data "0D" is "20 0
It is not 000H ”but the start address“ 00 0000H ”to which the data“ 0F ”has been previously written. Therefore, the next address (start address) "00 0000H" (30 0000H
The data “0D” is written in “H”). That is,
Here, the data of the start address "00 0000H" is "0
Rewriting (updated) from "F" to "0D" (Fig. 6)
(C)).

Subsequently, also in the data writing to the next address "30 0000H", the address for writing the data "0C" is not "30 0000H", but the address "10 0000H" where the data "0E" was previously written. Is. Therefore, in this case as well, the next address "10 0000H" (30 000H
Data “0C” is written to 0H ”) and the address“ 10C ”is written.
The data of "0000H" is rewritten (updated) from "0E" to "0C" (see FIG. 6D).

Similarly, data is sequentially updated every 2 MB, and data "0B" and "0A" are next stored at the start address "00 0000H" and the next address "10 0000H".
Is written (see FIG. 7B). Further, the data of the start address "00 0000H" and the next address "10 0000H" are the data "09" and "08" (see FIG. 7D).
→ Data “07” and “06” (see FIG. 8B) → Data “05” and “04” (see FIG. 8D) → Data “0”
3 "and" 02 "(see FIG. 9 (b)) → data" 01 "and" 0 "(see FIG. 9 (d)) are sequentially updated, and when the data" 0 "is written, the start address" 00 0000
The data of "H" has been updated to "01". Therefore, it can be seen that the additional memory 4 has a capacity of 2 (1 + 1) MB.

If the extension memory 4 is 1 MB and the data "0" is written as shown in FIG. 5B, the data of the start address "00 0000H" is "0".
Therefore, it can be seen that the additional memory 4 is equipped with a memory having a capacity of 1 MB.

Further, in the example of the above-mentioned embodiment, the data "0F" (15 decimal number) is assigned to the start address "00 0000H".
(Data indicating that) is written first, but the data to be written first is not limited to this data.

FIG. 10 is a flow chart showing an example thereof. In the figure, each process and judgment is indicated by a symbol of step ST, but corresponds to each step S of the flowchart shown in FIG. However, in the process of ST5, the process of writing data “10” (data indicating 16 in decimal) to the start address is different, and ST
8 is different in that it is determined whether or not the subtraction data is "1".

That is, in the processing after determining whether or not the additional memory 4 is mounted (ST1 to 4), the data is sequentially decremented by 1 (ST6 to 8), and the start address when the data becomes "1" is set. By checking the data, the start address data itself indicates the memory capacity.

For example, in FIG. 11A, the extension memory 4 has one
The case of 6 MB is shown, and in the figure (b), the expansion memory 4 has 8 M
The case of B is shown, and FIG. 7C shows the case where the extension memory 4 is 4 MB. Further, in FIG.
In the case of MB, the expansion memory 4 is 1 MB in the same figure (b).
The case of is shown. As shown in both figures, the data of the start address “000000H” when the data “1” is written is the memory capacity itself of the additional memory 4 in any capacity memory.

The present invention is not limited to the case of inputting data "0F" or "10" to the start address.

[0034]

As described above, according to the present invention, the data written at the start address is automatically rewritten to the memory capacity of the expanded memory to be checked, and the expanded memory capacity can be known very easily. it can.

Further, the processing program of the present invention writes the numerical value corresponding to the maximum value of the expandable memory capacity to the start address, and thereafter subtracts this numerical value to automatically update the data of the start address to the final value. It is possible to recognize the memory capacity by reading the information, and it is possible to reduce the cost of the entire apparatus without using an expensive additional memory.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a memory capacity check device according to an embodiment.

FIG. 2 is a diagram showing a configuration of an additional memory.

FIG. 3 is a flowchart illustrating a program process of the memory capacity check device according to the embodiment.

FIG. 4A shows an example in which the expansion memory is 16 MB. (B) shows an example when the extension memory is 8 MB.
(C) shows an example when the expansion memory is 4 MB.

FIG. 5A shows an example in which the extension memory is 2 MB. (B) shows an example when the expansion memory is 1 MB.

FIG. 6 shows an example when the extension memory is 2 MB.

FIG. 7 shows an example when the extension memory is 2 MB.

FIG. 8 shows an example when the extension memory is 2 MB.

FIG. 9 shows an example when the extension memory is 2 MB.

FIG. 10 is another flowchart illustrating the program processing of the memory capacity check device.

FIG. 11A shows an example in which the expansion memory is 16 MB. (B) shows an example when the extension memory is 8 MB.
(C) shows an example when the expansion memory is 4 MB.

FIG. 12A shows an example in which the extension memory is 2 MB. (B) shows an example when the expansion memory is 1 MB.

FIG. 13 is a diagram illustrating a process of a conventional memory capacity check device.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 Expansion memory 5 Expansion memory (expansion memory with 16MB memory capacity) 6 Expansion memory (expansion memory with 8MB memory capacity) 7 Expansion memory (expansion memory with 4MB memory capacity) 8 Expansion memory (memory) Expansion memory with a capacity of 2MB) 9 Expansion memory (expansion memory with a memory capacity of 1MB)

[Procedure amendment]

[Submission date] June 18, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG.

Claims (2)

[Claims] 1. A memory capacity identification device for an electronic device, wherein a memory having a predetermined capacity is defined as one unit, and a memory having an integral multiple of the unit capacity can be arbitrarily selected to be expanded. A writing process of writing data corresponding to an integer value divided by a unit capacity to an initial address of the memory, an address updating process of updating an address for each unit capacity, and a writing process set by the writing process during the address updating process. A subtraction process for subtracting a numerical value, and a recognition process for recognizing the data remaining at the initial address as the memory capacity added to the electronic device when the subtraction value obtained by the subtraction process reaches a predetermined value. Memory capacity recognition method. 2. The data set to the initial address by the writing process is one unit capacity smaller than the maximum expandable memory capacity, and +1 is added to the data remaining at the initial address when the subtraction value becomes a predetermined value. The data that has been stored is the capacity of the expanded memory.
The memory capacity recognition method described.