JP2858816B2 - Initial setting method of EEPROM - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initialization method for an EEPROM, and more particularly, to an EEPROM for manufacturing or inspecting an electronic device equipped with the EEPROM.
Related to the initialization method.

[Conventional technology]

Conventionally, when manufacturing or inspecting an electronic device equipped with an EEPROM (electrically erasable and rewritable read-only memory), the initial setting method of the EEPROM is such that information indicating an operation mode of the electronic device is manually transmitted from an external terminal. The EEPROM is initialized by inputting data by operation. This will be described with reference to FIG. In the figure, reference numeral 101 is an EEPROM 105
, A terminal 102 for initializing the device 101, a communication circuit 103 for performing communication with the terminal 102, a ROM (read-only memory) 104, an EEPROM 105,
06 indicates a CPU (processor).

The initial setting procedure will be described below. The device 101 operates based on undefined data in the EEPROM 105 in a state where the EEPROM 105 is not initialized. In this state, the terminal 102 is connected to the device 101, and an initial set value is manually input. The CPU 106 stores the initial setting value input via the communication circuit 103 at a predetermined address of the EEPROM 105. After the initial setting, the CPU 106 operates based on the data on the EEPROM 105.

[Problems to be solved by the invention]

The above-described conventional EEPROM initial setting method is performed manually from a terminal, so that it takes time and effort to perform the initial setting, and there is a disadvantage in that the operation efficiency is reduced due to a terminal operation error or the like.

[Means for solving the problem]

The method of the present invention employs an electrically erasable and rewritable read-only memory (EEPR) having an area for storing check data indicating that the initial data has been written.
OM) and a read-only memory (RO) storing the initial data suitable for each operation mode at the time of initial setting.
M), an input port for reading the data indicating the operation mode, and reading the operation mode data from the input port at the time of initial setting, reading the initial data conforming to the operation mode data from the ROM, and transferring the data to the EEPROM. A device having a processor for writing and controlling the operation of storing the check data in the EEPROM; and a plurality of strap terminal pairs each connected to a voltage pull-up resistor. A data generating circuit for providing the operation mode data to the input port according to the presence or absence.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, reference numeral 201 denotes a device equipped with an EEPROM, 202
Is an input port for operating mode input, 203 is ROM, 204 is EEP
ROM and 205 indicate a CPU, R indicates a pull-up resistor connected to the voltage VDD, and 208 to 209 indicate a pair of strap terminals for setting an operation mode.

FIG. 2 is a flowchart showing the initial setting process in the CPU 205. After performing the normal initialization (step 301), the CPU 205 checks whether or not the initial data has already been written to the EEPROM 204 before performing the initialization of the EEPROM 204 (step 302). For checking whether or not the initial data has been written, an address space for several bytes is prepared in the EEPROM 204 in advance. When the initial data is written, check data having a predetermined pattern of several bytes is written in the address space for the check, and when the initial data is not written, the check data is undefined. (Writing of check data will be described later). When the check data is indefinite, the length of the check data is set to several bytes in order to sufficiently reduce the probability of coincidence with a preset pattern. still,
The initial setting of the EEPROM 204 in the initial setting process is a process that is not performed after the initial data has been written to the EEPROM 204 even once, and the check data is undefined because the EEPROM 204 has been written once Since there is no data, there is almost no probability that the indefinite data matches a preset pattern. The CPU 205 reads the check data, determines that the initial data has already been written to the EEPROM 204 if it matches the pattern set in advance, and has not yet written the initial data to the EEPROM 204 if it does not match. Judge (step
302). When the CPU 205 determines that the initial data has been written to the EEPROM 204, the CPU 205 ends the initial setting process, and when it determines that the initial data has not been written to the EEPROM 204, The operation mode is read (step 303). The operation mode is specified by binary data generated by a circuit composed of the strap terminal pairs 208 to 209 and the pull-up resistor R, and is set in advance by the presence or absence of a strap wiring between each terminal pair prior to the initial setting. ing. The CPU 205 selects the initial data on the ROM 203 corresponding to the input operation mode, and
Is transferred to a predetermined address (step 304). Where ROM20
On the top of FIG. 3, initial data is prepared corresponding to each operation mode that can be set by the strap terminal pairs 208 to 209.
After the transfer of the initial data to the EEPROM 204 is completed, the CPU 205
Writes the check data to the address for the check data in the EEPROM 204 (Stape 305). The initialization processing ends.

Next, the reason why it is necessary to check that the initial data has been written in the EEPROM 204 in step 302 in FIG. 2 will be described. After finishing the above-described initialization processing, the CPU 205 starts operating according to the initial data on the EEPROM 204. Normally, while processing is being performed, the CPU
Is changed. When turning on the power or resetting,
If the data in the ROM 203 is uniformly transferred without checking whether or not the initial data has been written to the EEPROM 204 in the initial setting process, the settings in the EEPROM 204 up to the previous time will be erased. To prevent this, it is necessary to check whether the initial data has been written to the EEPROM 204.

〔The invention's effect〕

As described above, the present invention enables the CPU to transfer an initial setting value suitable for the operation mode indicated by the setting state of the strap terminal pair from the ROM to the EEPROM.
The initial setting of M can be performed automatically. As a result,
This eliminates the need for manual operation of the terminal as in the conventional method, reduces the number of work steps for performing the initial setting, and has the effect of preventing a decrease in work efficiency due to a terminal operation error or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a flowchart of an initial setting process in an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional system. is there. 101,102 …… Device, 202 …… Input port, 104,203 …… RO
M, 105, 204 ... EEPROM, 106, 205 ... CPU, 208-209 ...
Strap terminal pair, R ... pull-up resistor.

Claims (2)

(57) [Claims] 1. An electrically erasable and rewritable read-only memory (EEPROM) having an area for storing check data indicating that initial data has been written.
And a read-only memory (ROM) storing the initial data suitable for each operation mode at the time of initial setting.
An input port for reading the data indicating the operation mode, and reading the operation mode data from the input port at the time of initial setting, reading the initial data conforming thereto from the ROM, transferring the data to the EEPROM, and writing the data. A device having a processor that controls the operation of storing the check data in the EEPROM; and a plurality of strap terminal pairs connected to the voltage pull-up resistors, respectively. A data generating circuit for providing the operation mode data to the input port in response to the operation mode data. 2. The EEPROM initial setting method according to claim 1, wherein said data generation circuit is built in said device.