CN113297014A - Method and device for identifying capacity of memory to be tested, electronic equipment and storage medium - Google Patents
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Abstract
The invention provides a method and a device for identifying the capacity of a memory to be tested, electronic equipment and a storage medium. The identification method comprises the following steps: determining a first address, wherein the first address is larger than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory; determining a mirror image address of the first address according to the coding rule of the second memory, wherein the mirror image address is smaller than or equal to the second addressing range, and the mirror image address refers to an address pointing to the same storage unit as the first address when the CPU accesses the second memory; and identifying the capacity of the memory to be tested through the read-write operation of the first address and the mirror image address. The identification method of the invention can lead the software to distinguish the capacity of the memory at the initial stage of the initialization, and the hardware does not need to separately make the identification mark of the product model for distinguishing the memory capacity.
Description
Technical Field
The invention belongs to the technical field of memory capacity identification, and particularly relates to a method for identifying the memory capacity to be detected, a device for identifying the memory capacity to be detected, electronic equipment and a computer-readable storage medium.
Background
With the development of software, the requirement of the software on the size of a memory is larger and larger. Products that have been released may be faced with insufficient memory capacity. The memory capacity is enlarged and at the same time the necessary information is needed to indicate the change of the memory capacity, so that it can be ensured that one software image can be compatible with two kinds of hardware. If the hardware is modified due to lack of necessary memory capacity indication, it costs money and time. If the software provides two images for two versions, the software maintenance costs are increased.
For the memory capacity change, it is common to provide a capacity change identification instruction by providing a model identification resistor on a circuit board or by providing hardware such as a capacity identification register to provide identification information.
However, the above-described instruction methods for memory capacity change require hardware modifications for providing necessary instruction information. Hardware revisions can result in extended product release cycles and also can be more capital and labor intensive. If the hardware is not changed, the software needs to provide two images, which increases the maintenance cost of the software.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a method for identifying a memory capacity to be tested, an apparatus for identifying a memory capacity to be tested, an electronic device, and a computer-readable storage medium.
In an aspect of the present invention, a method for identifying a capacity of a memory to be tested is provided, where the memory to be tested includes a first memory and a second memory, and the capacity of the first memory is greater than the capacity of the second memory, and the method includes:
determining a first address, wherein the first address is larger than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory;
determining a mirror image address of the first address according to the coding rule of the second memory, wherein the mirror image address is smaller than or equal to the second addressing range, and the mirror image address refers to an address pointing to the same storage unit as the first address when the CPU accesses the second memory;
and identifying the capacity of the memory to be tested through the read-write operation of the first address and the mirror image address.
In some optional embodiments, the identifying the capacity of the memory to be tested through the read-write operation on the first address and the mirror address includes:
writing first data into the first address, and writing second data into the mirror image address;
reading first actual data from the first address and reading second actual data from the mirror address;
and identifying the capacity of the memory to be tested according to the first actual data and the second actual data.
In some optional embodiments, the identifying, according to the first actual data and the second actual data, the capacity of the memory to be tested includes:
if the first actual data is equal to the second data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the first actual data and the second data are not equal, matching the capacity of the memory to be tested with the capacity of the first memory.
In some optional embodiments, the identifying, according to the first actual data and the second actual data, the capacity of the memory to be tested includes:
if the second actual data is equal to the first data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the second actual data is not equal to the first data, matching the capacity of the memory to be tested with the capacity of the first memory.
In another aspect of the present invention, an apparatus for identifying a capacity of a memory to be tested, where the memory to be tested includes a first memory and a second memory, and the capacity of the first memory is greater than the capacity of the second memory, includes:
an address determining unit, configured to determine a first address, where the first address is greater than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory; and the number of the first and second groups,
the address determining unit is further configured to determine a mirror address of the first address according to a coding rule of the second memory, where the mirror address is smaller than or equal to the second addressing range, and the mirror address is an address pointing to the same storage unit as the first address when the CPU accesses the second memory;
and the identification unit is used for identifying the capacity of the memory to be tested through the read-write operation of the first address and the mirror image address.
In some optional embodiments, the identifying unit includes a writing subunit, a reading subunit, and an identifying subunit, and the identifying the capacity of the memory to be tested by performing a read-write operation on the first address and the mirror address includes:
the writing subunit is configured to write first data to the first address, and write second data to the mirror address;
the reading subunit is configured to read first actual data from the first address, and read second actual data from the mirror address;
the identifying subunit is configured to identify the capacity of the memory to be tested according to the first actual data and the second actual data.
In some optional embodiments, the identifying, according to the first actual data and the second actual data, the capacity of the memory to be tested includes:
the identifier unit is specifically configured to:
if the first actual data is equal to the second data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the first actual data and the second data are not equal, matching the capacity of the memory to be tested with the capacity of the first memory.
In some optional embodiments, the identifying, according to the first actual data and the second actual data, the capacity of the memory to be tested includes:
the identifier unit is specifically configured to:
if the second actual data is equal to the first data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the second actual data is not equal to the first data, matching the capacity of the memory to be tested with the capacity of the first memory.
In another aspect of the present invention, an electronic device is provided, including:
one or more processors;
a storage unit for storing one or more programs which, when executed by the one or more processors, enable the one or more processors to implement the method according to the preceding description.
In another aspect of the invention, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, is adapted to carry out the method according to the above description.
In another aspect of the invention, a computer program is provided, which, when being executed by a processor, is capable of carrying out the method according to the above description.
The memory capacity identification method and the identification device of the invention find out the first address and the mirror image address which have mirror image relation relative to the second memory with small capacity according to the first memory and the second memory with known capacity, and then identify the capacity of the memory to be detected by reading and writing the first address and the mirror image address.
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Fig. 1 is a schematic structural diagram of an electronic device according to a first embodiment of the present invention;
fig. 2 is a flowchart of a method for identifying a memory capacity to be tested according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first memory and a second memory according to a third embodiment of the present invention;
FIG. 4 is a diagram illustrating a DDR SDRAM according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of an apparatus for identifying a memory capacity to be tested according to a fifth embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
First, an exemplary electronic device for implementing the identification apparatus and the identification method of the embodiment of the present invention is described with reference to fig. 1.
As shown in FIG. 1, electronic device 200 includes one or more processors 210, one or more memory devices 220, one or more input devices 230, one or more output devices 240, and the like, interconnected by a bus system 250 and/or other form of connection mechanism. It should be noted that the components and structures of the electronic device shown in fig. 1 are exemplary only, and not limiting, and the electronic device may have other components and structures as desired.
The processor 210 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 200 to perform desired functions.
Storage 220 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, Random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, Read Only Memory (ROM), hard disk, flash memory, etc. On which one or more computer program instructions may be stored that may be executed by a processor to implement client functionality (implemented by the processor) and/or other desired functionality in embodiments of the invention described below. Various applications and various data, such as various data used and/or generated by the applications, may also be stored in the computer-readable storage medium.
The input device 230 may be a device used by a user to input instructions and may include one or more of a keyboard, a mouse, a microphone, a touch screen, and the like.
The output device 240 may output various information (e.g., images or sounds) to an outside (e.g., a user), and may include one or more of a display, a speaker, and the like.
As described in the background section, it is assumed that there are two memories with different capacities, namely, a large-capacity memory and a small-capacity memory, but for software to be executed, it is not known whether the software is to be executed on the small-capacity memory or the large-capacity memory, and therefore, in order to ensure software compatibility, the problem of memory capacity identification is declared, and it is understood that as software, it is impossible to open a housing from one device to another to see what kind of memory is at all, and only the software can perform the identification.
Based on this, the inventor of the present invention provides an identification method and an identification device for identifying the capacity of the memory to be tested.
Next, an identification method according to an embodiment of the present invention will be described with reference to fig. 2.
As shown in fig. 2, an identification method S100 of a capacity of a memory to be tested, where the memory to be tested includes a first memory and a second memory, and the capacity of the first memory is greater than the capacity of the second memory, the identification method includes:
s110, determining a first address, wherein the first address is larger than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory.
Specifically, in this step, an address X that does not exceed the first addressing range but exceeds the second addressing range is selected as the first address according to the first addressing range of the first memory and the second addressing range of the second memory.
For example, assume that the first addressing range of the first memory is 0x 0-0 x7FF, where a is 0x7 FF; the second addressing range of the second memory is 0X 0-0X 3FF, B is 0X3FF, and obviously, the address X should be greater than 0X3FF and less than 0X7 FF.
S120, determining a mirror image address of the first address according to the encoding rule of the second memory, wherein the mirror image address is smaller than or equal to the second addressing range, and the mirror image address is an address pointing to the same storage unit as the first address when the CPU accesses the second memory.
Specifically, in this step, it is determined that, when the memory is the second memory, the storage unit corresponding to the access address X of the CPU is the storage unit corresponding to the actually accessed address Y according to the address coding mode of the second memory, that is, when the CPU accesses the second memory, the address X and the address Y point to the same storage unit, and the address Y should be in the second addressing range. Let us say that address X and address Y are mirror addresses of a pair of second memories, and address X and address Y do not constitute mirror addresses in the first memory.
Illustratively, as shown in fig. 3, the first addressing range of the first memory is 0x 0-0 x7FF, and the second addressing range of the second memory is 0x 0-0 x3FF, so that a target address is selected as the first address from the addressing address range 0x 400-0 x7FF which is larger than the second addressing range and smaller than or equal to the first addressing range, for example, 0x400 address is selected as the first address. The second memory uses Addr 0-Addr 9,10 address lines are used for address coding, when the address is 0x400, Addr 0-Addr 9 are all 0, when the memory is the second memory, the CPU accesses the 0x400 address, and actually accesses the 0x0 address. I.e., the 0x0 address and the 0x400 address correspond to the same memory location for the second memory, and thus the two addresses are mirror addresses.
S130, identifying the capacity of the memory to be tested through the read-write operation of the first address and the mirror image address.
Specifically, in this step, according to the above description, if the first address and the mirror address having a mirror relationship with the first address are found, the capacity of the memory to be tested can be determined through the read operation on the two addresses.
In the method for identifying the capacity of the memory to be tested according to the embodiment, the first address and the mirror image address which have a mirror image relationship with respect to the second memory with a small capacity are found out according to the first memory and the second memory with known capacities, and the capacity of the memory to be tested is identified through read-write operations on the first address and the mirror image address.
The memory identification method provided by the embodiment of the invention is simple, can also enable software to distinguish the capacity of the memory at the initial stage of initialization, and does not need to separately make identification marks of product models for distinguishing the memory capacity on hardware.
Illustratively, the identifying the capacity of the memory to be tested through the read-write operation on the first address and the mirror address includes:
and writing first data into the first address, and writing second data into the mirror image address. First real data is read from the first address, and second real data is read from the mirror address. And identifying the capacity of the memory to be tested according to the first actual data and the second actual data.
For example, in some optional embodiments, the identifying, according to the first actual data and the second actual data, the capacity of the memory to be tested includes:
and if the first actual data is equal to the second data, determining that the capacity of the memory to be tested is matched with the capacity of the second memory, and if the first actual data is not equal to the second data, determining that the capacity of the memory to be tested is matched with the capacity of the first memory.
Specifically, in this step, as shown in fig. 3, the two addresses having the mirror relationship are the address 0x400 and the address 0x0, so that the first data, such as 0xAAAA, can be written to the address 0x400, and the second data, such as 0x5555, can be written to the address 0x 0. Then, the first actual data is fetched according to the 0x400 address, if the first actual data fetched from the first address 0x400 is 0x5555, it indicates that the same storage unit is written in the address 0x400 and the address 0x0, the two addresses are mirror addresses, and the memory to be tested is a small memory, i.e., a second memory. On the contrary, if the first actual data fetched from the first address 0x400 is not 0x5555, it indicates that the same storage unit is not written in the address 0x400 and the address 0x0, and the two addresses are not mirror addresses, and the memory to be tested is a large memory, i.e. the first memory. Therefore, whether the memory to be tested is a large-capacity memory or a small-capacity memory can be identified according to the relation between the first actual data and the second data.
In addition, it may also be determined whether the memory to be tested is a large-capacity memory or a small-capacity memory according to a relationship between second actual data and first data, for example, if the second actual data is equal to the first data, the capacity of the memory to be tested matches the capacity of the second memory. And if the second actual data is not equal to the first data, matching the capacity of the memory to be tested with the capacity of the first memory.
Specifically, in this step, as described above, the second data, such as 0x5555, may be written to the address 0x0, and then the first data, such as 0xAAAA, may be written to the address 0x 400. And then, extracting second actual data according to the address 0x0, wherein if the actual data extracted from the second address 0x0 is 0xAAAA, it indicates that the address 0x400 and the address 0x0 are written into the same storage unit, the two addresses are mirror addresses, and the memory to be tested is a small memory, namely, the second memory. On the contrary, if the first actual data extracted from the second address 0x0 is not 0xAAAA, it indicates that the addresses 0x400 and 0x0 are not the same memory unit, and the two addresses are not mirror addresses, and the memory to be tested is a large memory, that is, the first memory. Therefore, whether the memory to be tested is a large-capacity memory or a small-capacity memory can be identified according to the relation between the first actual data and the second data.
The memory capacity identification method of the present invention will be specifically described below with a specific example.
Assuming that a product initially uses a manufacturer's 64 megabyte (64MByte) Double Data Rate SDRAM (DDR SDRAM for short), the original 64MByte cannot meet the software requirement later because of the service logic expansion. Then the replacement of the 128MByte DDR SDRAM, which is larger in capacity, is considered.
Generally, the inside of the DDR SDRAM consists of a block (bank), a column (column), and a row (row), where for easy understanding, the internal structure of the DDR SDRAM can be thought of as an Excel file, the bank is a worksheet, the column is a worksheet column, the row is a worksheet row, and one Excel file has multiple worksheets, each table has multiple rows and multiple columns. DDR SDRAM is accessed through a parallel bus, the internal address space of the DDR SDRAM is continuous, the address arrangement modes of different DDR SDRAM are possibly different, and only one memory unit can be uniquely determined as long as the values of bank, column and row are given.
As shown in FIG. 4 and Table 1 below, the DDR SDRAM of CPU with address coding sequence of column, row, bank, 128MByte has one more bank line than 64MByte DDR SDRAM, A0-A13 are used to select row, A0-A9 select column. Then, for the CPU, when the DDR SDRAM is 64MByte, the addressing range is 0x0 ~ 0x3FFFFFF, and when the DDR SDRAM is 128MByte, the addressing range is 0x0 ~ 0x7 FFFFFF. An address is selected in an addressing space of the DDR SDRAM exceeding 64MByte, for example 0x4000000, according to the DDR SDRAM addressing mode, the 64MByte DDR SDRAM has no Bank2 address line, namely bit26 bits of the address are floating, so bit26 of the address has no influence on the decoding of the 64MByte DDR SDRAM address no matter 0 or 1. Therefore, when the CPU issues an address of 0x4000000, the 64MByte DDR SDRAM gates the memory cell corresponding to bank ═ 0, row ═ 0, column ═ 0; when the CPU issues an address of 0x0000000, the 64MByte DDR SDRAM still gates the memory cell corresponding to bank 0, row 0, column 0. Therefore, two addresses 0x4000000 and 0x0000000 are mirror addresses.
TABLE 1
After determining that two addresses with mirror image relationship exist, writing 0x55AA5555 to the address of 0x4000000, then writing 0x55AAAA to the address of 0x0, and then reading 4 bytes of data from the address of 0x4000000, if the read value is 0x55AA5555, then proving that the address of 0x0 and the address of 0x4000000 do not point to the same block of memory cells, namely the DDR SDRAM has the capacity of 128 MByte; if the read value is 0x55AAAAAA, it is proved that the 0x0 address and the 0x4000000 address point to the same block of memory cells, i.e. the bank2 line is not valid, and the DDR SDRAM capacity is 64 MByte.
In another aspect of the present invention, as shown in fig. 5, an apparatus 100 for identifying a capacity of a memory to be tested is provided, where the memory to be tested includes a first memory and a second memory, and a capacity of the first memory is greater than a capacity of the second memory. The identification apparatus 100 can be applied to the identification methods described above, and reference may be made to the related descriptions, which are not described herein again. The identification apparatus 100 includes:
an address determining unit 110, configured to determine a first address, where the first address is greater than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory; and the CPU is further used for determining a mirror image address of the first address according to the coding rule of the second memory, wherein the mirror image address is smaller than or equal to the second addressing range, and the mirror image address refers to an address pointing to the same storage unit as the first address when the CPU accesses the second memory.
An identifying unit 120, configured to identify the capacity of the memory to be tested through read-write operations on the first address and the mirror address.
The device for identifying the capacity of the memory to be tested according to the embodiment finds out the first address and the mirror image address which have a mirror image relationship with respect to the second memory with small capacity according to the first memory and the second memory with known capacities, and then identifies the capacity of the memory to be tested through reading and writing operations on the first address and the mirror image address. The memory identification device provided by the embodiment of the invention has a simple structure, can also enable software to distinguish the capacity of the memory at the initial stage of initialization, and does not need to separately make identification marks of product models for distinguishing the memory capacity on hardware.
It should be noted that, as to how to specifically find the mirror image address in the mirror image relationship with the first address from the second memory, reference may be made to the detailed description in the identification method according to the embodiment of the present invention, which is not described herein again.
In some optional embodiments, the identifying unit 120 includes a writing subunit 121, a reading subunit 122, and an identifying subunit 123, and the identifying the capacity of the memory to be tested by performing a read-write operation on the first address and the mirror address includes:
the write subunit 121 is configured to write first data to the first address, and write second data to the mirror address;
the reading subunit 122 is configured to read first actual data from the first address, and read second actual data from the mirror address;
the identifying subunit 123 is configured to identify the capacity of the memory to be tested according to the first actual data and the second actual data.
In some optional embodiments, the identifying, according to the first actual data and the second actual data, the capacity of the memory to be tested includes:
the identification subunit 123 is configured to:
and if the first actual data is equal to the second data, matching the capacity of the memory to be tested with the capacity of the second memory. And if the first actual data and the second data are not equal, matching the capacity of the memory to be tested with the capacity of the first memory.
In addition, the identifying subunit 123 may also determine whether the memory to be tested is a large-capacity memory or a small-capacity memory according to a relationship between second actual data and the first data, for example, if the second actual data is equal to the first data, the capacity of the memory to be tested matches the capacity of the second memory. And if the second actual data is not equal to the first data, matching the capacity of the memory to be tested with the capacity of the first memory.
In another aspect of the present invention, an electronic device is provided, including:
one or more processors;
a storage unit for storing one or more programs which, when executed by the one or more processors, enable the one or more processors to implement the method according to the preceding description.
In another aspect of the invention, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, is adapted to carry out the method according to the above description.
The computer readable medium may be included in the apparatus, device, system, or may exist separately.
The computer readable storage medium may be any tangible medium that can contain or store a program, and may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, more specific examples of which include, but are not limited to: a portable computer diskette, a hard disk, an optical fiber, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may also include a propagated data signal with computer readable program code embodied therein, for example, in a non-transitory form, such as in a carrier wave or in a carrier wave, wherein the carrier wave is any suitable carrier wave or carrier wave for carrying the program code.
In another aspect of the invention, a computer program is provided, which when executed by a processor is capable of implementing the method according to the above description.
It will be appreciated that the computer program may be stored on a computer storage medium such as the Random Access Memory (RAM), Read Only Memory (ROM), erasable programmable read only memory (EPROM or flash memory), portable compact disc read only memory (CD-ROM), and the like, described above.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A method for identifying the capacity of a memory to be tested comprises a first memory and a second memory, wherein the capacity of the first memory is larger than that of the second memory, and the method comprises the following steps:
determining a first address, wherein the first address is larger than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory;
determining a mirror image address of the first address according to the coding rule of the second memory, wherein the mirror image address is smaller than or equal to the second addressing range, and the mirror image address refers to an address pointing to the same storage unit as the first address when the CPU accesses the second memory;
and identifying the capacity of the memory to be tested through the read-write operation of the first address and the mirror image address.
2. The method of claim 1, wherein the identifying the capacity of the memory to be tested through the read/write operations on the first address and the mirror address comprises:
writing first data into the first address, and writing second data into the mirror image address;
reading first actual data from the first address and reading second actual data from the mirror address;
and identifying the capacity of the memory to be tested according to the first actual data and the second actual data.
3. The method of claim 2, wherein the identifying the capacity of the memory under test according to the first actual data and the second actual data comprises:
if the first actual data is equal to the second data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the first actual data and the second data are not equal, matching the capacity of the memory to be tested with the capacity of the first memory.
4. The method of claim 2, wherein the identifying the capacity of the memory under test according to the first actual data and the second actual data comprises:
if the second actual data is equal to the first data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the second actual data is not equal to the first data, matching the capacity of the memory to be tested with the capacity of the first memory.
5. An apparatus for identifying a capacity of a memory to be tested, the memory to be tested including a first memory and a second memory, the capacity of the first memory being greater than the capacity of the second memory, the apparatus comprising:
an address determining unit, configured to determine a first address, where the first address is greater than a second addressing range of the second memory and smaller than or equal to a first addressing range of the first memory; and the number of the first and second groups,
the address determining unit is further configured to determine a mirror address of the first address according to a coding rule of the second memory, where the mirror address is smaller than or equal to the second addressing range, and the mirror address is an address pointing to the same storage unit as the first address when the CPU accesses the second memory;
and the identification unit is used for identifying the capacity of the memory to be tested through the read-write operation of the first address and the mirror image address.
6. The apparatus of claim 5, wherein the identifying unit comprises a writing subunit, a reading subunit and an identifying subunit, and wherein the identifying the capacity of the memory to be tested through the reading and writing operations on the first address and the mirror address comprises:
the writing subunit is configured to write first data to the first address, and write second data to the mirror address;
the reading subunit is configured to read first actual data from the first address, and read second actual data from the mirror address;
the identifying subunit is configured to identify the capacity of the memory to be tested according to the first actual data and the second actual data.
7. The apparatus of claim 6, wherein the identifying the capacity of the memory under test according to the first actual data and the second actual data comprises:
the identifier unit is specifically configured to:
if the first actual data is equal to the second data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the first actual data and the second data are not equal, matching the capacity of the memory to be tested with the capacity of the first memory.
8. The apparatus of claim 6, wherein the identifying the capacity of the memory under test according to the first actual data and the second actual data comprises:
the identifier unit is specifically configured to:
if the second actual data is equal to the first data, the capacity of the memory to be tested is matched with the capacity of the second memory;
and if the second actual data is not equal to the first data, matching the capacity of the memory to be tested with the capacity of the first memory.
9. An electronic device, comprising:
one or more processors;
a storage unit to store one or more programs that, when executed by the one or more processors, cause the one or more processors to implement the method of any of claims 1-4.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, is able to carry out a method according to any one of claims 1 to 4.
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