JPH09274612A - Vector processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten set time by directly performing the set of scalar data to a scalar register at a vector processor corresponding to a vector instruction. SOLUTION: As a pair of vector instructions, a VLI instruction for setting immediate value data to the low-order 32 bits of the scalar register and a VLIS instruction for setting immediate value data to the high-order 32 bits of the scalar register are prepared, these instructions are composed of OP codes, scalar register numbers to be set and immediate data and by decoding the instructions, the immediate value data are set to the low-order side of register 2371 and the high-order side of a register 2372 at a data control circuit. When executing the instruction, in the case of VLI instruction, the data in the register 2371 are selected and these data are written in the scalar register to be set by a selection circuit. In the case of VLIS instruction, the data in the register 2372 are selected and the data are written in the scalar register to be set by the selection circuit but only the high-order part of data is written corresponding to the designation of a set signal control circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device suitable for speeding up processing when a large amount of scalar data is required, such as function calculation often appearing in scientific and technological calculations.

[0002]

2. Description of the Related Art In order to set scalar data in a scalar register, a conventional vector processing device uses a vector processing preparation instruction LMS (Load Multiple S).
read from the main storage device,
Data was set in the scalar register via the storage control unit and the data transfer circuit. Therefore, if the number of scalar data to be set is large in addition to passing through each unit, waiting may occur due to contention for main memory access or contention for banks on the main memory. It was hanging. Generally, in function calculation, a large amount of scalar data is required in the coefficient part, and a large number of scalar registers are used. Therefore, in the conventional vector processing apparatus, when a function comes out in the DO loop, after the vector processing before the function ends, the vector processing is started again, the value of the scalar register is reset, and the function After the processing was completed, the vector processing was started again, and the value of the scalar register used in the vector processing after the function was reset. That is, vector processing is started at least three times in one DO loop, and in the function part, a large amount of scalar data is read from the main storage device and stored in the scalar register via the storage control unit and the data transfer circuit. Because it was set,
The processing time was long.

[0003]

In the prior art, since the data was read from the main memory and set in the scalar register when the vector processing was started, the number of required scalar data such as the coefficient of the function calculation is required. If the number of vector processing is large, it takes a long time to start the vector processing, and in the processing of the loop including the function, it is necessary to perform the vector processing starting a plurality of times, and the ratio of the vector processing starting time to the total vector processing time is large. It has become high and hinders the speeding up of vector processing. An object of the present invention is to reduce scalar setup time at the time of starting vector processing by directly specifying scalar data required for function calculation by a vector instruction and setting it in a scalar register in the vector processor. The purpose is to enable high-speed calculation by reducing the number of vector processing activations.

[0004]

To achieve the above object, the present invention is a vector processing device for executing a vector instruction for setting immediate data of a scalar in a scalar register, wherein the vector instruction includes an operation code,
It has a scalar register number to be set and immediate data, and the instruction execution determination circuit decodes the vector instruction, transfers the immediate data to the data control circuit, transfers the other part to the vector instruction register, and executes the instruction. The control unit selects the scalar register having the scalar register number by the selection circuit according to the contents of the vector instruction register in response to the instruction activation and writes the immediate data in the data control circuit. The vector instruction is composed of a pair of VLI instruction and VLIS instruction, and the VLI instruction is
It has an operation code, a scalar register number to be set, and immediate data of the lower part of the scalar register,
The VLIS instruction has an operation code, a scalar register number to be set, and immediate data of the upper side portion of the scalar register. The instruction execution determination circuit decodes the VLI instruction or the VLIS instruction to control the immediate data. The lower part of the first register and the upper part of the second register of the circuit are transferred, and the other part of the instruction is transferred to the vector instruction register. In the case of the VLI instruction, the data of the first register in the data control circuit is selected by the selector and transferred to the selection circuit, and the scalar register of the scalar register number is selected by the selection circuit to write the data. , VLIS instruction, the data in the second register in the data control circuit is selected by the selector. Transferred to 択回 path, so that the selected scalar register scalar register number, and writes only the upper portion of the data under the control of the set signal the control circuit by the selection circuit.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below. FIG. 1 is an overall configuration diagram showing an embodiment of a vector processing device of the present invention. 1 is a scalar processor, 2 is a vector processor, 3 is a storage control unit,
Reference numeral 4 is a main storage device. The vector processor 2 includes a vector instruction buffer 21 and a vector address register 2
2, instruction execution determination circuit 23, vector instruction register 2
4, activation control unit 25, instruction execution control unit 26, vector arithmetic unit 271, post-processing arithmetic unit 272, vector register 2
8, a scalar register 29, and a data transfer circuit 210. Although only one vector calculator 271 and data transfer circuit 210 are shown in the figure, there may actually be more than one.

In FIG. 1, the scalar processor 1 activates the vector processor 2 when the vector processing has to be performed. At this time, the scalar processor 1 processes the vector processing preparation instruction. Examples of vector processing preparation instructions include the following instructions. LMA (Load Multiple Vector Address & Increment)
Instructions LMB (Load Multiple Vector Base) Instructions These instructions both set the data (address) in the main storage device 4 to the vector address register 22 via the storage control unit 3. LMS (Load Multiple Scalar) instruction This instruction sets the data (scalar data) in the main storage device 4 to the scalar register 29 via the storage control unit 3. EXVP (Execute Vector Processing) Command This command instructs the vector processor 2 to start vector processing. The scalar processor 1 sequentially processes such vector processing preparation instructions.

In the processing of the LMS instruction, the scalar data in the main memory 4 is set in the scalar register 29 through the storage control unit 3 and the selection circuit 291. In addition to the scalar data from the main storage device 4, the selection circuit 291 is a scalar data designated by the scalar data from the scalar processor 1 and the calculation result obtained by the post-processing calculator 272 such as inner product and sum. Set in register 29. At the same time that the data is set in the scalar register 29, the corresponding Valid bit is also set to 1. The Valid bit is provided one bit at a time corresponding to each register of the scalar register 29, and when data is set in the scalar register 29, the corresponding V
The value of the alid bit is set to 1. This makes it possible to manage whether or not the setting of the scalar data to the scalar register 29 is completed.

Further, in the processing of the EXVP instruction, the vector processing start signal 12 is sent to the vector processor 2, the vector instruction string is read from the head address of the vector instruction string in the main memory 4, and the vector instruction buffer is read. 21 is set. Since the end of setting the scalar data in the scalar register 29 is managed by the Valid bit, the vector process start can be started without waiting for the end of the data setting in the scalar register 29.

In the instruction execution determination circuit 23, when the instruction decoder 231 receives the vector processing start signal 12, it fetches one vector instruction from the leading fetch position of the vector instruction buffer 21 and decodes it. In the instruction decoder 231 of FIG. 1, the format of the decoding result of the fetched vector instruction is shown. In this, OP is an operation code indicating the type of operation, R
N1 to RN3 are register designating sections for designating vector register numbers or scalar register numbers, and VAIRN and VBRN are vector address register designating sections for designating vector address register numbers. Further, the format shown in the vector instruction register 24 is also the same, but ALN is a vector arithmetic unit designating section for designating a vector arithmetic unit to be used in this vector instruction.
TRN is a data transfer circuit designating section that designates a data transfer circuit used in this vector instruction.

The instruction decoder 231 sends the decoding result to the conflict check circuit 235 to determine whether the decoded vector instruction can be executed. To determine whether the vector instruction is executable, the vector register 2 specified by the fetched vector instruction is used.
8 and the scalar register 29, the vector arithmetic unit 271 for performing the operation designated by the vector instruction, and the data transfer circuit 210 need to be open. Therefore, the result of the display circuit 234 is used to perform the conflict check. Do. The display circuit 234 uses the vector calculator 27.
1, each of the vector register 28, the scalar register 29, and the data transfer circuit 210 is provided with one indicator, which indicates whether or not they are in use. The conflict check circuit 235 refers to these indicators to refer to the vector register 28 and the scalar register 2 specified by the fetched vector instruction.
9. It is checked whether or not the vector calculator 271 and the data transfer circuit 210 for performing the operation designated by the vector instruction are available, and when it is detected that all the necessary ones are available, the vector instruction is executed. When it is determined that it is possible, the signal line 341 is transmitted to the activation control unit 25, and the decoding result of the vector instruction is transmitted to the vector instruction register 24 through the signal line 342. In that case, the indicators corresponding to the vector register 28, the scalar register 29, the vector calculator 271, and the data transfer circuit 210 used in the vector instruction are set so as to indicate that they are in use. To do. When you need something, wait until it's free.

If the scalar register 29 is designated by the vector instruction, the designated scalar register 29 is designated by the Valid bit read control circuit 232.
An instruction to read the value of the Valid bit corresponding to is sent to the scalar register 29 via the signal line 39, and
Read the value of d bits. The SR setup check circuit 236 determines whether or not data setting is completed for the specified scalar register 29 based on the value of the read Valid bit. The value of the Valid bit corresponding to the specified scalar register 29 is 1
In addition, as a result of the conflict check, the scalar register 29 and the vector register 28 designated by the vector instruction, the vector computing unit 271 for performing the computation designated by the vector instruction, and the data transfer circuit 210 are all empty. If so, it is determined that the vector instruction is executable, the determination result is sent to the activation control unit via the signal line 351, and the decoding result of the vector instruction is transmitted via the signal line 352 to the vector instruction register 24.
To send to. If the value of the Valid bit is 0, the data is not yet set in the specified scalar register 29, and therefore the vector instruction is not executed until the value of the Valid bit becomes 1.

The activation control unit 25 includes an instruction execution determination circuit 23.
When the signal line 341 or 351 is received from, the activation signal 56 is sent to the instruction execution control unit 26. When the instruction execution control unit 26 receives the activation signal 56, it fetches one vector instruction from the vector instruction register 24,
A vector calculator 271 designated by the vector instruction,
The vector register 28, the scalar register 29, and the data transfer circuit 210 are caused to perform vector processing operations.

Normal vector processing is performed as described above. In such a vector processing device,
Consider processing a DO loop as follows.

[0014]

[Equation 1]

Generally, in function calculation, a large amount of scalar data is required in the coefficient portion, and a large number of scalar registers 29 are used. Therefore, when a function appears in such a DO loop, vector processing is started again after (vector processing) before the function is completed, and the scalar register 2
The value of 9 must be reset, and further, after the processing of the function is finished, the vector processing must be started again and the value of the scalar register 29 used in (vector processing) after the function must be reset. This allows
In the DO loop process, the vector process start time is long in addition to the vector process execution time, and moreover, a large amount of scalar data is read out from the main storage device and stored in the scalar register 29 via the storage control unit 3. It has to be set, which increases processing time. But,
In the present invention, by newly providing two vector instructions and providing a configuration for executing these instructions, it is possible to start the vector processing once even in the processing of such a DO loop, and a large number of The time for setting the scalar data in the scalar register 29 can be greatly shortened.

FIG. 2 shows the specifications of two newly provided vector instructions. In the VLI instruction, immediate data is set in the lower 32 bits of the scalar register 29, and the VLI
In the S instruction, immediate data is set in the upper 32 bits of the scalar register 29. However, these two vector instructions are always used as a set. FIG. 3 shows FIG.
FIG. 3 is a diagram showing a constituent part for executing two newly-established vector instructions in FIG. 3, and is a diagram showing in detail along a data flow from the data control circuit 237 to the scalar register 29.

The processing operation of two vector instructions will be described below with reference to FIGS. 1 and 3. In FIG. 1, in the instruction execution determination circuit 23, when the instruction decoder 231 receives the vector processing start signal 12, it fetches and decodes one vector instruction from the leading fetch position of the vector instruction buffer. The instruction decoder 231 is provided with means for decoding the VLI instruction and the VLSI instruction. If the fetched vector instruction is the VLI instruction or the VLIS instruction, the valid bit read control circuit 232 is activated, and the valid bit read control circuit 232 reads out the value of the valid bit corresponding to the specified scalar register 29. Is transmitted through the signal line 39, and the value of the Valid bit is read. In addition,
In FIG. 3, the illustration of the Valid bit read control circuit 232 and the Valid bit read signal line from the scalar register 29 is omitted. On the other hand, the instruction decoder 23
1 sends the 32 bits of immediate data designated by the VLI instruction or the VLIS instruction to the data control circuit 237.

As shown in FIG. 3, the data control circuit 237.
Then, 64-bit data 2371 in which 32-bit all'0 'data is added to the upper 32-bit data received from the instruction decoder 231, and 32-bit all'0' data in the lower 32-bit data are added. The added 64-bit data 2372 is generated. In the SR setup check circuit 236, the read Vali
If the value of the d bit is 0, it is determined that writing to the scalar register 29 is possible, a signal of the determination result is sent to the activation control unit 25 via the signal line 651, and the decoding result of the operation code or the like is sent to the signal line. 652 to the vector instruction register 24.

Upon receiving the signal line 651, the activation control unit 25 sends an activation signal to the instruction execution control unit 26 via the signal line 56. When the instruction execution control unit 26 receives the activation signal, it fetches one vector instruction from the vector instruction register 24, and this fetches one vector instruction or VLI instruction.
When it is confirmed that it is the S instruction, the data control circuit 237
On the other hand, a signal for activating the select signal generation circuit 2374 is sent out via the signal line 671, and at the same time, an operation code is sent out via the signal line 672.
In the data control circuit 237, 64-bit data 2371
And one of the 64-bit data 2372 is selected by the selector 2373. The select signal is generated by the select signal generation circuit 2374 by the input of the activation signal from the signal line 671 and the operation code from the signal line 672. 6 for VLI instructions
In the case of the VLIS instruction so as to select the 4-bit data 2371, the select signal is generated by the select signal generation circuit 2374 so as to select the 64-bit data 2372.

Further, the instruction execution control unit 26 includes a selection circuit 2
A signal for instructing 91 to write 64-bit data to the specified scalar register 29 is sent to the signal line 69.
Send by 1 At the same time, the scalar register 29
To the set signal control circuit 294 which controls the set signal to the signal line 69
The operation code is transmitted according to 3. In the case of the VLIS instruction, the set signal control circuit 294 inhibits the set signal to the lower 32 bits so that only the upper 32 bits of the 64-bit data are written according to the content of the operation code. For VLI instructions,
Nothing is done because all 64-bit data is written.
In this way, the immediate data 32 bits specified by the VLI instruction are transferred to the lower 32 bits of the specified scalar register 29, and the immediate data 32 bits specified by the VLI instruction are transferred to the upper 32 bits of the specified scalar register 29. Written to bits. At the same time as writing to the scalar register 29 by the VLIS instruction, the value of the Valid bit corresponding to the scalar register 29 is set to 1
To

Here, the value of the Valid bit corresponding to the scalar register 29 designated by the VLI instruction and the VLI instruction must be 0 before writing the immediate data, but the Valid bit read control circuit 232.
If the value read by is due to a bug in the compiler or some kind of hardware failure, overwrite the specified scalar register 29 in the same procedure as when the Valid bit value is 0. Do.
The Valid bit that becomes 1 is reset by the compiler after the vector processing is completed.

As described above, the VLI instruction and the VL
By setting two vector instructions of the IS instruction and providing a configuration necessary for executing these instructions, the immediate data designated by the vector instruction is set in the scalar register 29 in the vector processor 2. Therefore, it is possible to set the scalar data read from the main storage device 4 in a short time as compared with the case where the scalar data is set in the scalar register 29 via the storage control unit 3.

[0023]

According to the present invention, immediate data of a scalar can be directly specified by a vector instruction and set in a scalar register in a vector processor, and a large number of scalars such as function calculation can be obtained. When data is required, the setup time of the scalar at the time of starting the vector process can be shortened, and at the same time, the number of times of the vector process start of the DO loop including the function calculation etc. can be reduced, and the vector process can be speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration showing an embodiment of a vector processing device of the present invention.

FIG. 2 is a diagram showing specifications of a vector instruction newly provided in the present invention.

FIG. 3 is a diagram showing components that execute two newly provided vector instructions.

[Explanation of symbols]

 1 Scalar Processor 2 Vector Processor 3 Storage Control Unit 4 Main Memory 21 Vector Instruction Buffer 22 Vector Address Register 23 Instruction Execution Judgment Circuit 24 Vector Instruction Register 25 Startup Control Section 26 Instruction Execution Control Section 28 Vector Register 29 Scalar Register 210 Data Transfer Circuit 237 data control circuit 271 vector operation unit 281, 282, 291, 292 selection circuit

Claims (2)

[Claims] 1. A vector processing device for executing a vector instruction for setting scalar immediate data to a scalar register, wherein the vector instruction has an operation code, a scalar register number to be set, and immediate data. The execution determination circuit decodes the vector instruction,
The immediate data is transferred to the data control circuit, the other part is transferred to the vector instruction register, and the instruction execution control unit follows the contents of the vector instruction register in response to the instruction activation and selects the scalar register of the scalar register number by the selection circuit. A vector processing device which is selected and writes immediate data in the data control circuit. 2. A vector processing device for executing a vector instruction for setting scalar immediate data in a scalar register, wherein the vector instruction comprises a pair of a VLI instruction and a VLIS instruction, and the VLI instruction is an operation code. And a scalar register number to be set and immediate data of the lower side portion of the scalar register. The VLIS instruction has an operation code, a scalar register number to be set, and immediate data of the upper side portion of the scalar register. The instruction execution determination circuit decodes the VLI instruction or the VLIS instruction and outputs immediate data to the first of the data control circuits.
The lower part of the register and the upper part of the second register, the other part of the instruction is transferred to the vector instruction register, and the instruction execution control unit follows the contents of the vector instruction register in response to instruction activation In the case of, the data of the first register in the data control circuit is selected by the selector and transferred to the selection circuit, and the selection circuit selects the scalar register of the scalar register number to write the data, and the VLIS instruction In this case, the data in the second register in the data control circuit is selected by the selector and transferred to the selection circuit, the scalar register having the scalar register number is selected by the selection circuit, and the data is controlled by the set signal control circuit. A vector processing device, characterized in that only the upper part of the data is written to the.